AN.No.G1216B1N000-3D0E
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(3) X-address (page) set
DB
0
Code
D/I
DB
7
1
0
1
1
1
A
A
A
R/W
0
0
Upper bits
Lower bits
The display data RAM “X” address (page) which is expressed with binary AAA is set in the X-address
register. Following write/read operations from the MPU are performed on the specified X-address
(page) until the next X-address (page) set is performed. The configuration of display data RAM and
X-address is shown in Figure 9.
DB
0
Code
D/I
DB
7
0
1
A
A
A
A
A
A
R/W
0
0
Upper bits
Lower bits
(4) Y-address set
The display data RAM Y- address which is expressed with binary AAAAAA is set in the Y-address
counter. After that the Y-address counter advances by one each time write/read is performed from
the MPU. The configuration of the display data RAM and Y-address is shown in Figure 9.
Page 0
Y-address
DB
0
to
DB
7
X=0
Page
1
DB
0
to
DB
7
X=1
Page 6
DB
0
to
DB
7
X=6
Page 7
DB
0
to
DB
7
X=7
0
1
2
3
4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
61 62 63
Figure 9 Display Data RAM Address Configuration
