background image

Chapter 5
 
Schematics

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D

D

C

C

B

B

A

A

Eval-J-Link-OB-STM32F205R-STM32F072C

A

VK

1

1

-

SE G G ER

www.segger.com

J-Link

TM

Technology

Title

Size

Date:
File:

Revision

Sheet

/

03.03.2014

Drawn:

A3

History / Changes

Number

Eval_J_Link_OB_STM32F205R_STM32F072C_RevA.SchDoc

SWO

GND

VCC3V3

GND

VDD, VDDA decoupling

GND

VCC3V3

GND

VCC3V3

VIN

1

GND

2

CE

3

VOUT

5

nc

4

U3

XC6219B332MRN

LED_OB

LTST-C170KGKT

C3
100n

C4
100n

C5
100n

C2
1u

C1

100n

C7
4u7/6V3

C6
4u7/6V3

R1

10k

GND

R3

220R

R2

220R

VCC3V3

GND

#RESET_OB

SWO

GND

Target MCU

USB OB

#RESET_OB

VCC3V3

GND

J-Link OB Programming Pads

SWCLK_OB

SWDIO_OB

For programming of OB no connector is
required. Programming is performed using
the "J-Link 6 Pin Adapter" from SEGGER.

VCC

1

DN

2

DP

3

ID

4

GND

5

A
B
C
D

J1

USB_MINI_B

R

W

L

SWCLK_OB

SWDIO_OB

GND

GND

X1

DNP

C17
DNP

C16
DNP

R

6

D

N

P

GND

VCC3V3

VDD, VDDA decoupling

C12
100n

C13
100n

C14
100n

C15
100n

C11
100n

VCC3V3

SWDIO
SWCLK

SWO

#RESET

#RESET

OB MCU

Pin Header Port A

PA0
PA1
PA2
PA3
PA4

PA5
PA6
PA7

PA8
PA9
PA10
PA11
PA12

PB0
PB1
PB2

PB5
PB6
PB7

PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15

VCC3V3

LED2

LTST-C170KGKT

R5

220R

LED1

LTST-C170KGKT

R4

220R

LEDs

PC5

PC4

PA[15..0]

PB[15..0]

PC[15..0]

D_P

D_N

SWDIO

SWCLK

#RESET

SWDIO

BOOT0

60

NRST

7

PH0-OSC_IN

5

PH1-OSC_OUT

6

PA0-WKUP

14

PA1

15

PA2

16

PA3

17

PA4

20

PA5

21

PA6

22

PA7

23

PA8

41

PA9

42

PA10

43

PA11

44

PA12

45

PA13

46

PA14

49

PA15

50

PB0

26

PB1

27

PB2

28

PB3

55

PB4

56

PB5

57

PB6

58

PB7

59

PB8

61

PB9

62

PB10

29

PB11

30

PB12

33

PB13

34

PB14

35

PB15

36

PC0

8

PC1

9

PC2

10

PC3

11

PC4

24

PC5

25

PC6

37

PC7

38

PC8

39

PC9

40

PC10

51

PC11

52

PC12

53

PC13

2

PC14-OSC32_IN

3

PC15-OSC32_OUT

4

PD2

54

U2A

STM32F205RCT6

VBAT

1

VDD_2

48

VDD_3

64

VDD_4

19

VDDA

13

VCAP_1

31

VCAP_2

47

VSS_3

63

VSS_4

18

VDD_1

32

VSSA

12

U2B

STM32F205RCT6

C8
2u2/4V
C9
2u2/4V

PB4

GND

GND

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

C

DNP

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

A

DNP

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

B

DNP

VCC3V3

PC0
PC1

PC2
PC3
PC4
PC5
PC6
PC7

PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15

GND

VCC3V3

GND

VCC3V3

GND

Pin Header Port B

Pin Header Port C

PA15

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PA8

PA9

PA10

PA11

PA12

PA15

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PC8

PC9

PC10

PC11

PC12

PC13

PC14

PC15

PB0

PB1

PB2

PB5

PB6

PB7

PB8

PB9

PB10

PB11

PB12

PB13

PB14

PB15

PB4

C10
4u7/6V3

U

VTref

1

SWDIO

2

#RES

3

SWCLK

4

GND

5

SWO

6

J2

TC2030-IDC

VUSB

VUSB

*
*
*

* PC13, PC14, PC15 only provide limited drive
capability and cannot source current.

Note:

J-Link OB

SWCLK

Not Assembled

SWO

SWDIO

SWCLK
#RESET

Not Assembled

Power Supply

Application

BOOT0

44

NRST

7

PF0/OSC_IN

5

PF1/OSC_OUT

6

PA0

10

PA1

11

PA2

12

PA3

13

PA4

14

PA5

15

PA6

16

PA7

17

PA8

29

PA9

30

PA10

31

PA11

32

PA12

33

PA13/SWDIO

34

PA14/SWCLK

37

PA15

38

PB0

18

PB1

19

PB2

20

PB3

39

PB4

40

PB5

41

PB6

42

PB7

43

PB8

45

PB9

46

PB10

21

PB11

22

PB12

25

PB13

26

PB14

27

PB15

28

PC13

2

OSC32_IN/PC14

3

OSC32_OUT/PC15

4

VBAT

1

VDD_1

24

VDDIO2

36

VDD_2

48

VDDA

9

VSS_1

23

VSS_3

35

VSS_2

47

VSSA

8

EP

EP

U1

STM32F072CxU6

Rev. A:
- Changed pinning for target interface
- Added Virtual COM Port

PA9

PA10
PA12
PA11

RxD

TxD

RTS

CTS

RxD

TxD

RTS
CTS

Virtual COM Port:
- Option 1: Do not connect (VCOM support not needed)
- Option 2: Connect RxD/TxD only
- Option 3: Connect all 4 signals (VCOM incl. HW flow control)

J-Link-OB-STM32F072-128KB-Cortex-M User Guide
(UM08029)

© 2004-2017 SEGGER Microcontroller GmbH

Summary of Contents for J-Link-OB-STM32F072-128KB

Page 1: ...J Link OB STM32F072 128KB Cortex M User guide of the onboard debug probe based on STM32F072Cx MCU Document UM08029 Revision 1 Date January 18 2018 A product of SEGGER Microcontroller GmbH www segger com ...

Page 2: ... or fitness for a particular purpose Copyright notice You may not extract portions of this manual or modify the PDF file in any way without the prior written permission of SEGGER The software described in this document is furnished under a license and may only be used or copied in accordance with the terms of such a license 2004 2017 SEGGER Microcontroller GmbH Hilden Germany Trademarks Names ment...

Page 3: ... and we will try to assist you as soon as possible Contact us for further information on topics that are not yet documented Print date January 18 2018 Manual version Revision Date By Description 0 00 1 171012 NG Initial Version J Link OB STM32F072 128KB Cortex M User Guide UM08029 2004 2017 SEGGER Microcontroller GmbH ...

Page 4: ...4 J Link OB STM32F072 128KB Cortex M User Guide UM08029 2004 2017 SEGGER Microcontroller GmbH ...

Page 5: ... macros that the product offers It assumes you have a working knowledge of the C language Knowledge of assembly programming is not required Typographic conventions for syntax This manual uses the following typographic conventions Style Used for Body Body text Keyword Text that you enter at the command prompt or that appears on the display that is system functions file or pathnames Parameter Parame...

Page 6: ...6 J Link OB STM32F072 128KB Cortex M User Guide UM08029 2004 2017 SEGGER Microcontroller GmbH ...

Page 7: ...pported target interfaces 10 3 1 Target interface pins 11 3 2 Target interface SWD 12 3 3 Target interface VCOM 13 4 Compatible MCUs as J Link OB host 14 5 Schematics 15 6 Glossary 16 J Link OB STM32F072 128KB Cortex M User Guide UM08029 2004 2017 SEGGER Microcontroller GmbH ...

Page 8: ...d manufacturers J Link OB can be used with the same software package as the general J Links and can be used with the same utilities as far as the feature set of the J Link OB supports this Note It is not allowed to use J Link OB STM32F072 128KB Cortex M for stand alone em ulators J Link OB STM32F072 128KB Cortex M User Guide UM08029 2004 2017 SEGGER Microcontroller GmbH ...

Page 9: ...ported target CPU cores For a list of cores supported by this J Link OB model please refer to here J Link OB Model overview J Link OB STM32F072 128KB Cortex M User Guide UM08029 2004 2017 SEGGER Microcontroller GmbH ...

Page 10: ...rfaces The J Link OB STM32F072 128KB Cortex M supports the following target interfaces SWD SWO It may only be used with Cortex M target CPUs J Link OB STM32F072 128KB Cortex M User Guide UM08029 2004 2017 SEGGER Microcontroller GmbH ...

Page 11: ...A10 Pin 31 CTS PA7 Pin 17 RTS PA6 Pin 16 Which signals are required depends on what features shall be supported on the evaluation board If support for a specific feature or interface is not required the spare pins should be left open For more information about which target interface requires which signals please refer to the following sections J Link OB STM32F072 128KB Cortex M User Guide UM08029 ...

Page 12: ... following signals need to be connected RESET PA1 Pin 11 SWCLK PA2 Pin 12 SWO PA3 Pin 13 SWDIO PA4 Pin 14 If SWO support is not required e g when the target CPU is Cortex M0 M0 based which does not provide SWO support the SWO signal can be left open J Link OB STM32F072 128KB Cortex M User Guide UM08029 2004 2017 SEGGER Microcontroller GmbH ...

Page 13: ...fer to J Link VCOM functionality If VCOM optional hardware flow control support is required on the target hardware to be designed the following signals need to be connected TXD PA9 Pin 30 RXD PA10 Pin 31 CTS PA7 Pin 17 RTS PA6 Pin 16 If hardware flow control support is not required the CTS and RTS signal can be left open J Link OB STM32F072 128KB Cortex M User Guide UM08029 2004 2017 SEGGER Microc...

Page 14: ... series MCUs The following microcontrollers are compatible to this J Link OB model ST STM32F072CB LQFP 48 ST STM32F072CB UFQFPN 48 ST STM32F072CB WLCSP 49L ST STM32F072RB LQFP 64 ST STM32F072RB UFBGA 64L ST STM32F072VB LQFP 100 ST STM32F072VB UFBGA 100 J Link OB STM32F072 128KB Cortex M User Guide UM08029 2004 2017 SEGGER Microcontroller GmbH ...

Page 15: ...1 52 PC12 53 PC13 2 PC14 OSC32_IN 3 PC15 OSC32_OUT 4 PD2 54 U2A STM32F205RCT6 VBAT 1 VDD_2 48 VDD_3 64 VDD_4 19 VDDA 13 VCAP_1 31 VCAP_2 47 VSS_3 63 VSS_4 18 VDD_1 32 VSSA 12 U2B STM32F205RCT6 C8 2u2 4V C9 2u2 4V PB4 GND GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 C DNP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A DNP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 B DNP ...

Page 16: ...Chapter 6 Glossary This chapter describes important terms used throughout this manual J Link OB STM32F072 128KB Cortex M User Guide UM08029 2004 2017 SEGGER Microcontroller GmbH ...

Page 17: ...in a JTAG chain TDO The electronic signal output from a TAP controller to the data sink downstream Usually the TDO signal of J Link is connected to the TDO of the last TAP controller in a JTAG chain TMS The electronic signal Test Mode Select is an input to the TAP controller and it is used to select different stages of state machine It is clocked in into the TAP controller using the TCK signal ups...

Page 18: ...k OB STM32F072 128KB Cortex M is able to receive the data in asynchronous mode when SWO of the target CPU is connected to the SWOin signal of J Link OB STM32F072 128KB Cortex M Normally the SWO output signal of a Cortex M CPU is directed via the TDO signal pin but may be separated on some devices J Link OB STM32F072 128KB Cortex M User Guide UM08029 2004 2017 SEGGER Microcontroller GmbH ...

Reviews: