Segger J-Link ARM User Manual Download

Page: 67 / 274

J-Link / J-Trace (UM08001)

2004-2012 SEGGER Microcontroller GmbH & Co. KG

3.2.4

J-Link STM32 Commander (Command line tool)

J-Link STM32 Commander (

JLinkSTM32.exe

) is a free command line tool which can

be used to disable the hardware watchdog of STM32 devices which can be activated

by programming the option bytes. Moreover the J-Link STM32 Commander unsecures

a read-protected STM32 device by re-programming the option bytes.

Note:

Unprotecting a secured device or will cause a mass erase of the flash

memory.

Summary of Contents for J-Link ARM

Page 1: ...A product of SEGGER Microcontroller GmbH Co KG www segger com J Link J Trace User Guide Software Version V4 51a Manual Rev 0 Document UM08001 Date June 6 2012...

Page 2: ...in this doc ument is furnished under a license and may only be used or copied in accordance with the terms of such a license 2012 SEGGER Microcontroller GmbH Co KG Hilden Germany Trademarks Names men...

Page 3: ...AG Chapter J Link and J Trace related software Section J Link software and documentation package in detail updated Chapter Introduction Section Built in intelligence for supported CPU cores added V4 2...

Page 4: ...OEM versions updated 78 091023 AG Chapter Licensing Section J Link OEM versions updated 77 090910 AG Chapter Introduction Section J Link J Trace models updated 76 090828 KN Chapter Introduction Secti...

Page 5: ...nformation Section Embedded Trace Macrocell ETM updated Chapter J Link and J Trace related software Section Dedicated flash programming utilities for J Link updated 65 090320 AG Several changes in the...

Page 6: ...nks J Traces to your PC updated 47 080910 AG Chapter Licensing updated 46 080904 AG Chapter Licensing added Chapter Hardware Section J Link OEM versions moved to chapter Licensing 45 080902 AG Chapter...

Page 7: ...ection Introduction updated Section Licensing updated Section Using flash download and flash breakpoints with different debuggers updated 33 080207 AG Chapter Flash download and flash breakpoints adde...

Page 8: ...312 SK Chapter Hardware Differences between different versions supplemented 20 070307 SK Chapter J Link J Trace related software J Link GDB Server licensing updated 19 070226 SK Chapter J Link J Trace...

Page 9: ...e target board for trace added 8 060117 OO Chapter Related Software Added JLinkARM dll Screenshots updated 7 051208 OO Chapter Working with J Link Sketch added 6 051118 OO Chapter Working with J Link...

Page 10: ...10 J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG...

Page 11: ...FAQs on page 259 helps to troubleshoot common problems For simplicity we will refer to J Link ARM as J Link in this manual For simplicity we will refer to J Link ARM Pro as J Link Pro in this manual T...

Page 12: ...supporting the ARM ETM Embed ded Trace Macrocell J Link J Trace Related Software Add on software to be used with SEGGER s indus try standard JTAG emulator this includes flash programming software and...

Page 13: ...intelligence per model 42 1 7 Supported IDEs 44 2 Licensing 45 2 1 Introduction 46 2 2 Software components requiring a license 47 2 3 License types 48 2 3 1 Built in license 48 2 3 2 Key based licens...

Page 14: ...J Link Flash Software Developer Kit SDK 76 3 5 Using the J LinkARM dll 77 3 5 1 What is the JLinkARM dll 77 3 5 2 Updating the DLL in third party programs 77 3 5 3 Determining the version of JLinkARM...

Page 15: ...ing example 131 5 10 7 Executing J Link script files 131 5 11 Command strings 133 5 11 1 List of available commands 133 5 11 2 Using command strings 139 5 12 Switching off CPU clock during debug 141 5...

Page 16: ...ink RDI 190 8 5 4 Semihosting with AXD 190 8 5 5 Unexpected unhandled SWIs 191 9 Device specifics 193 9 1 Analog Devices 194 9 1 1 ADuC7xxx 194 9 2 ATMEL 196 9 2 1 AT91SAM7 197 9 2 2 AT91SAM9 199 9 3...

Page 17: ...cing and data tracing 245 11 2 3 J Trace integration example IAR Embedded Workbench for ARM 245 11 3 Embedded Trace Buffer ETB 249 11 4 Flash programming 250 11 4 1 How does flash programming via J Li...

Page 18: ...18 J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 15 Literature and references 271...

Page 19: ...J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 19 Chapter 1 Introduction This chapter gives a short overview about J Link and J Trace...

Page 20: ...00 or later For a list of all operating systems which are supported by J Link please refer to Supported OS on page 21 Target System A target system with a supported CPU is required You should make sur...

Page 21: ...ntroller GmbH Co KG 21 1 2 Supported OS J Link J Trace can be used on the following operating systems Microsoft Windows 2000 Microsoft Windows XP Microsoft Windows XP x64 Microsoft Windows Vista Micro...

Page 22: ...RM Pro J Trace ARM J Trace for Cortex M In the following the different J Link J Trace models are described and the changes between the different hardware versions of each model are listed To determine...

Page 23: ...ional license for flash download is required The flash breakpoint feature allows setting an unlimited num ber of breakpoints even if the application program is not located in RAM but in flash memory W...

Page 24: ...Hz JTAG speed 1 3 2 2 Specifications The following table gives an overview about the specifications general mechanical electrical for J Link ARM All values are valid for J Link ARM hardware version 8...

Page 25: ...0 MHz n 6 6 857 MHz n 7 6 000 MHz n 8 LOW level input voltage VIL VIL 40 of VIF HIGH level input voltage VIH VIH 60 of VIF For 1 8V VIF 3 6V LOW level output voltage VOL with a load of 10 kOhm VOL 10...

Page 26: ...ct both J Link and host computer Peak current 10 ms limit is 1A operating current limit is 300mA Version 5 4 Identical to version 5 3 with the following exception Supports 5V target interfaces Version...

Page 27: ...upplied Target power consumption can be measured with high accuracy External ADC can be connected via SPI 1 3 3 2 Specifications The following table gives an overview about the specifications general...

Page 28: ...rver Built in GDB Server planned to be implemented in the near future Serial Wire Debug supported Reset low level output voltage VOL VOL 10 of VIF For the whole target voltage range 1 8V VIF 5V LOW le...

Page 29: ...3 4 3 Hardware versions Version 1 1 Compatible to J Link ARM Provides an additional Ethernet interface which allows to communicate with J Link via TCP IP 1 3 5 J Link ARM Lite J Link ARM Lite is a fu...

Page 30: ...tec FTSH connector 3 3V target interface voltage General Supported OS For a complete list of all operating sys tems which are supported please refer to Supported OS on page 21 Electromagnetic compatib...

Page 31: ...s 41mm x 34mm x 8mm Weight without cables 6g Mechanical USB interface USB 2 0 full speed Target interface 19 pin 0 05 Samtec FTSH connector 9 pin 0 05 Samtec FTSH connector JTAG SWD Interface Electric...

Page 32: ...JTAG speed up to 12 MHz Download speed up to 420 Kbytes second DCC speed up to 600 Kbytes second Measured with J Trace ARM7 50 MHz 12MHz JTAG speed 1 3 7 2 Specifications for J Trace General Supported...

Page 33: ...Mea suring download speed on page 260 The actual speed depends on various factors such as JTAG clock speed host CPU core etc 1 3 7 4 Hardware versions Version 1 This J Trace uses a 32 bit RISC CPU Ma...

Page 34: ...h are supported please refer to Supported OS on page 19 Electromagnetic compatibility EMC EN 55022 EN 55024 Operating temperature 5 C 60 C Storage temperature 20 C 65 C Relative humidity non condensin...

Page 35: ...Power supply USB powered Max 50mA Target Supply current Target interface voltage VIF 1 2V 5V Voltage interface low pulse VIL Max 40 of VIF Voltage interface high pulse VIH Min 60 of VIF Trace Interfac...

Page 36: ...l speed Target interface JTAG SWD 20 pin JTAG Interface Electrical Power supply USB powered Max 50mA Target Supply current Target interface voltage VIF 1 2V 5V Target supply voltage 4 5V 5V if powered...

Page 37: ...lt in 26 pin BDM connector which is compatible to the standard 26 pin connector defined by Freescale For more infor mation about J Link ColdFire BDM 26 please refer to UM08009 J Link ColdFire BDM26 Us...

Page 38: ...AG Trace connector USB and 20 pin ribbon cable included Memory viewer J Mem included TCP IP server included which allows using J Trace via TCP IP networks RDI interface available which allows using J...

Page 39: ...M0 M1 M3 M4 and Cortex A5 A8 A9 R4 core If you experience problems with a particular core do not hesitate to contact Segger ARM7TDMI Rev 1 ARM7TDMI Rev 3 ARM7TDMI S Rev 4 ARM720T ARM920T ARM922T ARM9...

Page 40: ...nd since no intelligence for the CPU core is necessary in the J Link firmware This means all target sequences JTAG SWD are generated on the PC side and the J Link simply sends out these sequences and...

Page 41: ...can not be guaranteed in all cases especially if the target interface speed JTAG SWD is significantly higher than the CPU speed Poor performance Since a lot more data has to be transferred over the ho...

Page 42: ...ew about which model of J Link J Trace has intelligence for which CPU core 1 6 3 1 Current models The table below lists the firmware CPU support for J Link J Trace models currently available J Link J...

Page 43: ...lder J Link J Trace models which are not sold anymore J Link J Trace model Version ARM 7 9 ARM 11 Cortex A R Cortex M Renesas RX600 JTAG JTAG JTAG JTAG SWD JTAG J Link 3 not sup ported J Link 4 not su...

Page 44: ...no no CodeSourcery yes no no no Yargato GDB yes yes yes no RDI compliant toolchains such as RVDS ADS yes1 yes1 yes1 no IDE Debug support4 Flash download Flash breakpoints Trace support3 SWO support IA...

Page 45: ...2004 2012 SEGGER Microcontroller GmbH Co KG 45 Chapter 2 Licensing This chapter describes the different license types of J Link related software and the legal use of the J Link software with original...

Page 46: ...G 2 1 Introduction J Link functionality can be enhanced by the features J Flash RDI flash download and flash breakpoints FlashBP The flash breakpoint feature does not come with J Link and need an addi...

Page 47: ...Flash breakpoints FlashBP For more information about J Link RDI licensing procedure license types please refer to the J Link RDI User Guide UM08004 chapter Licensing For more information about J Flash...

Page 48: ...kpoints with other J Links every J Link needs a license Device based license The device based license comes with the J Link software and is available for some devices For a complete list of devices wh...

Page 49: ...l open and show all licenses both key based and built in licenses of J Link Now choose Add license to add one or more new licenses Enter your license s and choose OK Now the licenses should have been...

Page 50: ...k ARM FlashBP NXP LPC2102 J Link ARM FlashDL J Link ARM FlashBP NXP LPC2103 J Link ARM FlashDL J Link ARM FlashBP NXP LPC2104 J Link ARM FlashDL J Link ARM FlashBP NXP LPC2105 J Link ARM FlashDL J Lin...

Page 51: ...Link ARM FlashDL J Link ARM FlashBP NXP LPC2212 J Link ARM FlashDL J Link ARM FlashBP NXP LPC2214 J Link ARM FlashDL J Link ARM FlashBP NXP LPC2292 J Link ARM FlashDL J Link ARM FlashBP NXP LPC2294 J...

Page 52: ...nly be used with original SEGGER products and autho rized OEM products The use of the licensed software to operate SEGGER product clones is prohibited and illegal 2 4 1 Use of the software with 3rd pa...

Page 53: ...supported by the built in licenses please refer to Device list on page 50 2 5 2 J Link Ultra J Link Ultra is a JTAG SWD emulator designed for ARM Cortex and other supported CPUs It is fully compatibl...

Page 54: ...rod ucts J Link ARM FlashDL FlashBP RDI J Link GDB Server and J Flash 2 5 4 J Trace J Trace is a JTAG emulator designed for ARM cores which includes trace ETM support It connects via USB to a PC run n...

Page 55: ...ad and flash breakpoints for some devices For a complete list of devices which are supported by the built in licenses please refer to Device list on page 50 2 5 6 Flasher ARM Flasher ARM is a programm...

Page 56: ...does not support OEM versions support is provided by the respective OEM 2 6 1 Analog Devices mIDASLink mIDASLink is an OEM version of J Link sold by Analog Devices Limitations mIDASLink works with Ana...

Page 57: ...KS can not be used with Keil MDK This lim itation can NOT be lifted if you would like to use J Link with Keil MDK you need to buy a separate J Link IAR J Link does not sup port kickstart power Licens...

Page 58: ...ces This limita tion can NOT be lifted if you would like to use J Link with a device from an other manufacturer you need to buy a separate J Link Licenses No licenses are included 2 6 8 SEGGER J Link...

Page 59: ...single chip versions of J Link which are used on var ious evalboards It is legal to use J Link software with these boards provided that the eval board manufacturer has obtained a license from SEGGER T...

Page 60: ...nes of SEGGER products Manufacturing and selling these clones is an illegal act for various reasons amongst them trademark copyright and unfair business practise issues The use of illegal J Link clone...

Page 61: ...related soft ware This chapter describes Segger s J Link J Trace related software portfolio which cov ers nearly all phases of the development of embedded applications The support of the remote debug...

Page 62: ...r Free target memory viewer Shows the memory content of a running target and allows editing as well J Flash Stand alone flash programming application Requires an addi tional license For more informati...

Page 63: ...mand line tool that opens an svf file and sends the data in it via J Link J Trace to the target J Link Software Developer Kit SDK The J Link Software Developer Kit is needed if you want to write your...

Page 64: ...for simple analysis of the target system It permits some simple commands such as memory dump halt step go and ID check as well as some more in depths analysis of the state of the ARM core and the ICE...

Page 65: ...der to create the SWO output file which is th input file for the SWO Analyzer the J Link config file needs to be modified It should contain the following lines SWO SWOLogFile C TestSWO dat 3 2 3 J Lin...

Page 66: ...con troller even if a program is in flash which causes the ARM core to stall When starting the STR91x commander a command sequence will be performed which brings MCU into Turbo Mode While enabling the...

Page 67: ...2 exe is a free command line tool which can be used to disable the hardware watchdog of STM32 devices which can be activated by programming the option bytes Moreover the J Link STM32 Commander unsecur...

Page 68: ...ed to the J Link TCP IP Server via the command line 3 2 5 1 List of available commands The table below lists the commands accepted by the J Link TCP IP Server 3 2 5 2 port Syntax port Portno Example T...

Page 69: ...and SFRs Special Function Registers while the target is running This makes it pos sible to look into the memory of an ARM chip at run time RAM can be modified and SFRs can be written You can choose be...

Page 70: ...ices J Flash requires a additional license from Segger Even without a license key you can still use J Flash ARM to open project files read from connected devices blank check target memory verify data...

Page 71: ...n addition to its own license Evaluation licenses are available free of charge For further information go to our website or contact us directly Note The RDI software as well as flash breakpoints and f...

Page 72: ...al proto col The GDB Server translates the GDB monitor commands into J Link commands The GNU Project Debugger GDB is a freely available debugger distributed under the terms of the GPL It connects to a...

Page 73: ...cial and production pur poses you need to obtain a license from SEGGER SEGGER also offers to create ded icated flash programming utilities for custom hardware When starting a dedicated flash programmi...

Page 74: ...ies for pro duction and commercial purposes If you want to use dedicated flash programming utilities for production and commer cial purposes you need to obtain a license from SEGGER In order to obtain...

Page 75: ...possible A A The free dedicated flash programming utilities which come with J Link do not support custom hardware mIn order to use your own hardware with a dedicated flash programming utility SEGGER...

Page 76: ...DLL does not have API functions for flash programming However the functionality offered can be used to program flash In this case a flash loader is required The table below lists some of the included...

Page 77: ...ink DLL updater to update the JLinkARM dll in the IAR Embedded Workbench The IAR Embedded Workbench IDE is a high performance integrated development environment with an editor compiler linker debugger...

Page 78: ...context menu Click the Version tab to display information about the product ver sion 3 5 4 Determining which DLL is used by a program To verify that the program you are working with is using the DLL...

Page 79: ...Chapter 4 Setup This chapter describes the setup procedure required in order to work with J Link J Trace Primarily this includes the installation of the J Link software and documenta tion package whi...

Page 80: ...rocedure To install the J Link ARM software and documentation pack follow this procedure Note We recommend to check if a newer version of the J Link software and doc umentation pack is available for d...

Page 81: ...3 Accept the default installation path C Program Files SEG GER JLinkARM_V VersionNumber or choose an alternative location Confirm your choice with the Next button 4 The Choose options dialog is opene...

Page 82: ...n Complete dialog box appears after the copy process Close the installation wizard with the Finish button The J Link software and documentation pack is successfully installed on your PC 7 Connect your...

Page 83: ...s flashing After successful enumeration the LED stays on permanently Start the provided sample application JLink exe which should display the compila tion time of the J Link firmware the serial number...

Page 84: ...n about driver provider version date and digital signer 4 2 2 Uninstalling the J Link USB driver If J Link J Trace is not properly recognized by Windows and therefore does not enu merate it makes sens...

Page 85: ...J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 85 jlink USB and click the Change Remove button 3 Confirm the uninstallation process...

Page 86: ...J Link Configurator The J Link software and documentation package comes with a free GUI based utility called J Link Configurator which auto detects all J Links that are connected to the host PC via US...

Page 87: ...iguration page allows configuration of network related settings IP address subnet mask default gateway of J Link The user can choose between automatic IP assignment settings are provided by a DHCP ser...

Page 88: ...tup J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 4 4 FAQs Q How can I use J Link with GDB and Ethernet A You have to use the J Link GDB Server in order to connect to J Link via G...

Page 89: ...t identification method for current J Links J Link with hardware version 8 or later For re configuration of old J Links or for configuration of the IP settings use DHCP IP address subnet mask of a J L...

Page 90: ...as USB identification method and click the OK button The same dialog also allows configuration of the IP settings of the connected J Link if it supports the Ethernet interface Note When re configurin...

Page 91: ...nnecting to different J Links connected to the same host PC via USB In general when having multiple J Links connected to the same PC the J Link to connect to is explicitly selected by its serial numbe...

Page 92: ...ers software which does not provide such a functionality the J Link DLL automatically detects that mutliple J Links are connected to the PC and shows a selection dialog which allows the user to select...

Page 93: ...J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 93 Chapter 5 Working with J Link and J Trace This chapter describes functionality and how to use J Link and J Trace...

Page 94: ...ware Then start JLink exe which should now display the normal J Link J Trace related information and in addition to that it should report that it found a JTAG target and the target s core ID The scree...

Page 95: ...nk All J Links feature the main indicator Some newer J Links such as the J Link Pro Ultra come with additional input output Indicators In the following the meaning of these indicators will be explaine...

Page 96: ...mulator has been in idle mode for at least 7 seconds GREEN flashing at 1 Hz Emulator has a fatal error This should not normally hap pen Table 5 1 J Link single color main indicator Indicator status Me...

Page 97: ...information about the emulator to target connection 5 2 3 1 Bi color output indicator Indicator status Meaning GREEN Target voltage could be measured Target is connected ORANGE Target voltage could be...

Page 98: ...ices in the scan chain J Link J Trace can handle multiple devices in the scan chain This applies to hard ware where multiple chips are connected to the same JTAG connector As can be seen in the follow...

Page 99: ...J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 99 SEGGER J Flash configuration dialog This dialog box can be found at Options Project settings...

Page 100: ...ler GmbH Co KG SEGGER J Link RDI configuration dialog box This dialog can be found under RDI Configure for example in IAR Embedded Work bench For detailed information check the IAR Embedded Workbench...

Page 101: ...n the instruction registers of the devices before the tar get device IR len The position can usually be seen in the schematic the IR len can be found in the manual supplied by the manufacturers of the...

Page 102: ...of more than 10 MHz are not recommended 5 3 4 2 Automatic JTAG speed Selects the maximum JTAG speed handled by the TAP controller Note On ARM cores without synchronization logic this may not work rel...

Page 103: ...he Instrumentation Trace Macrocell ITM and Serial Wire Output SWO can be used to form a Serial Wire Viewer SWV The Serial Wire Viewer provides a low cost method of obtaining information from inside th...

Page 104: ...z 5MHz 3 33MHz J Link V7 Supported SWO input speeds are 6MHz n n 1 6MHz 3MHz 2MHz 1 5MHz Permitted combinations are SWO output SWO input Deviation percent 6MHz n 12 6MHz n 1 0 3MHz n 24 3MHz n 2 0 3 2...

Page 105: ...se the same J Link J Trace simultaneously Configuring a debugger to work with a core in a multi core environment does not require special settings All that is required is proper setup of the scan chai...

Page 106: ...onnect your target to J Link J Trace 2 Start your debugger for example IAR Embedded Workbench for ARM 3 Choose Project Options and configure your scan chain The picture below shows the configuration f...

Page 107: ...than single core debugging You should be aware of the pitfalls related to JTAG speed and resetting the target 5 5 3 1 JTAG speed Each core has its own maximum JTAG speed The maximum JTAG speed of all...

Page 108: ...04 2012 SEGGER Microcontroller GmbH Co KG 5 5 3 2 Resetting the target All cores share the same RESET line You should be aware that resetting one core through the RESET line means resetting all cores...

Page 109: ...tch below shows a host running two application programs Each application communicates with one ARM core via a separate J Link Older J Links J Traces all reported the same serial number which made it n...

Page 110: ...ller GmbH Co KG In order to re configure a J Link to use the new USB identification method use the J Link Configurator which comes with the J Link software and documentation package For more informati...

Page 111: ...ware are shown Moreover the following general settings can be configured Show tray icon If this checkbox is disabled the tray icon will not show from the next time the DLL is loaded Start minimized If...

Page 112: ...nk ARM FlashDL will be disabled internally On Enables the J Link ARM FlashDL feature If no license has been found an error message appears Off Disables the J Link ARM FlashDL feature Skip download on...

Page 113: ...s checkbox is enabled ARM instructions will be simulated as far as possible This speeds up single stepping especially when FlashBPs are used Save settings When this button is pushed the current settin...

Page 114: ...ccesses to the ICE registers for Cortex M3 devices write accesses to the memory mapped flash breakpoint registers and in general simple write accesses for software breakpoints if the program is locate...

Page 115: ...calls to log Register read write Memory read write set clear breakpoint step go halt is halted 5 7 1 5 CPU Regs In this section the name and the value of the CPU registers are shown 5 7 1 6 Target Po...

Page 116: ...ly supports UART encoding Bytes in buffer Shows how many bytes are in the DLL SWV data buffer Bytes transferred Shows how many bytes have been transferred via SWV since the debug session has been star...

Page 117: ...halted Some CPUs can actually be halted before executing any instruction because the start of the CPU is delayed after reset release If a pause has been specified J Link waits for the specified time...

Page 118: ...6 Software This reset strategy is only a software reset Software reset means basically no reset just changing the CPU registers such as PC and CPSR This reset strategy sets the CPU registers to their...

Page 119: ...ds The CPU does not start execution of the program because J Link sets the VC_CORERESET bit before reset which causes the CPU to halt before execution of the first instruction 5 8 2 3 Type 2 ResetPin...

Page 120: ...le instruction 5 8 2 9 Type 9 Reset for LPC1200 devices On the NXP LPC1200 devices the watchdog is enabled after reset and not disabled by the bootloader if a valid application is in the flash memory...

Page 121: ...get application program that regularly calls the DCC handler The supplied abort handler should be installed optional An application program that uses DCC is JLink exe 5 9 2 Target DCC handler The targ...

Page 122: ...ed in a script file depends on if the corresponding function is present in the script file In the following all J Link actions which can be customized using a script file are listed and explained 5 10...

Page 123: ...unction or a variable is added right behind the string Prototype __api__ int Report1 const char sMsg int v 5 10 2 5 JTAG_SetDeviceId Description Sets the JTAG Id of a specified device in the JTAG chai...

Page 124: ...bles on page 126 Prototype __api__ int JTAG_StoreIR unsigned int Cmd 5 10 2 9 JTAG_WriteDR Description Writes JTAG data Before calling this function please make sure that the JTAG chain has been confi...

Page 125: ...DLL JTAG buffer Prototype __api__ int JTAG_StoreClocks int NumClocks 5 10 2 16JTAG_Reset Description Performs a TAP reset and tries to auto detect the JTAG chain Total IRLen Number of devices If auto...

Page 126: ...following all global variables and their value ranges are listed and described Note All global variables are treated as unsigned 32 bit values and are zero ini tialized Variable Description R W CPU P...

Page 127: ...0 Low 1 high Example JTAG_ResetPin 0 SYS_Sleep 5 Give pin some time to get low JTAG_ResetPin 1 W JTAG_TRSTPin Pulls reset pin low Releases nTRST pin Used to issue a reset of the debug logic of the CP...

Page 128: ...sableHWTransmissions 1 W CORESIGHT_CoreBaseAddr Set base address of core debug component for CoreSight compliant devices Setting this vari able disables the J Link auto detection of the core debug com...

Page 129: ...present one for each device This function can only be used if a AP layout has been configured via CORESIGHT_AddAP Example CORESIGHT_AddAP 0 CORESIGHT_AHB_AP CORESIGHT_AddAP 1 CORESIGHT_APB_AP CORESIG...

Page 130: ...ventions of the C lan guage but it does not support all expresisons and operators which are supported by the C language In the following the supported operators and expressions are listed 5 10 5 1 Sup...

Page 131: ...tom device 5 bits IRLen void InitTarget void Report J Link script example JTAG_Reset Perform TAP reset and J Link JTAG auto detection if JTAG_TotalIRLen 9 Basic check if JTAG chain information matche...

Page 132: ...a project file for J Link is set by the debugger which allows the J Link DLL to save the settings of the control panel in this project file After selecting the script file restart your debug session F...

Page 133: ...ture EnableFlashBPs Enables the FlashPB feature EnableFlashDL Enables the J Link ARM FlashDL feature map exclude Ignore all memory accesses to specified area map indirectread Specifies an area which s...

Page 134: ...Memory mapping Some devices do not allow access of the entire 4GB memory area Ideally the entire memory can be accessed if a memory access fails the CPU reports this by switching to abort mode The CPU...

Page 135: ...pecified memory area to the host Before map indirectread can be called a RAM area for the indirectly read code snippet has to be defined Use therefor the map ram command and define a RAM area with a s...

Page 136: ...fore any other map command is called Syntax map reset Example map reset 5 11 1 10 SetAllowSimulation This command can be used to enable or disable the instruction set simulation By default the instruc...

Page 137: ...e different reset strategies for ARM 7 9 and Cortex M devices Syntax SetResetType value Example SetResetType 0 Selects reset strategy type 0 normal 5 11 1 14 SetRestartOnClose This command specifies w...

Page 138: ...The target CPU is powered down when there is no transmission between J Link and target CPU for at least 10ms 5 11 1 17 SupplyPower This command activates power supply over pin 19 of the JTAG connector...

Page 139: ...sted with the J Link Commander Use the com mand exec supplemented by one of the command strings Example exec SupplyPower 1 exec map reset exec map exclude 0x10000000 0x3FFFFFFF 5 11 2 2 IAR Embedded W...

Page 140: ...04 2012 SEGGER Microcontroller GmbH Co KG On the Extra Options page select Use command line options Enter jlink_exec_command CommandLineOption in the textfield as shown in the screenshot below If more...

Page 141: ...the first instruction in the ISR typically at address 0x18 Synthesizable cores ARM7TDMI S ARM9E S etc With these cores the clock input of the TAP controller is connected to the output of a three stage...

Page 142: ...this is the responsibility of the software 5 13 2 Cache clean area J Link J Trace handles cache cleaning directly through JTAG commands Unlike other emulators it does not have to download code to the...

Page 143: ...nk J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 143 Chapter 6 Flash download This chapter describes how the flash download feature of the DLL can be used in dif ferent debugger environm...

Page 144: ...feature of J Link is very efficient and allows fast flash programming For exam ple if a debugger splits the download image into several pieces the flash download software will collect the individual p...

Page 145: ...J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 145 6 2 Licensing No extra license required The flash download feature can be used free of charge...

Page 146: ...umber of microcontrol lers You can always find the latest list of supported devices on our website http www segger com jlink_supported_devices html In general J Link can be used with any ARM7 9 11 Cor...

Page 147: ...rs is explained 6 4 1 IAR Embedded Workbench Using the J Link flash download feature in IAR EWARM is quite simple First choose the right device in the project settings if not already done The device s...

Page 148: ...t settings if not already done The device set tings can be found at Project Options for Target Device To enable the J Link flash loader J Link J Trace at Project Options for Tar get Utilities has to b...

Page 149: ...n in the screenshot below 6 4 3 J Link GDB Server The configuration for the J Link GDB Server is done by the gdbinit file The follow ing command has to be added to the gdbinit file to enable the J Lin...

Page 150: ...exec device DeviceName DeviceName is the name of the device for which download into internal flash mem ory shall be enabled For a list of supported devices please refer to Supported devices on page 14...

Page 151: ...DK Using the J Link flash download feature with IAR Embedded Workbench Keil MDK is quite simple First start the debug session and open the J Link Control Panel In the tab Settings you will find the lo...

Page 152: ...iant parallel NOR Flash on a ST STM32F103ZE using J Link commander r speed 1000 exec setcfiflash 0x64000000 0x64FFFFFF exec setworkram 0x20000000 0x2000FFFF w4 0x40021014 0x00000114 RCC_AHBENR FSMC cl...

Page 153: ...nk DLL flash loaders make flash behave as RAM from a user perspective since flash programming is triggered by simply calling the J Link API functions for memory reading writing For more information ab...

Page 154: ...154 CHAPTER 6 Flash download J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG...

Page 155: ...J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 155 Chapter 7 Flash breakpoints This chapter describes how the flash breakpoints feature of the DLL can be used in different debugger enviro...

Page 156: ...ation is not located in RAM On modern microcontrollers this is the stan dard scenario because on most microcontrollers the internal RAM is not big enough to hold the complete application When replacin...

Page 157: ...neral SEGGER offers free 30 days trial licenses for flash breakpoints upon request The J Link DLL also comes with a special feature that allows the user to test the flash breakpoints feature for 24 ho...

Page 158: ...f microcontrollers You can always find the latest list of supported devices on our website http www segger com jlink_supported_devices html In general J Link can be used with any ARM7 9 11 Cortex M0 M...

Page 159: ...CFI flash For more information about how to setup various debuggers for flash download please refer to Setup for various debuggers internal flash on page 147 If flash break points are available can be...

Page 160: ...KG 7 5 FAQ Q Why can flash breakpoints not be used with Rowley Crossworks A Because Rowley Crossworks does not use the proper J Link API to set breakpoints Instead of using the breakpoint API Crosswo...

Page 161: ...ARM trying to standardize a debugger debug probe interface It is defined for cores only that have the same CPU register set as ARM7 CPUs This chapter describes how to use the RDI DLL which comes with...

Page 162: ...onsists of a DLL designed for ARM cores to be used with any RDI compliant debugger The J Link DLL feature flash download and flash breakpoints can also be used with J Link RDI 8 1 1 Features Can be us...

Page 163: ...cense is necessary for each J Link For some devices J Link comes with a device based license and some J Link models also come with a full license for J Link RDI but the normal J Link comes with out an...

Page 164: ...d with IAR Embedded Workbench for ARM 8 3 1 1 Supported software versions J Link RDI has been tested with IAR Embedded Workbench IDE version 4 40 There should be no problems with other versions of IAR...

Page 165: ...to the RDI page of the Debugger options select the manufacturer driver JLinkRDI dll and click OK 4 Now an extra menu RDI has been added to the menu bar Choose RDI Configure to configure the J Link For...

Page 166: ...use J Link RDI for Cortex M devices because SEGGER and IAR have been come to an agreement regarding the RDI register assignment for Cortex M The following table lists the register assignment for RDI a...

Page 167: ...been tested with ARM s AXD version 1 2 0 and 1 2 1 There should be no problems with other versions of ARM s AXD All screenshots are taken from ARM s AXD version 1 2 0 8 3 2 2 Configuring to use J Lin...

Page 168: ...is available in the Target Environments list 4 Select J Link and press OK to connect to the target via J Link ARM For more information about the generic setup of J Link RDI please refer to Configurat...

Page 169: ...I has been tested with ARM RVDS version 2 1 and 3 0 There should be no problems with earlier versions of RVDS up to version v3 0 1 All screenshots are taken from ARM s RVDS version 2 1 Note RVDS versi...

Page 170: ...ink J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 2 Select File Connection Connect to Target 3 In the Connection Control dialog use the right mouse click on the first item and select Add...

Page 171: ...inkRDI dll 5 After adding the DLL an additional Dialog opens and asks for description These values are voluntary if you do not want change them just click OK Use the fol lowing values and click on OK...

Page 172: ...page 180 7 Click the OK button in the configuration dialog Now close the RDI Target List dialog Make sure your target hardware is already connected to J Link 8 In the Connection control dialog expand...

Page 173: ...J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 173 9 Now the RealView Debugger is connected to J Link...

Page 174: ...3 4 GHS MULTI 8 3 4 1 Software version J Link RDI has been tested with GHS MULTI version 4 07 There should be no prob lems with other versions of GHS MULTI All screenshots are taken from GHS MULTI ve...

Page 175: ...nter rdiserv in the Server field and enter the following values in the Arguments field config dll FullPathToJLinkDLLs Note that JLinkRDI dll and JLinkARM dll must be stored in the same directory If th...

Page 176: ...The J Link RDI Configuration dialog will be opened For more information about the generic setup of J Link RDI please refer to Configuration on page 180 7 Click the OK button to connect to the target B...

Page 177: ...3 5 KEIL MDK Vision IDE 8 3 5 1 Software version J Link has been tested with KEIL MDK 3 34 There should be no problems with other versions of KEIL Vision All screenshots are taken from MDK 3 34 8 3 5...

Page 178: ...elect the Debug tab Choose RDI Interface Driver from the list as shown above and click the Settings button Select the location of JLinkRDI dll in Browse for RDI Driver DLL field and click the Configur...

Page 179: ...k J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 179 After finishing configuration the project can be build Project Build Target and the debugger can be started Debug Start Stop debug ses...

Page 180: ...l needs to be copied into it Project A needs to be configured to use JLinkRDI dll A in the first folder project B needs to be configured to use the DLL in the second folder Both projects will use sepa...

Page 181: ...ould connect to the J Link Some J Link models also come with an Ethernet interface which allows to use an emulator remotely via TCP IP connection License J Link RDI License managment 1 The License but...

Page 182: ...is now added 8 4 4 2 Init tab Macro file A macro file can be specified to load custom settings to configure J Link RDI with advanced commands for special chips or operations For example a macro file...

Page 183: ...rts the ARM core Halt Halts the ARM core Read8 Addr Reads a 8 16 32 bit value Addr address to read as hex value Read16 Addr Read32 Addr Verify8 Addr Data Verifies a 8 16 32 bit value Addr address to v...

Page 184: ...AG speed Adaptive clocking For more information about the different speed settings supported by J Link please refer to JTAG Speed on page 102 JTAG scan chain with multiple devices The JTAG scan chain...

Page 185: ...ence Cache flash contents If enabled the flash contents is cached by the J Link RDI software to avoid reading data twice and to speed up the transfer between debugger and target Allow flash download T...

Page 186: ...by setting and resetting breakpoints according to program code Use flash breakpoints This allows to set an unlimited number of breakpoints if the program is located either in RAM or in flash by settin...

Page 187: ...e way of resetting and halting an ARM core before it starts to execute instructions For more information about the different reset strategies which are supported by J Link and why different reset stra...

Page 188: ...5 060 232 0001 ARM_ReadMem FFFFF130 0004 Data 00 00 00 00 060 233 0001 ARM_ReadMem FFFFF130 0004 Data 00 00 00 00 060 234 0001 ARM_ReadMem FFFFF130 0004 Data 00 00 00 00 060 236 0000 ARM_ReadMem FFFFF...

Page 189: ...lso invoke the semihosting SWI directly Refer to the C library descriptions in the ADS Compilers and Libraries Guide for more information on sup port for semihosting in the ARM C library Semihosting i...

Page 190: ...ports an error See Unexpected unhandled SWIs on page 191 8 5 3 1 DCC semihosting J Link RDI does not support using the debug communications channel for semihost ing 8 5 4 Semihosting with AXD This sem...

Page 191: ...J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 191 8 5 5 Unexpected unhandled SWIs When an unhandled SWI is detected by J Link RDI the message box below is shown...

Page 192: ...192 CHAPTER 8 RDI J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG...

Page 193: ...J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 193 Chapter 9 Device specifics This chapter describes for which devices some special handling is necessary to use them with J Link...

Page 194: ...ftware reset means basically RESET pin is used to perform the reset the reset is initiated by writing special func tion registers via software The software reset for Analog Devices ADuC7xxxx executes...

Page 195: ...ce UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 195 Analog ADuC7026x62 Analog ADuC7027x62 Analog ADuC7030 Analog ADuC7031 Analog ADuC7032 Analog ADuC7033 Analog ADuC7128 Analog ADuC7129 Analog...

Page 196: ...M3S1C AT91SAM3S2A AT91SAM3S2B AT91SAM3S2C AT91SAM3S4A AT91SAM3S4B AT91SAM3S4C AT91SAM3U1C AT91SAM3U2C AT91SAM3U4C AT91SAM3U1E AT91SAM3U2E AT91SAM3U4E AT91SAM3X2C AT91SAM3X2E AT91SAM3X2G AT91SAM3X2H AT...

Page 197: ...all devices 9 2 1 2 Memory mapping Either flash or RAM can be mapped to address 0 After reset flash is mapped to address 0 In order to majlink_supported_devices html RAM to address 0 a 1 can be writte...

Page 198: ...FFF60 0x00480100 monitor sleep 100 Setup GDB for faster downloads set remote memory write packet size 1024 set remote memory write packet size 4096 set remote memory write packet size fixed monitor sp...

Page 199: ...rite32 0xFFFFFC20 0x00000601 Set PLL Delay 200 Write32 0xFFFFFC2C 0x00191C05 Set PLL and divider Delay 200 Write32 0xFFFFFC30 0x00000007 Select master clock and processor clock Write32 0xFFFFFF60 0x00...

Page 200: ...Device specifics J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 9 3 DSPGroup J Link has been tested with the following DSPGroup devices DA56KLF Currently there are no specifics for...

Page 201: ...J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 201 9 4 Ember J Link has been tested with the following Ember devices EM351 EM357 Currently there are no specifics for these devices...

Page 202: ...G280F32 EFM32G280F64 EFM32G280F128 EFM32G290F32 EFM32G290F64 EFM32G290F128 EFM32G840F32 EFM32G840F64 EFM32G840F128 EFM32G880F32 EFM32G880F64 EFM32G880F128 EFM32G890F32 EFM32G890F64 EFM32G890F128 EFM32...

Page 203: ...2 MK50DX256 MK50DN512 MK50DX256 MK51DX256 MK51DN512 MK51DX256 MK51DN512 MK51DN256 MK51DN512 MK52DN512 MK53DN512 MK53DX256 MK60N256 MK60N512 MK60X256 9 6 1 Kinetis family 9 6 2 Unlocking If your device...

Page 204: ...Trace On these devices a low drive strength should be configured for the trace clock pin in order to match the timing requirements On later silicons this has been corrected The J Link software and do...

Page 205: ...ices MB9AF102N MB9AF102R MB9AF104N MB9AF104R MB9BF104N MB9BF104R MB9BF105N MB9BF105R MB9BF106N MB9BF106R MB9BF304N MB9BF304R MB9BF305N MB9BF305R MB9BF306N MB9BF306R MB9BF404N MB9BF404R MB9BF405N MB9BF...

Page 206: ...9 Device specifics J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 9 8 Itron J Link has been tested with the following Itron devices TRIFECTA Currently there are no specifics for th...

Page 207: ...LM3S316 LM3S317 LM3S328 LM3S601 LM3S610 LM3S611 LM3S612 LM3S613 LM3S615 LM3S617 LM3S618 LM3S628 LM3S801 LM3S811 LM3S812 LM3S815 LM3S817 LM3S818 LM3S828 LM3S2110 LM3S2139 LM3S2410 LM3S2412 LM3S2432 LM3...

Page 208: ...has been locked accidentially e g by bad application code in flash which mis configures the PLL and J Link can not identify it anymore there is a spe cial unlock sequence which erases the flash memor...

Page 209: ...51 LPC1752 LPC1754 LPC1756 LPC1758 LPC1764 LPC1765 LPC1766 LPC1768 LPC2101 LPC2102 LPC2103 LPC2104 LPC2105 LPC2106 LPC2109 LPC2114 LPC2119 LPC2124 LPC2129 LPC2131 LPC2132 LPC2134 LPC2136 LPC2138 LPC21...

Page 210: ...the J Link com mand map ram and define afterwards the memory area which should be read indirect with the command map indirectread to use the indirectly reading feature of J Link Note that the data in...

Page 211: ...sure that user flash is mapped at address 0 Moreover the user have to correct the Stack pointer R13 and the PC R15 manually after reset in order to debug the application 9 10 3 LPC288x flash programmi...

Page 212: ...k J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 9 11 OKI J Link has been tested with the following OKI devices ML67Q4002 ML67Q4003 ML67Q4050 ML67Q4051 ML67Q4060 ML67Q4061 Currently there...

Page 213: ...oller GmbH Co KG 213 9 12 Renesas J Link has been tested with the following Renesas devices R5F56104 R5F56106 R5F56107 R5F56108 R5F56216 R5F56217 R5F56218 R5F562N7 R5F562N8 R5F562T6 R5F562T7 R5F562TA...

Page 214: ...depends on the content of the smart option bytes at addr 0xC0 The watchdog keeps counting even if the CPU is in debug mode e g halted So please do not use the watchdog when debug ging to avoid unexpec...

Page 215: ...1FV0 STR731FV1 STR731FV2 STR735FZ1 STR735FZ2 STR736FV0 STR736FV1 STR736FV2 STR750FV0 STR750FV1 STR750FV2 STR751FR0 STR751FR1 STR751FR2 STR752FR0 STR752FR1 STR752FR2 STR755FR0 STR755FR1 STR755FR2 STR75...

Page 216: ...g Turbo Mode is necessary to guarantee proper function of all commands in the STR91x Commander 9 14 1 3 Switching the boot bank The bootbank of the STR91x devices can be switched by using the J Link S...

Page 217: ...out J Flash please refer to UM08003 J Flash User Guide In order to unsecure a read protected STM32F10x device SEGGER offers two software components J Flash J Link STM32 Commander command line utility...

Page 218: ...ster of the STM32F10x devices To configure the watchdog timers to stop while the CPU is in debug mode bits 8 and 9 of the DBGMCU_CR have to be set volatile int 0x40040520 1 8 1 9 9 14 3 STM32F2xxx The...

Page 219: ...lock MEM_WriteU32 0x40023830 0x00000010 Assign trace pins to alternate function in order to make them usable as trace pins PE2 Trace clock PE3 TRACE_D0 PE4 TRACE_D1 PE5 TRACE_D2 PE6 TRACE_D3 MEM_Write...

Page 220: ...1A128 TMS470R1A256 TMS470R1A288 TMS470R1A384 TMS470R1B512 TMS470R1B768 TMS470R1B1M TMS470R1VF288 TMS470R1VF688 TMS470R1VF689 9 15 1 AM335x The AM335x series CPUs need some special handling in various...

Page 221: ...x AM37xx Needs a J Link script file to guarantee proper functionality J Link script file can be found at JLINK_INST_DIR Samples JLink Scripts For more information about how to use J Link script files...

Page 222: ...K_INST_DIR Samples JLink Scripts For more information about how to use J Link script files please refer to Executing J Link script files on page 131 9 15 7 OMAP3550 Needs a J Link script file to guara...

Page 223: ...DFG TMPM330FWFG TMPM330FYFG TMPM332FWUG TMPM333FDFG TMPM333FWFG TMPM333FYFG TMPM341FDXBG TMPM341FYXBG TMPM360F20FG TMPM361F10FG TMPM362F10FG TMPM363F10FG TMPM364F10FG TMPM366FDFG TMPM366FWFG TMPM366FY...

Page 224: ...224 CHAPTER 9 Device specifics J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG...

Page 225: ...08001 2004 2012 SEGGER Microcontroller GmbH Co KG 225 Chapter 10 Target interfaces and adapters This chapter gives an overview about J Link J Trace specific hardware details such as the pinouts and av...

Page 226: ...t Typically connected to nTRST of the target CPU This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection 5 TDI Output JTAG data input of target CPU It...

Page 227: ...41651 For example 15 RESET I O Target CPU reset signal Typically connected to the RESET pin of the target CPU which is typically called nRST nRESET or RESET 17 DBGRQ NC This pin is not connected in J...

Page 228: ...t circuit Power can be controlled via the J Link com mander The following commands are available to control power Command Explanation power on Switch target power on power off Switch target power off...

Page 229: ...Not used NC This pin is not used by J Link If the device may also be accessed via JTAG this pin may be connected to TDI other wise leave open 7 SWDIO I O Single bi directional data pin A pull up resi...

Page 230: ...iconductor manufacturer 10 1 2 3 Target power supply Pin 19 of the connector can be used to supply power to the target hardware Supply voltage is 5V max current is 300mA The output current is monitore...

Page 231: ...or on each alternate rising or falling edge 10 2 1 Connecting the target board J Trace connects to the target board via a 38 pin trace cable This cable has a recep tacle on the one side and a plug on...

Page 232: ...TAG port 12 VTRef Signal level reference It is normally fed from Vdd of the target board and must not have a series resistor 13 RTCK Return test clock from the target JTAG port 14 VSupply Supply volta...

Page 233: ...chi tecture versions on page 234 23 Trace signal 20 24 Trace signal 8 25 Trace signal 19 26 Trace signal 7 27 Trace signal 18 28 Trace signal 6 29 Trace signal 17 30 Trace signal 5 31 Trace signal 16...

Page 234: ...Trace signal 2 PIPESTAT 1 PIPESTAT 1 TRACECTL Trace signal 3 PIPESTAT 2 PIPESTAT 2 Logic 1 Trace signal 4 TRACESYNC PIPESTAT 3 Logic 0 Trace signal 5 TRACEPKT 0 TRACEPKT 0 Logic 0 Trace signal 6 TRACE...

Page 235: ...half rate clocking mode Data is output on each edge of the TRACECLK signal and TRACECLK max 100MHz For half rate clocking the setup and hold times at the JTAG Trace connector must be observed Tsh 2 5n...

Page 236: ...uired for SWD communication This pin normally pin 7 is not existent on the 19 pin JTAG SWD and Trace connector 8 TDI Output JTAG data input of target CPU It is recommended that this pin is pulled to a...

Page 237: ...and protected against overload and short circuit Power can be controlled via the J Link commander The following commands are available to control power 16 TRACE DATA 1 Input Input Trace data pin 0 18...

Page 238: ...of target CPU This pin should be pulled up on the target Typically connected to TMS of the target CPU When using SWD this pin is used as Serial Wire Output trace port Optional not required for SWD com...

Page 239: ...o KG 239 10 5 Adapters There are various adapters available for J Link as for example the JTAG isolator the J Link RX adapter or the J Link Cortex M adapter For more information about the different ad...

Page 240: ...240 CHAPTER 10 Target interfaces and adapters J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG...

Page 241: ...n This chapter provides background information about JTAG and ARM The ARM7 and ARM9 architecture is based on Reduced Instruction Set Computer RISC principles The instruction set and the related decode...

Page 242: ...e bit register that passes information from TDI to TDO Boundary scan data register A test data register which allows the testing of board interconnections access to input and output of components when...

Page 243: ...te between scan DR or IR operations Once entered this state remains active as long as TMS is low DR Scan Temporary controller state If TMS remains low a scan sequence for the selected data registers i...

Page 244: ...rom occurring during the shifting process Capture IR Instructions may be loaded in parallel into the instruction register Shift IR The instruction register shifts the values in the instruction registe...

Page 245: ...has been captured J Trace is seamlessly integrated into the IAR Embedded Workbench IDE The advanced trace debugging features can be used with the IAR C SPY debug ger 11 2 1 Trigger condition The ETM c...

Page 246: ...246 CHAPTER 11 Background information J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 11 2 3 1 Code coverage Disassembly tracing...

Page 247: ...J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 247 11 2 3 2 Code coverage Source code tracing...

Page 248: ...248 CHAPTER 11 Background information J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG...

Page 249: ...rt of the device once capture has been completed No additional special trace port is required so that the ETB can be read via J Link The trace functionality via J Link is limited by the size of the ET...

Page 250: ...fter this This process may have to be repeated until the entire data is programmed into the flash 11 4 3 Data download via DCC In this case the RAM code is started as described above before downloadin...

Page 251: ...flash loaders can of course be used if they match your flash configura tion which is something that needs to be checked with the vendor of the debugger 11 4 4 4 Write your own flash loader Implement y...

Page 252: ...require a reboot It is recommended that you always use the latest version of JLinkARM dll In the screenshot The red box identifies the new firmware The green box identifies the old firmware which has...

Page 253: ...lication for example JLink exe which uses the desired version of JLinkARM dll This automatically replaces the invalidated firmware with its embedded firmware In the screenshot The red box identifies t...

Page 254: ...254 CHAPTER 11 Background information J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG...

Page 255: ...k J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 255 Chapter 12 Designing the target board for trace This chapter describes the hardware requirements which have to be met by the tar get b...

Page 256: ...be taken when ETM signals are multiplexed with other pin functions and where the PCB is designed to support both functions with differing tracking requirements 12 1 2 Minimizing Signal Skew Balancing...

Page 257: ...p pull down combination is used their resistance values must be selected so that their parallel combination equals the PCB track impedance Caution At lower frequencies parallel termination requires co...

Page 258: ...H Co KG 12 3 Signal requirements The table below lists the specifications that apply to the signals as seen at the JTAG Trace connector Signal Value Fmax 200MHz Ts setup time min 2 0ns Th hold time mi...

Page 259: ...tips together with solutions for common prob lems which might occur when using J Link J Trace There are several steps you can take before contacting support Performing these steps can solve many probl...

Page 260: ...asuring download speed 13 1 1 Test environment JLink exe has been used for measurement performance The hardware consisted of PC with 2 6 GHz Pentium 4 running Win2K USB 2 0 port USB 2 0 hub J Link Tar...

Page 261: ...working properly and cannot be the cause of your problem 14 If the problem persists and you own an original product not an OEM version see section Contacting support on page 263 13 2 2 Typical proble...

Page 262: ...2004 2012 SEGGER Microcontroller GmbH Co KG J Link J Trace does not get any connection to the target Most likely reasons a The JTAG cable is defective b The target hardware is defective Remedy Follow...

Page 263: ...there If the device functions correctly the USB setup on the original machine or your target hardware is the source of the problem not J Link J Trace If you need to contact support send the following...

Page 264: ...race as well as the supply voltage which can be useful to detect hardware problems on the target system J Link support of ETM Q Does J Link support the Embedded Trace Macrocell ETM A No ETM requires a...

Page 265: ...J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 265 Chapter 14 Glossary This chapter describes important terms used throughout this manual...

Page 266: ...itten to the cache but has not been written to main memory is referred to as dirty data Only write back caches can have dirty data because a write through cache writes data to the cache and to main me...

Page 267: ...tion Obtaining memory coherency is difficult when there are multiple possible physical locations that are involved such as a system that has main memory a write buffer and a cache Memory management un...

Page 268: ...ARM standard procedural interface between a debugger and the debug agent The widest possible adoption of this standard is encouraged RTCK Returned TCK The signal which enables Adaptive Clocking RTOS...

Page 269: ...TAP Controller Comprises TCK TMS TDI TDO and nTRST optional Transistor transistor logic TTL A type of logic design in which two bipolar transistors drive the logic output to one or zero LSI and VLSI...

Page 270: ...270 CHAPTER 14 Glossary J Link J Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG...

Page 271: ...Trace UM08001 2004 2012 SEGGER Microcontroller GmbH Co KG 271 Chapter 15 Literature and references This chapter lists documents which we think may be useful to gain deeper under standing of technical...

Page 272: ...ion ARM IHI 0014J This document defines the ETM standard including signal protocol and physical interface It is publicly available from ARM www arm com RVI RealView ICE and RealView Trace User Guide A...

Page 273: ...nstruction Register 267 IR 267 J J Flash ARM 70 J Link Adapters 239 Developer Pack DLL 76 Supported chips 144 145 156 157 J Link ARM Flash DLL 76 J Link Commander 64 J Link GDB Server 72 J Link RDI 71...

Page 274: ...emihosting 268 SetDbgPowerDownOnClose 137 SetSysPowerDownOnIdle 138 Support 259 265 Supported flash devices 146 147 151 158 SWI 268 T Tabs 111 TAP Controller 268 Target 268 TCK 226 268 TDI 226 268 TDO...

Search results

Summary of Contents for J-Link ARM

Reviews:

Related manuals for J-Link ARM

Brands by name

Popular brands

Segger J-Link ARM, User Manual

Search results

Summary of Contents for J-Link ARM

Reviews:

Related manuals for J-Link ARM

Brands by name

Popular brands