μ
Q7-962
μ
Q7-962 User Manual - Rev. First Edition: 1.0 - Last Edition: 3.1 - Author: S.B. - Reviewed by P.Z Copyright © 2016 SECO S.r.l.
33
3.2.1.10
LPC/GPIO interface signals
According to Qseven
®
specifications rel. 2.0, on the golden edge finger connector there are 8 pins that could be used for implementation of Low Pin Count (LPC)
Bus interface or as General Purpose I/Os (GPIO).
However, LPC interface is not native for i.MX6 processors, for this reason on golden finger connector
’
s pins 185÷192 there are eight General Purpose I/Os, which
are bidirectional signals at +3.3V_S electrical level. Programming of these GPIOs can be made using dedicated APIs supplied by SECO, or through Linux File
System. In the following table, it is shown the correspondence of MXM pins and i.MX6 GPIO pins, as well as GPIO Virtual Number:
MXM Connector pin #
i.MX6 GPIO Signal name
GPIO Virtual Number *
185
GPIO1_IO16
16
186
GPIO1_IO17
17
187
GPIO1_IO19
19
188
GPIO1_IO21
21
189
GPIO1_IO20
20
190
GPIO1_IO18
18
191
GPIO6_IO14
174
192
GPIO6_IO15
175
* Virtual Number = (GPIO port_number -1) x 32 + GPIO_number, assuming that in GPIO
x
_IO
y
nomenclature
x
shows the GPIO Port_number and
y
shows the
GPIO_number.
3.2.1.11
SPI interface signals
i.MX6 processors offer up to four Enhanced Configurable Serial Peripheral Interfaces (eCSPIS), which can be used for connection of EEPROMs and Serial Flash
devices, which can also be used for serial boot.
SPI interface can support speed up to 20MHz.
Signals involved with SPI management are the following (they are supported by i.MX6 processor
’
s ECSPI2 controller):
SPI_MOSI: SPI Master Out Slave In, Output from Qseven
®
module to SPI devices embedded on the Carrier Board. Electrical level +3.3V_S
SPI_MISO: SPI Master In Slave Out, Input to Qseven
®
module from SPI devices embedded on the Carrier Board. Electrical level +3.3V_S
SPI_CLK: SPI Clock Output to carrier board
’
s SPI embedded devices. Electrical level +3.3V_S
SPI_CS0#: SPI primary Chip select, active low output signal (+3.3V_S electrical level)
SPI_CS1#: SPI secondary Chip select, active low output signal (+3.3V_S electrical level). This signal must be used only in case there are two SPI devices on the
carrier board, and the first chip select signal (SPI_CS0#) has already been used. It must not be used in case there is only one SPI device.
