Seagate Ultra 160, Product Manual

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Parallel SCSI Interface Product Manual, Rev. A ) 37
The receiver skew compensation and clock shifting adjust the timing relationship between the clocking signal
(i.e., REQ or ACK) and the signals being clocked (e.g., the data bus signals). That adjustment causes the clock
signal to align with the middle of the signals being clocked when those signals enter the receiver. The receiver
is then able to the clock signal to latch valid data.
During paced transfers, the clock signal (i.e., REQ or ACK) transitions at the negotiated transfer period. Data is
qualified by the clock signal and the phase of the P1 signal.
Receiver skew compensation is not defined in this manual.
Figure 9. Example of a SCSI bus with paced transfers
2.9 Data transfer modes
There are three types of transfer modes:
• Asynchronous
• Synchronous
• Paced
This section provides a brief description of each of these types of transfer modes.
2.9.1 Asynchronous transfers
SCSI device ports default to 8-bit asynchronous transfers.
8-bit asynchronous transfers are used for all COMMAND, STATUS, and MESSAGE phases.
ST DATA phases may use 8-bit or 16-bit asynchronous transfers. Asynchronous transfers are not permitted in
DT DATA phases.
2.9.2 Synchronous transfers
ST DATA phases shall use synchronous transfers when a synchronous transfer agreement is in effect. ST
DATA phases may use 8-bit or 16-bit synchronous transfers.
DT DATA phases shall use synchronous transfers when a synchronous transfer agreement is in effect. DT
DATA phases shall only use wide transfers.
2.9.3 Paced transfers
Paced transfers shall only be used in DT DATA phases when a paced transfer agreement is in effect. DT
phases shall only use wide transfers.
Driver Precomp
SCSI Device SCSI Device
Cable
and/or
Backplane
Signal
Adjustment
Skew
Compensator
& Clock
Shift
Receiver
Optional