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Spinpoint M8 Product Manual REV 2.6

 

29 

 

 

   

5.2.2.6           Power Management

 

 

Power  management  features  are  incorporated  into  each  block  of  the  Spinpoint  M8.  This  allows  the  designer 
to tailor the amount of power management to the specified design. Other power management features include: 

  

Independent power management control for each block. 

  

DSP block powered down and up when needed. 

  

Disk Sequencer and associated disk logic powered up when the Disk Sequencer is started. 

  Weak

  pull-up  structure  on  input  pins  to  prevent  undesirable  power  consumption  due  to 

floating CMOS inputs. 

 

 

 

 

5.2.3    Read/Write IC

 

 

 

The  Read/Write  IC,  shown  in  Figure  5-3  provides  read/write-processing  functions  for  the  drive.  The 
Read/Write IC receives the Read GATE and Write GATE signals, write data, and servo AGC and gates from the 
Interface Controller.  The  Read/Write  IC  sends  decoded  read  data  and  the  read  reference  clock.  It receives 
write data from the Interface Controller. 
 
The 88C9410 which is embedded in 88i9422 is a sampled-data digital PRML channel designed to work with a disk 
controller and a read/write preamplifier to provide the signal processing elements required to build a state of the art 
high density, high speed disk drive. The 88C9410 implements a noise predictive, PRML Viterbi read channel 
(supporting) zone-bit recording, 
 
The  read/write  channel  functions  include a time base generator,  AGC  circuitry,  asymmetry  correction circuitry 
(ASC), analog anti-aliasing  low-pass filter, analog to digital converter (ADC), digital FIR filter, timing recovery 
circuits, Viterbi detector, sync mark detection, Iterative code ENDEC, serializer and de-serializer, and write pre-
compensation circuits.  Servo functions include servo data detection and PES demodulation.  Additionally the 
88C9410 contains specialized circuitry to perform various parametric measurements on the processed read signal. 
This allows for implementation of self-tuning and optimization capability in every drive built using the 88C9410. 
 
A  12-bit  NRZ  interface  is  provided  to  support  high  speed  data  transfers  and  from  the  controller. 
Programming of the 88C9410 is performed through a serial interface.  The serial interface is also used to read 
various channel parameters that are computed on the fly. 

 

5.2.3.1           Time Base Generator

 

 

The  time  base  generator  provides  the  write  frequency  and  serves  as  a  reference  clock  to  the  synchronizer 
during non-read mode. 

 

 

5.2.3.2           Automatic Gain Control

 

 

The  AGC  accepts  a  differential  signal  from  the  pre-amp,  and  provide  constant  output  amplitude  to  the  analog 
filter. It’s capable of accepting signal ranges from 50 mV to 400mVppd. 

 

 

5.2.3.3           Asymmetry Correction Circuitry (ASC)

 

 

The  ASC  circuit  is  designed  to correct  for  amplitude  asymmetry  introduced  by MR  heads.  The  compensation 
range  of  this  circuit  is  +/-30%.  This  circuit  allows  optimal  bias  current  to  be  used  independent  of  the 
asymmetry effect. 

Summary of Contents for Spinpoint M8

Page 1: ...M8 Product Manual 2 5 Hard Disk Drive March 6 2013 Rev 2 6...

Page 2: ...and one terabyte or TB equals one trillion bytes Your computer s operating system may use a different standard of measurement and report a lower capacity In addition some of the listed capacity is us...

Page 3: ...vity 17 4 5 DRIVE INSTALLATION 21 CHAPTER 5 DISK DRIVE OPERATION 22 5 1 HEAD DISK ASSEMBLY HDA 22 5 1 1 Base Casting Assembly 22 5 1 2 DC Spindle Motor Assembly 22 5 1 3 Disk Stack Assembly 24 5 1 4 H...

Page 4: ...tor Count Register and Sector Count Extended Register Ex 1F2h 40 6 3 4 6 Cylinder High Register and Cylinder High Extended Register Ex 1F5h 40 6 3 4 7 Cylinder Low Register and Cylinder Low Extended R...

Page 5: ...9h 37h extended 63 8 2 31 Set Multiple Mode C6h 63 8 2 32 Sleep E6h 63 8 2 33 Standby E2h 63 8 2 34 SMART B0h 64 8 2 34 1 Smart disable operations D9h 64 8 2 34 2 Smart enable disable attribute auto s...

Page 6: ...fy data structure 49 Table 8 4 Diagnostic Codes 50 Table 8 5 IDENTIFY DEVICE information 51 Table 8 6 Automatic Standby Timer Periods 56 Table 8 7 Security password content 60 Table 8 8 Security Erase...

Page 7: ...at might be helpful to the reader 1 1 User Definition The Spinpoint M8 product manual is intended for the following readers Original Equipment Manufacturers OEMs Distributors 1 2 Manual Organization T...

Page 8: ...channel works independently There is no sharing of interface master slave drive configuration and no master slave jumper settings This is different from Parallel ATA PATA architecture where 2 drives p...

Page 9: ...ctronics The drive s electrical interface is compatible with all mandatory optional and vendor specific commands within the ATA specification Drive size conforms to the industry standard 2 5 inch form...

Page 10: ...SR Pin 11 Device Activity Signal Activity LED Pin 11 Staggered Spin up Control Auto Activate DMA Setup FIS Native Command Queuing with queue depth of 32 First Party DMA Physical Event Counters Softwar...

Page 11: ...perature regulation The Spinpoint M8 hard disk drive satisfies the following standards and regulations Underwriters Laboratory UL Standard 1950 Information technology equipment including business equi...

Page 12: ...e Spinpoint M8 hard disk drive 3 1 Specification Summary Table 3 1 Specifications DESCRIPTION ST320LM001 ST500LM012 ST750LM022 ST1000LM024 Number of R W heads 2 3 4 4 Maximum KBPI 2418 Flexible data T...

Page 13: ...5 mm 2 750 0 0098 inch 9 5 0 2 mm 0 374 0 0079 inch 1 Disk 109 g 0 241 lb 2 Disk 117 g 0 258 lb 3 3 Logical Configurations Table 3 3 Logical Configurations 1MB 1 000 000 Bytes 1GB 1 000 000 000 Bytes...

Page 14: ...erage is incurred after a seek completion prior to reading or writing user data Startup time is the time elapsed between the supply voltages reaching operating range and the drive being ready to accep...

Page 15: ...ow Power Idle Watt 0 7 Read Write Watt 2 3 Seek Watt 2 0 Stand by Watt 0 2 Sleep Watt 0 2 Power Requirements Tolerance For 5V 5 Ripple 0 30MHz mVp p 100 Supply Rise Time us msec 10us 100ms Supply Fall...

Page 16: ...ration temperature 0 C 60 C 40 C 70 C 20 C 20 hr Relative Humidity non condensing Operation Non operation Maximum wet bulb temperature Operating Non operating 5 90 5 95 30 C 40 C Altitude relative to...

Page 17: ...Spinpoint M8 Product Manual REV 2 6 11 SPECIFICATIONS Figure 3 1 Measurement Position...

Page 18: ...ifications Table 3 7 Reliability Specifications DESCRIPTION ST320LM001 ST500LM012 ST750LM022 ST1000LM024 Recoverable Read Error 10 in 1011 bits Non Recoverable Read Error 1 sector in 1014 bits MTBF PO...

Page 19: ...LLATION This chapter describes how to unpack mount configure and connect a Spinpoint M8 hard disk drive It also describes how to install the drive in systems 4 1 Space Requirements Figure 4 1 shows th...

Page 20: ...protect the drive from ESD damage after removing it from the bag CAUTION During shipment and handling the anti static ESD protection bag prevents electronic component damage due to electrostatic disc...

Page 21: ...ATION 4 3 1 Orientation Figure 4 2 shows the physical dimensions and mounting holes located on each side of the drive The mounting holes on Spinpoint M8 hard disk drive allow the drive to be mounted i...

Page 22: ...within a point to point configuration with the SATA host port There is no master or slave relationship within the devices Thus SATA does not require master slave jumper The drive interface section of...

Page 23: ...inboard or Serial ATA host adapter Figure 4 5 Connectivity to Drives Figure 4 5 illustrates Connectivity of SATA to drives It can be used with a SATA host adapter lower picture or directly into mother...

Page 24: ...n the SATA interface and power connector It is based on SATA 1 0a Specifications Note that pin numbers is designated from the pin farthest from power segment Table 4 1 SATA Connector Pin Definitions D...

Page 25: ...face connector on the drive connects the drive to an SATA host bus adapter or an on board SATA adapter in the computer Figure 4 6 illustrates the power SATA and factory use only jumper Figure 4 7 show...

Page 26: ...Spinpoint M8 Product Manual REV 2 6 20 INSTALLATION Figure 4 7 Pin Locations on the Drive PCBA...

Page 27: ...nstallation The Spinpoint M8 hard disk drive can be installed in a SATA compatible system Figure 4 8 indicates the interface and power cable connections required for proper drive installation Figure 4...

Page 28: ...contamination in the HDA never remove or adjust its cover and seals Disassembling the HDA voids your warranty The Spinpoint M8 hard disk drive models and capacities are distinguished by the number of...

Page 29: ...Spinpoint M8 Product Manual REV 2 6 23 Cover Assembly Figure 5 1 Exploded Mechanical View...

Page 30: ...o the magnet yoke Pawl latch and rubber crash stops mounted on a magnetic yoke physically prevent the head s from moving beyond the designed inner boundary into the spindle or off the disk surface Cur...

Page 31: ...ore to perform the ATA interface control buffer data flow management disk format read write control and error correction functions of an embedded disk drive controller The DSP communicates with the di...

Page 32: ...t Manual REV 2 6 26 Disk Preamp Motor Control Format Sequencer Read Channel Host Interface Block SATA Host Bus 6 Gbps 32 bit ARM Disk Controller Buffer Control Block DDR Figure 5 2 Spinpoint M8 Functi...

Page 33: ...byte transfers Additional functionality is provided in the Host Interface Block by the following features Programmable transfer length for automatic ECC byte transfer on the AT bus Support of both LBA...

Page 34: ...programmed by the user to automatically control all single track format read and write operations From within the sequencer micro program the Disk Control block can automatically deal with such real...

Page 35: ...ctions include a time base generator AGC circuitry asymmetry correction circuitry ASC analog anti aliasing low pass filter analog to digital converter ADC digital FIR filter timing recovery circuits V...

Page 36: ...ted to digital signal with the ADC Its main function is to avoid aliasing for the ADC circuit 5 2 3 5 Analog to Digital Converter ADC and FIR The output of the analog filter is quantified using a 6 bi...

Page 37: ...a position loop with velocity damping Settle mode does not use feed forward 3 Velocity control mode is used for acceleration and deceleration of the actuator for seeking of two or more tracks A seek o...

Page 38: ...switches the Preamplifier and Write Driver IC to write mode and selects a head Once the Preamplifier and Write Driver IC receives a write gate signal it transmits current reversals to the head which...

Page 39: ...FY 3Ch INITIALIZE DEVICE PARAMETER 91h SLEEP 99h E6h STANDBY IMMEDIATELY 94h E0h READ BUFFER E4h WRITE BUFFER E8h WRITE SAME E9h 5 5 2 Write Caching Write caching improves both single and multi sector...

Page 40: ...d sector areas determined by the HDD firmware 5 5 5 SMART The intent of Self monitoring Analysis and Reporting Technology SMART is to protect user data and to minimize the likelihood of unscheduled sy...

Page 41: ...mes within the characters of the ALIGN primitive CODE VIOLATION A code violation is an error that occurs in the reception process as a result of 1 a running disparity violation or 2 an encoded charact...

Page 42: ...in First party DMA mode uses First party DMA as a primary communications method between the host and the device A software driver uses legacy mode commands to place the device into First party DMA mod...

Page 43: ...30 2004 available from http www serialata org retrieved and available on Jan 6 2005 6 3 1 Signal Descriptions For data packets and additional information please consult the document entitled Serial A...

Page 44: ...O registers Command Block registers When read When written Data Data Error Features Current Features Previous Sector Count Current Sector Count Previous Sector Count Current Sector Count Previous LBA...

Page 45: ...es Register and Feature Extended Register Ex 1F1h This register is command specific and used to enable and disable features of the interface e g by the Set Features command to enable and disable cachi...

Page 46: ...nded Register Ex 1F5h In CHS mode the Cylinder High Register contains the high order bits of the starting cylinder address for any disk access In LBA mode the Cylinder High Register contains bits 16 2...

Page 47: ...d If the host reads this register when an interrupt is pending it is considered to be the interrupt acknowledge Any pending interrupt is cleared whenever this register is read 7 6 5 4 3 2 1 0 BSY DRDY...

Page 48: ...e host floating devices that support staggered spin up disable through pin 11 shall enable staggered spin up 7 3 Auto Activate in DMA Setup FIS Spinpoint M8 implemented the option for the Auto Activat...

Page 49: ...hy Event Counter Supports Identifier Bits 11 0 Mandatory Optional Supported Description 000h Mandatory Y No counter value marks end of counters in the page 001h Mandatory Y Command failed due to an IC...

Page 50: ...sfer Mode o Read Look Ahead Set Multiple Mode 7 7 SATA Power Management Spinpoint M8 supports SATA power management from the SATA I and SATA II specifications The SATA power management is designed to...

Page 51: ...Device Configuration B1h Overlay 1 Execute Device 90h Diagnostic 1 Flush Cache E7h 1 Flush Cache Extended EAh 1 Format Track 3 50h 1 Initialize Device 91h Parameters 3 1 Identify Device ECh 1 Idle E3...

Page 52: ...B0h y y y y y 1 Standby E2h y 1 Standby Immediate E0h 1 Write Buffer E8h 1 Write DMA CAh y y y y y 1 Write DMA Extended 35h y y y y y y y y y 2 Write FPDMA Queued 61h y y y y y y y y y y 1 Write Log E...

Page 53: ...es Table 8 2 Device Configuration Overlay Feature Register Values Value Command C0h Device Configuration Restore C1h Device Configuration Freeze Lock C2h Device Configuration Identify C3h Device Confi...

Page 54: ...support for Ultra DMA mode 4 and below is allowed 3 1 Reporting support for Ultra DMA mode 3 and below is allowed 2 1 Reporting support for Ultra DMA mode 2 and below is allowed 1 1 Reporting support...

Page 55: ...When the command is issued prepares to transfer the 256 words of device identification data to the host sets the DRQ bit clears the BSY bit and generates an interrupt The host can then transfer the d...

Page 56: ...logical cylinders 2 0 Reserved 3 00XXh Number of logical heads 4 5 0 Retired 6 003Fh Number of logical sectors per logical track 7 8 0 Reserved for CFA 9 0 Retired 10 19 Serial number 20 ASCII charact...

Page 57: ...in nanoseconds 120ns 16 6MB S 66 0078h Manufacturer s recommended Multiword DMA transfer cycle time 15 0 Cycle time in nanoseconds 120ns 16 6MB S 67 0078h Minimum PIO transfer cycle time without flow...

Page 58: ...be set to one 13 1 FLUSH CACHE Ext supported 12 1 Mandatory FLUSH CACHE command supported 11 1 Device Configuration Overlay features supported 10 1 48 bit address feature supported 9 Reserved 8 1 SET...

Page 59: ...ress feature supported 9 Reserved 8 1 SET MAX security feature enabled by SET MAX SET PASSWORD 7 1 Set Address Offset Reserved Area Boot INCITS TR27 2001 6 1 SET FEATURES subcommand required to spin u...

Page 60: ...Request Size 96 0000h Streaming Transfer Time DMA 97 0000h Streaming Access Latency DMA and PIO 98 99 0000h Streaming Performance Granularity 100 103 xxxxh Maximum User LBA for 48 bit address 100 LSB...

Page 61: ...Count register is non zero then the automatic Idle Mode sequence is enabled and the timer begins counting down immediately If the Sector Count register is zero the automatic power down sequence is di...

Page 62: ...ears BSY and generates an interrupt The host then reads up to 512 bytes of data from the buffer The Read Buffer and Write Buffer commands are synchronized so that sequential Write Buffer E8h and Read...

Page 63: ...9h extended The Read Multiple command performs similarly to the Read Sectors command except interrupts are not generated on every sector but on the transfer of a block which contains the number of sec...

Page 64: ...Once at the desired track the drive searches for the appropriate ID field If the ID is read correctly the data address mark shall be recognized within a specified number of bytes or the Address Mark N...

Page 65: ...nt of the security password If the password selected by word 0 matches the password previously saved by the device the device shall unlock mode This command shall not change the Master password The Ma...

Page 66: ...rozen mode the command executes and the device shall remain in frozen mode Commands disabled by SECURITY FREEZE LOCK are as follows SECURITY SET PASSWORD SECURITY UNLOCK SECURITY DISABLE PASSWORD SECU...

Page 67: ...s of data from the host If the Identifier bit is set to Master and the device is in high security level then the password supplied shall be compared with the stored Master password If the device is in...

Page 68: ...ransition SC 06 Software Settings Preservation AAh Enable read look ahead feature BBh Obsolete Set 4 byte ECC length D2h DFh VU Features F0h FFh VU Features When the drive receives this command it che...

Page 69: ...Multiple commands and execution of those commands is enabled If a block count is not supported an Aborted Command error is posted and Read Multiple and Write Multiple commands are disabled At power o...

Page 70: ...of SMART either enabled or disabled shall be preserved by the device across power cycles After receipt of this command by the device all other SMART commands including SMART DISABLE OPERATIONS comman...

Page 71: ...f the new command After servicing the interrupting command from host the device may immediately re initiate or resume its off line data collection activities without any additional commands from host...

Page 72: ...cific 367 F Off line data collection capability 368 369 F SMART capability 370 F Error logging capability 7 1 Reserved 0 1 Device error logging supported 371 X Vendor specific 372 F Short self test ro...

Page 73: ...ngth Total number of the attributes is 30 Each attribute defines Attribute ID Status Flag Attribute Value and Vendor Specific bytes The Attribute ID is range from 01h to FFh The Vendor Specific bytes...

Page 74: ...eration of the device or during both normal operation and off line testing 2 Performance 1 Attributes that characterizes a performance aspects of the drive degradation of which may indicate imminent d...

Page 75: ...Pending sector count Off line scan pending sectors 198 Uncorrectable sector count Off line scan uncorrectable sectors 199 UDMA CRC error rate CRC Errors during UDMA transfer 200 Write error rate Erro...

Page 76: ...completed having the electrical element of the test failed 6 The previous self test completed having the servo and or seek test element of the test failed 7 The previous self test completed having the...

Page 77: ...ediately upon return to Active or Idle mode from a Standby mode Bit 1 SMART data auto save after event capability bit The value of this bit shall be equal to one for devices complying with this standa...

Page 78: ...available Any error encountered during Write DMA execution results in the termination of data transfer The drive issues an interrupt to indicate that data transfer has terminated and the status is ava...

Page 79: ...he Sector Count register contains the number of sectors not the number of blocks or the block count requested If the number of requested sectors is not evenly divisible by the block count as many full...

Page 80: ...the Command Block registers contain the cylinder head and sector number of the last sector written in CHS mode or the logical block address in LBA mode If an error occurs during a write of more than...

Page 81: ...e when handling the Spinpoint M8 hard disk drive 5 Do not touch cover and the components on the PCB Please see the Fig 9 2 6 Do not stack the HDDs in column Please see the Fig 9 3 7 Avoid harsh shocks...

Page 82: ...Spinpoint M8 Product Manual REV 2 6 76 Fig 9 1 HDD handling guide Please handle HDD by side surfaces Fig 9 2 HDD handling guide Do not Touch Cover and PCB Fig 9 3 HDD handling guide Do Not Stack...

Page 83: ...pecific drive use a web browser to access the following web page http www seagate com support warranty and returns From this page click on the Verify Your Warranty link You will be asked to provide th...

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