ST2115
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26
The flip-flop circuits:
The flip-flop circuits when used in this way is called a shift register since each clock
pulse applied to the flip-flops causes the contents of each flip-flop to be shifted to the
right. The feedback connections provide the input to the left-most flip-flop. With N
binary stages, the largest number of different patterns the shift register can have is 2N.
However, the all-binary-zero state is not allowed because it would cause all remaining
states of the shift register and its outputs to be binary zero. The all-binary-ones state
does not because a similar problem of repeated binary ones provided the number of
flip-flops input to the module 2 adder is even. The period of the PN sequence is
therefore 2N-1.
Starting with the register in state 001 as shown, the next 7 states are 100, 010, 101,
110, 111, 011, and then 001 again and the states continue to repeat. The output taken
from the right-most flip-flop is 1001011 and then repeats. With the three stage shift
register shown, the period is 23-1 or 7.
The PN sequence in general has 2N/2 binary ones and [2N/2]-1 binary zeros. As an
example, note that the PN sequence 1001011 of period 23-1 contains 4 binary ones
and 3 binary zeros. Furthermore, the numbers of times the binary ones and zeros
repeat in groups or runs also appear in the same proportion they would if the PN
sequence were actually generated by a coin tossing experiment.
The flip-flops which should be tapped-off and fed into the module 2 adder are
determined by an advanced algebra which has identified certain binary polynomials
called primitive irreducible or unfactorable polynomials. Such polynomials are used
to specify the feedback taps. For example, IS-95 specifies the in-phase PN generator
shall be built based on the characteristic polynomial PI(x) = x15 + x13 + x9 + x8 + x7
+ x5 + 1 (1)
Now visualize a 15 stage shift register with the right-most stage numbered zero and
the successive stages to the left numbered 1, 2, 3 etc., until the left-most stage is
numbered 14. Then the exponents less than 15 in Eq. (1) tell us that stages 0, 5, 7, 8,
9, and 13 should be tapped and summed in a module 2 adder. The output of the adder
is then input to the left-most stage. The shift register PN sequence generator is shown
below.
Figure 10
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