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5-4

Applications

Date Code 20010515

SEL-2BFR, -2/BFR Instruction Manual

between the secondaries of potential transformers connected on both sides of the protected
breaker.

If the potential transformers on each side of the breaker do not have identical turns ratios, you
must install a voltage balancing circuit between the secondary on one potential transformer and
the voltage input to the relay. Figure 5.3 shows one circuit you can use to balance the input
voltage.

If you do not wish to use voltage-based breaker protection features such as resistor thermal
protection, flashover protection, and breaker voltage warning, you need not connect the voltage
inputs.

Example Breaker

Figure 5.3 shows the example breaker arrangement. Table 5.1 lists pertinent breaker, line, and
system information.

Table 5.1: Example Line/Breaker Information

System per-unit bases:

525 kV; 100 MVA; 2756

Ω

; 110.0 A

Line

length:

100

miles

Line impedances:

Z1 = Z2 = 0.0218 pu
Z0 = 0.0758 pu

Source impedances:

ZS1 = 0.0034 pu
ZS0 = 0.0055 pu

Three-pole

tripping

Zone 1, three-phase minimum
fault duty:

I

3ph

= 49.6 pu = 5456 A

Line charging current:

I

c

= 350 A

CTR:

3000/5

(600/1)

PTR:

4300/1

Breaker:

Cogenel Type PK-8E (Air Blast)
500 kV, 3000 A, 3800 MVA

Maximum trip time:

2 cycles

Nominal close time:

10 cycles

Close

resistors:

35

Ω

/column, 2 columns

Trip

resistors:

110

Ω

/column, 2 columns

Transfer trip channel time:

0.5 cycle

Scheme Overview

The protection scheme in this example protects the breaker for all failures to trip. When fault
current exceeds the minimum three-phase fault duty for a Zone 1 fault, the fault must be cleared

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Summary of Contents for SEL-2BFR

Page 1: ...SEL 2BFR 2 BFR BREAKER FAILURE RELAY AND MONITOR INSTRUCTION MANUAL 20030207 SCHWEITZER ENGINEERING LABORATORIES 2350 NE HOPKINS COURT PULLMAN WA USA 99163 5603 TEL 509 332 1890 FAX 509 332 7990 ...

Page 2: ...trademark of their respective holders ACSELERATOR Connectorized CONSELTANT Job Done Schweitzer Engineering Laboratories SEL SELOGIC and SEL PROFILE are registered trademarks of Schweitzer Engineering Laboratories Inc The English language manual is the only approved SEL manual Copyright SEL 1990 1991 1992 1994 1996 1998 1999 2001 2003 All rights reserved Printed in USA This product is covered by U ...

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Page 5: ...0FT pickup on IRIG B operation in Section 2 Specifications and Section 5 Applications 990714 Changed footers on entire manual to reflect SEL 2BFR 2 BFR Added Model Variation Information to Section 1 Introduction Incorporated SEL 2BFR 2 Time Delayed Retrip Logic into Section 2 Specifications Modified AND and OR gate numbering in Section 2 Specifications Reformatted Settings Sheets at end of Section...

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Page 7: ... CONTENTS SECTION 1 INTRODUCTION SECTION 2 SPECIFICATIONS SECTION 3 COMMUNICATIONS SECTION 4 EVENT REPORTING SECTION 5 APPLICATIONS SECTION 6 INSTALLATION SECTION 7 MAINTENANCE AND TESTING SECTION 8 APPENDICES Appendix A Firmware Versions in This Manual Appendix B Internal Diagrams Appendix C SEL BFR Specifications ...

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Page 9: ... CONTENTS SECTION 1 INTRODUCTION 1 1 Getting Started 1 1 Overview 1 1 Relay Features 1 1 Model Variations 1 2 SEL BFR 1 2 SEL 2BFR Relay 1 2 2BFR 2 Relay 1 2 Conventional Terminal Block 1 2 Plug In Connector 1 3 Phase Rotation 1 3 System Frequency 1 3 General Description 1 3 ...

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Page 11: ...ure timing an application outline that guides settings selection and Settings Sheets Section 3 Communications for a description of the commands used to set the relay for protection set the relay for control obtain target information obtain metering information etc Section 4 Event Reporting for a description of event report generation summary event reports long event reports and their interpretatio...

Page 12: ...DEL VARIATIONS SEL BFR This manual is written for SEL 2BFR relays For SEL BFR relays substitute SEL BFR for each reference to SEL 2BFR Refer to Appendix C SEL BFR Specifications for SEL BFR general specifications and drawings SEL 2BFR Relay The basic SEL 2BFR relay has all the features outlined in the preceding Overview 2BFR 2 Relay This variation adds a timer RTSD Retrip Seal In Delay to delay th...

Page 13: ...cy of 60 Hz For relays which specify a nominal frequency of 50 Hz substitute 50 Hz for each reference to 60 Hz References made to a sampling time of 1 240 seconds should be replaced with a time of 1 200 seconds GENERAL DESCRIPTION The SEL 2BFR Relay is a single or three pole breaker failure protection and monitoring package The relay provides classical overcurrent based breaker failure protection ...

Page 14: ...ersonnel The relay also includes Programmable Mask Logic which allows you to configure the 86BF TRIP and five auxiliary outputs to operate when any of 40 protective elements or logic outputs pick up You can implement complete application specific protective schemes with a minimum of wiring and panel space Programmable Mask Logic also simplifies relay testing Communications functions provide remote...

Page 15: ...puts use Euro style plugs CT PT and power connectors come with factory crimped custom wiring harnesses Shorting mechanisms within CT plugs automatically short CT secondaries upon removal of the plugs from the relay High current interrupting contacts are standard on the SEL 2BFR plug in connector model These contacts use an electromechanical relay with solid state circuitry to interrupt dc currents...

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Page 17: ...6 Programmable Outputs A1 A2 A3 A4 A5 2 6 ALARM Output 2 7 Relay Word 2 7 Programmable Output Logic 2 9 Relay Targets 2 10 Signal Processing 2 11 Logic Description 2 11 Protection While Tripping Fault Current 2 12 Scheme 1 2 12 Scheme 2 2 13 Scheme 3 2 13 Scheme 4 2 14 Scheme 5 2 14 Scheme 6 2 15 Protection While Tripping Load or Line Charging Current 2 17 Thermal Protection of Close and Trip Resi...

Page 18: ...ront Panel Target Illumination Conditions 2 10 Table 2 5 Power Supply Self Test Limits 2 33 FIGURES Figure 2 1 A Phase Failure to Trip for Fault Logic Scheme 1 2 13 Figure 2 2 A Phase Failure to Trip for Fault Logic Scheme 2 2 13 Figure 2 3 A Phase Failure to Trip for Fault Logic Scheme 3 2 14 Figure 2 4 A Phase Failure to Trip for Fault Logic Scheme 4 2 14 Figure 2 5 A Phase Failure to Trip for F...

Page 19: ...nd MOD Trip Logic MOD Trip Enabled 2 27 Figure 2 17 MOD Trip Enabled Logic Timing Diagram 2 28 Figure 2 18 52BV Logic 2 28 Figure 2 19 Programmable Logic Mask Analogy 2 35 Figure 2 20 50FT Pickup Time Curves 2 36 Figure 2 21 50FT Dropout Time Curves 2 36 Figure 2 22 50MD Pickup Time Curves 2 37 Figure 2 23 50MD Dropout Time Curves 2 37 Figure 2 24 50LD Pickup Time Curves 2 38 Figure 2 25 50LD Drop...

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Page 21: ... 365 V for 10 s Burden 0 07 VA 67 V 0 42 VA 150 V Power Supply Rated 125 250 Vdc Range 85 350 Vdc or 85 264 Vac Burden 15 W Interruption 30 ms 125 Vdc Ripple 100 Rated 24 48 Vdc Range 20 60 Vdc Burden 15 W Interruption 30 ms 48 Vdc Ripple 5 Note Interruption and Ripple per IEC 255 11 1979 Output Contacts Standard Terminal Block Option Make 30 A Carry 6 A continuous carry at 70 C 1 s Rating 50 A MO...

Page 22: ...nt All current ratings are at nominal input voltage Routine AC current inputs AC voltage inputs 2500 Vac for 10 s power supply optoisolated inputs Dielectric Strength and output contacts 3100 Vdc for 10 s Frequency and System Frequency 50 or 60 Hz are ordering options Rotation Phase Rotation ABC or ACB are ordering options Communications Ports EIA 232 Baud rate 300 9600 baud includes front and rea...

Page 23: ...e at 2 multiples of pickup Dropout Time Less than 1 1 cycles MOD Current Element 50MD Pickup Range 5 A Model 0 1 45 0 A 1 A Model 0 02 9 00 A Pickup Accuracy Steady State 0 025 A 5 Pickup Time Less than 1 1 cycles at 2 multiples of pickup Dropout Time Less than 1 55 cycles Load Line Charging Current Element 50LD Pickup Range 5 A Model 0 10 45 00 A 1 A Model 0 02 9 00 A Pickup Accuracy Steady State...

Page 24: ...nt 87UB 87UB Phase Current Unbalance Element 87UB detects phase discordance when the protected breaker closes For example A phase is unbalanced if phase current is above the 50LD setting in one or more phases and setting UB 87 IC IB IA IA Stabilization Time Less than 1 35 cycle Overpower Elements 37OP Pickup Range 5 A Model 0 1 3400 0 Watts 1 A Model 0 02 680 00 Watts Pickup Time Less than 2 10 cy...

Page 25: ...5 63 75 cycles in quarter cycle steps 62UF Phase Discordance Failure Timer 62UP Phase Discordance Pending Failure Timer 62M1 Maximum Bus Clearing Time 62M2 Maximum MOD Operate Time setting ranges 0 25 16383 75 cycles in quarter cycle steps Fixed Timers 62F1 Flashover Voltage Time Delayed Dropout Timer 5 cycles 62F2 Load Current Pickup Timer Flashover Logic 5 cycles 62F3 Trip or Close Dropout Timer...

Page 26: ...OUTPUTS The SEL 2BFR Relay has seven programmable output relays All outputs except the ALARM output are programmed with the LOGIC command All can be tested with the OUT n command All conventional terminal block model relay contacts are rated for circuit breaker tripping duty Any of the programmable outputs or the ALARM contacts may be configured as a or b when you order the relay The 86BF TRIP out...

Page 27: ...larm condition occurs RELAY WORD The Relay Word consists of five eight bit rows containing relay elements timer outputs and logic outputs Each bit in the Relay Word is either a logical 1 or logical 0 1 indicates that the element is picked up or logic condition is true 0 indicates that the element is dropped out or logic condition is false The logic description defines the logic conditions in the R...

Page 28: ...9H Flashover Overvoltage Element 2 ALRM Breaker Operation Alarms 2 TC C Phase Retrip Output 2 TB B Phase Retrip Output 2 TA A Phase Retrip Output 3 PDBF Phase Discordance Breaker Failure 3 PDPF Phase Discordance Pending Failure 3 87UA A Phase Discordance 3 87UB B Phase Discordance 3 87UC C Phase Discordance 3 86RS 86BF Reset 3 MDT MOD Trip 3 CTF Close Resistor Thermal Failure 4 CRFA A Phase Close ...

Page 29: ...t relays Logic masks are saved in nonvolatile memory with the other settings They are set with the LOGIC command and retained through losses of control power To program each logic mask select elements of the Relay Word If any element in the Relay Word asserts and the same element is selected in a logic mask the output contact associated with the logic mask operates The output equations follow the ...

Page 30: ...TER command to clear the ALARM LED when it asserts The PF LED illuminates if any pending failure bits routed to an output contact assert If the relay asserts the 86BF TRIP output the A B or C targets latch to indicate the failed breaker pole The 52A and MOD LEDs illuminate if the associated rear panel input is asserted The target LEDs that illuminated during the last trip output remain lit until o...

Page 31: ...amples equal to 1 2 3 4 Again the output is zero Every quarter cycle the relay computes a new value of P for each input The current value of P combines with the previous value renamed Q to form a Cartesian coordinate pair This pair represents the input signal as a phasor P Q The relay processes these phasor representations of the input signals The digital and analog filter net frequency response i...

Page 32: ... disables the 62TT timer The 62FC timer starts when the trip signal input asserts The 62FC timer continues to time until 50FT drops out or the timer expires When the 62FC timer expires the FBF bit in the Relay Word asserts In ring bus and breaker and a half installations it is possible for the trip input to assert before the 50FT overcurrent element picks up If the trip input asserts before the 50...

Page 33: ...re scheme If the 50FT element remains asserted until the 62FC timer expires the Relay Word FBF bit asserts If the breaker operates successfully the 50FT element drops out before the 62FC timer expires and FBF does not assert Although it is very simple and effective in single breaker arrangements Scheme 2 is not recommended when the protected breaker is part of a ring bus or breaker and a half inst...

Page 34: ...protection Use Scheme 4 breaker protection in single breaker ring bus or breaker and a half installations When the SEL 2BFR Relay trip input is asserted the 62TT pickup timer starts The trip input is latched and may be deasserted after a single quarter cycle assertion 62TT pickup time following trip input assertion the 62TT timer output asserts The timer output remains asserted for 62TT dropout ti...

Page 35: ... ring bus or breaker and a half installations When the SEL 2BFR Relay trip input is asserted the 62TT pickup timer starts The trip input is latched and may be deasserted after a single quarter cycle assertion Following trip input assertion and 62TT pickup time the 62TT timer output asserts The timer output remains asserted for one cycle Relay Word bit FBF asserts if 50FT picks up and asserts durin...

Page 36: ...eaker 1 If Breakers 1 and 2 both fail to interrupt fault current and Breaker 1 has Scheme 6 active breaker failure protection problems can result The breaker failure protection scheme at Breaker 2 tries to trip the immediate breakers surrounding it including Breaker 1 Breaker 1 is also failed so the breaker failure trip from Breaker 2 to Breaker 1 is ineffectual Breaker failure timer 62TT or 62FC ...

Page 37: ...e current remains above the 50LD threshold for the duration of 62LD the LBF bit in the Relay Word asserts When the phase current drops below the 50LD threshold both timers reset Because this logic is very sensitive the trip input must be asserted for two consecutive quarter cycles before this logic acknowledges the input This feature provides security against incidental trip input assertions In so...

Page 38: ...aker Aux Failure Logic Enable Seal In Y Yes Yes 1 Yes No N No Yes 2 No No OR 7 OR 1 OR 2 AND 1 OR 8 AND 2 OR 4 AND 3 TRIP A IA 50LD RELAY OR MANUAL TRIP 62LD 62LP AND 4 OR 5 AND 5 TRIP B IB 50LD RELAY OR MANUAL TRIP 62LD 62LP AND 6 OR 6 AND 7 TRIP C IC 50LD RELAY OR MANUAL TRIP 62LD 62LP 52A 86BF TRIP E62A Y setting 0 62AF 62AP APpu AFpu LPpu 0 0 LDpu 0 0 0 LPpu LDpu LPpu 0 LDpu 0 TRIP A TRIP B TR...

Page 39: ... CRP_ or TRP_ close or trip resistor pending failure bit asserts in the Relay Word If 37OP remains asserted until the resistor energy reaches the 26CF or 26TF value the CRF_ or TRF_ close or trip resistor failure bit asserts in the Relay Word The Relay Word bits CTF Close resistor Thermal Failure and TTF Trip resistor Thermal Failure assert when any Close or Trip resistor thermal model has reached...

Page 40: ...2 20 Specifications Date Code 20010515 SEL 2BFR 2 BFR Instruction Manual Figure 2 9 Trip and Close Resistor Thermal Protection Logic ...

Page 41: ...Date Code 20010515 Specifications 2 21 SEL 2BFR 2 BFR Instruction Manual Figure 2 10 Protection for Current Through an Open Breaker Logic ...

Page 42: ...tart and the AND 1 condition is latched in via OR 2 The timers will assert their outputs if current remains above the 50LD threshold and the trip and close inputs remain deasserted and breaker voltage stays below the 59FO pickup threshold until the 62FP and 62FF timers expire This causes the FOPF Flashover Pending Failure bit then the FOBF Flashover Breaker Failure bit to assert in the Relay Word ...

Page 43: ...ting equal to Y With this setting the relay starts the RTTD time delayed pickup timer when the A phase trip input is asserted if A phase current is above the 50LD relay element setting The timer runs as long as current is above the 50LD setting When the RTTD timer expires the relay sets the Relay Word TA bit The TA bit remains asserted for three cycles following dropout of the 50LD element You may...

Page 44: ...etrip by setting DRTE Delayed Retrip Enable equal to Y The RTSD timer has a default setting of 0 25 to provide a quarter cycle seal in delay To increase the seal in delay of the trip input enter the desired delay in the RTSD setting Note This setting should be less than the RTTD setting Timers RTTD and RTSD will start timing when the A phase trip input is asserted and the A phase current is above ...

Page 45: ...ogic MOD Trip Disabled Figure 2 14 shows the logic used to assert the 86BF trip output and the 86RS reset bit in the Relay Word when MOD Trip logic is disabled setting ModTrip N Figure 2 15 shows the MOD Trip Disabled logic timing Figure 2 14 86BF TRIP and Reset Logic MOD Trip Disabled When AND 1 output asserts the 62M1 timer starts and the 86BF Trip output asserts After the 62M1 timer expires if ...

Page 46: ... Figure 2 16 shows the logic used to assert the 86BF trip output and the 86RS reset bit in the Relay Word when MOD Trip logic is enabled Figure 2 17 shows the timing of the MOD Trip Enabled logic The 86BF Trip output asserts and the 62M1 timer starts when the Relay Word logically ANDed with the M86T mask is not zero If the 50MD elements have dropped out when the 62M1 timer expires the MDT MOD Trip...

Page 47: ...Date Code 20010515 Specifications 2 27 SEL 2BFR 2 BFR Instruction Manual Figure 2 16 86BF TRIP Reset and MOD Trip Logic MOD Trip Enabled ...

Page 48: ...ram 52BV Logic Figure 2 18 shows the logic used to determine the state of 52BV in the Relay Word The 52BV bit asserts if the 52A input is deasserted while no phase current is above the 50LD setting The 52BV bit deasserts when the 52A input asserts or when any phase current exceeds the 50LD setting Figure 2 18 52BV Logic ...

Page 49: ...led CB trip resistors put in service Failed CB close resistors put in service 52A contradicts voltage Current while open Trip while open CB did not close Blown pot fuse Current after MOD Trip MOD contradicts current MOD Trip failed Volts across closed CB Slow trip Slow close To view the ALRM message buffer execute the STATUS command The following items explain conditions that cause ALRM assertion ...

Page 50: ...rts if any phase 50LD element is picked up when the 62M2 timer expires following an 86BF Trip when MOD Trip logic is enabled MOD Contradicts Current ALRM asserts if MOD Trip is enabled the 50MD element is picked up and the MOD STATUS input is not asserted indicating that the MOD is open MOD Trip Failed ALRM asserts if MOD Trip MDT asserts but the trip is unsuccessful See Unsuccessful MOD Trip Alar...

Page 51: ...on 3 Communications IRIG B INPUT DESCRIPTION The port labeled J201 AUX INPUT accepts demodulated IRIG B time code input The IRIG B input circuit is a 56 ohm resistor in series with an optocoupler input diode The input diode has a forward drop of about 1 5 volts Driver circuits should put approximately 10 mA through the diode when on On the Plug in Connector Model Ports 1 and 2R may be configured t...

Page 52: ...er is interrupted or when you make a setting or logic change The relay stores 100 event summaries in nonvolatile memory The event summaries are retained through setting changes and losses of control power Summaries contain breaker operation data such as event type mechanical and electrical breaker operating times and the event date and time You can use this data to monitor breaker wear and more ef...

Page 53: ...s test Read Only Memory The relay checks the read only memory ROM by computing a checksum If the computed value does not agree with the stored value the relay declares a ROM failure There is no warning state for this test Analog to Digital Converter The relay verifies A D converter function by checking the A D conversion time The test fails if conversion time is excessive or a conversion starts an...

Page 54: ... SX and SY are closed so closure of contact X or Y causes A1 to pick up This is expressed in Boolean terms next to the A1 output contact by the notation X Y where indicates the logical OR operation This logic scheme may be modified by setting switches SX SY and SZ to other positions If an application requires combinations of contacts X Y and Z to control other auxiliary relays diodes must be used ...

Page 55: ... event report generation Logic masks are saved in nonvolatile memory with the other settings and retained through losses of control power Figure 2 19 Programmable Logic Mask Analogy OVERCURRENT ELEMENT OPERATING TIME CURVES The following figures illustrate the pickup and dropout times of the 50FT 50MD and 50LD phase overcurrent elements Ten tests were performed at each multiple of element setting ...

Page 56: ...7 0 8 0 9 1 0 0 1 2 3 4 5 6 7 8 9 10 Multiple of Setting Pickup Time Cycles Minimum Mean Maximum Figure 2 20 50FT Pickup Time Curves 50FT Setting 1 0 A sec 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 0 1 2 3 4 5 6 7 8 9 10 Multiple of Setting Dropout Time Cycles Minimum Mean Maximum Figure 2 21 50FT Dropout Time Curves ...

Page 57: ...2 1 3 1 4 1 5 1 6 0 1 2 3 4 5 6 7 8 9 10 Multiple of Setting Pickup Time Cycles Minimum Mean Maximum Figure 2 22 50MD Pickup Time Curves 50MD Setting 1 0 A sec 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 0 1 2 3 4 5 6 7 8 9 10 Multiple of Setting Dropout Time Cycles Minimum Mean Maximum Figure 2 23 50MD Dropout Time Curves ...

Page 58: ...1 2 1 3 1 4 1 5 0 1 2 3 4 5 6 7 8 9 10 Multiple of Setting Pickup Time Cycles Minimum Mean Maximum Figure 2 24 50LD Pickup Time Curves 50LD Setting 1 0 A sec 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 0 1 2 3 4 5 6 7 8 9 10 Multiple of Setting Dropout Time Cycles Minimum Mean Maximum Figure 2 25 50LD Dropout Time Curves ...

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Page 115: ...g Time Constants 5 17 Select Breaker Pole Flashover Settings 5 17 Select Phase Discordance Failure to Close Settings 5 18 87UB Unbalance Current Ratio 5 18 62UC Time Delay Pickup Timer Setting 5 18 62UF and 62UP Timer Settings 5 19 Select MOD Trip Logic Setting 5 19 MOD Trip Logic Enabled ModTrip Equals Y 5 19 50MD Overcurrent Element Setting 5 19 62M1 and 62M2 Timer Settings 5 20 MOD Trip Logic D...

Page 116: ... 5 4 Table 5 2 Fault Current Scheme Setting Considerations 5 5 Table 5 3 Scheme Timing Considerations 5 11 FIGURES Figure 5 1 Basic Breaker Failure Protection Scheme 5 1 Figure 5 2 Basic Breaker Failure Scheme Timing 5 2 Figure 5 3 Single Phase of AC Inputs to the Relay 5 3 Figure 5 4 Scheme 1 Breaker Failure Timing 5 6 Figure 5 5 Scheme 2 Breaker Failure Timing 5 7 Figure 5 6 Scheme 3 Breaker Fai...

Page 117: ...ads are lost due to remote fault clearing which can be maintained using local breaker failure relaying Remote fault clearing is sequential requiring the local fault contribution to be cleared before remote relaying can detect the fault If the breaker fails to clear a fault all electrically adjacent breakers must be opened This stops a continuing fault and interrupts current flow in the failed brea...

Page 118: ...lay to protect a breaker independently for each of these failure types as shown below In ring bus and breaker and a half installations two circuit breakers must operate to interrupt line current Current distribution between the two breakers is unknown until the first breaker opens The bulk of fault current initially may be carried by a single breaker Both breakers receive the trip signal at the sa...

Page 119: ...t be processed during this period For 50FT element settings below load current 50FT element asserted during normal operating conditions consider one of the load breaker fail schemes Load current breaker fail schemes use the 50LD elements and the IRIG B time synchronizing function is unaffected Relay AC Current and Voltage Inputs To effectively protect a power circuit breaker that includes tripping...

Page 120: ...3 shows the example breaker arrangement Table 5 1 lists pertinent breaker line and system information Table 5 1 Example Line Breaker Information System per unit bases 525 kV 100 MVA 2756 Ω 110 0 A Line length 100 miles Line impedances Z1 Z2 0 0218 pu Z0 0 0758 pu Source impedances ZS1 0 0034 pu ZS0 0 0055 pu Three pole tripping Zone 1 three phase minimum fault duty I3ph 49 6 pu 5456 A Line chargin...

Page 121: ...le trip installations Table 5 2 Fault Current Scheme Setting Considerations Scheme Bus Configuration Operating Considerations 1 Single Breaker and a Half Ring Bus 62TTpu setting is not used Set 62TTdo greater than worst case protected breaker operating time Set 62FC greater than 62TTdo by at least two cycles relay logic requirement Trip input may be immediately deasserted 2 Single Breaker 62TT tim...

Page 122: ...al breaker operating time plus a safety margin 50FT reset time does not have to be taken into account 50FT setting must exceed maximum load current 62FC timer output asserts each time all three trip inputs assert Setting should be greater than local breaker operating time plus a safety margin 50FT reset time does not have to be taken into account See Figure 2 7 and accompanying note in Section 2 S...

Page 123: ...Date Code 20010515 Applications 5 7 SEL 2BFR 2 BFR Instruction Manual Figure 5 5 Scheme 2 Breaker Failure Timing Figure 5 6 Scheme 3 Breaker Failure Timing ...

Page 124: ...5 8 Applications Date Code 20010515 SEL 2BFR 2 BFR Instruction Manual Figure 5 7 Scheme 4 Breaker Failure Timing Figure 5 8 Scheme 5 Breaker Failure Timing ...

Page 125: ...alled upon to trip phase current greater than the 50FT setting Note The SEL 2BFR Relay does not discriminate between phase faults and ground faults Fault discrimination is based strictly upon phase current magnitude Breaker operations for ground faults with current duties above the 50FT setting are protected under the failure to break fault current logic For our example system conditions require t...

Page 126: ...ed on the 50FT overcurrent element can still pick up 8 A secondary 8 A secondary 12 100 7 A secondary In this case even though setting 50FT 8 00 A secondary the 50FT overcurrent element can still pick up for 7 A secondary Select Scheme Timer Settings Select the scheme timer settings based upon the following factors Maximum permissible fault duration Protective relay operating time Protected breake...

Page 127: ...ime is the sum of the front end analog filter dropout time less than a quarter cycle the First Order Difference FOD digital filter dropout time vast majority of the reset time The digital filter is disabled while the 62TT or 62FC pickup timers are timing in Scheme 6 Thus 50FT element reset time does not have to be taken into account as part of the safety margin incorporated into the 62TT and 62FC ...

Page 128: ...ic please refer to the logic descriptions before finalizing your 50LD setting selection When the protected breaker is part of a ring bus or breaker and a half installation load current may be very low due to unequal current distribution between the two breakers Failure to trip load current logic may still be used to protect the breaker Because current application may be sequential there is an unce...

Page 129: ...te the 86 lockout relay if the relay 52A input is not deasserted after a settable time delay In our example application this logic is not used The E62A setting is set equal to N The time delay settings should be selected based upon the maximum time permissible to operate the protected equipment under low or zero current conditions A slightly larger safety margin should be considered for this logic...

Page 130: ...ft in service following a breaker operation The relay can detect that condition model the energy accumulated in the resistor and trip the protected breaker or 86 lockout relay when resistor energy reaches a preset level Operation of the thermal protection logic is described in Section 2 Specifications Setting selection is described below 37OP Setting Select a 37OP element setting such that the ele...

Page 131: ...s In the example breaker the trip resistors consist of 88 ceramic disks having a volume per disk of 225 cm3 and a maximum thermal capacity of 700 Joules cm3 The maximum thermal stress per head is found secondary J 5 37 PTR CTR primary MJ 86 13 TS pole breaker per primary MJ 86 13 TS cm J 700 cm 225 disks 88 TS SEC MAX 3 3 MAX Thermal failure settings should prevent a normal trip and close operatio...

Page 132: ... pole trip installations single pole trip operations do not adversely affect the thermal models because current does not flow in the open pole Calculate the magnitude of negative sequence voltage for given phase voltages using the following equation o o 240 1 a and 120 1 a where aVC VB a VA 3 1 2 V 2 2 When the A phase potential fuse blows the magnitude and angle of negative sequence voltage prese...

Page 133: ...at cooling from 200 C to near ambient temperature takes four hours or three time constants 95 percent cooled This implies a cooling time constant of minutes 80 3 minutes 240 CRTC For the example 80 minute cooling time constants were selected for CRTC and TRTC If you select an inaccurate cooling time constant the resistor energy models may not be realistic for some time after breaker operations For...

Page 134: ... Assume 87UB equals eight and one per unit current flows in each breaker pole upon closure If A phase and B phase breaker poles close while the C phase pole remains open the relay makes the following comparisons 8 current unit per 2 pu 0 Ic 8 current unit per 2 pu 1 Ib 8 current unit per 2 pu 1 Ia 8 I I I pu 1 Ia c b a 87UC asserts because C phase current is less than the sum of phase current magn...

Page 135: ...e status Logic Description in Section 2 Specifications provides operational descriptions of SEL 2BFR Relay MOD Trip logic If you want the relay to operate a motor operated disconnect switch automatically to isolate a failed breaker set ModTrip to Y If you do not use an MOD on the protected breaker consider using this logic to indicate a Safe to Disconnect condition for station personnel If you do ...

Page 136: ...ns also determine the magnitude of secondary fault current presented to the relay It is desirable to keep secondary CT currents between 50 and 100 A during maximum short circuit conditions This reduces the likelihood of CT saturation and allows the current transformer to deliver a reliable secondary representation of the primary current during a fault condition The example protected breaker is equ...

Page 137: ...IME2 0 minutes Select the Autoport Setting AUTO AUTO specifies the port to which the relay sends automatically generated messages If a port is timed out see TIME1 and TIME2 settings the relay does not send automatic messages to that port even if the port is selected by the AUTO setting The relay can send automatic messages to PORT 1 only AUTO 1 PORT 2 only AUTO 2 or both ports AUTO 3 For the examp...

Page 138: ... 0 AUTO 2 RINGS 3 Note The SEL 2BFR 2 Relay includes the RTSD setting not shown Logic Mask Setting Selection Section 2 Specifications explains the operational concept of programmable logic masks used in the SEL 2BFR Relay Example logic mask settings below are provided to illustrate relay function and application Please select logic mask settings particular to your application Figure 5 10 and Figur...

Page 139: ...C TRPC DOPA DOPB DOPC 47Q 0 0 0 0 0 0 0 0 These settings cause the 86BF TRIP output contacts to close when one of the following occurs failure to trip fault current FBF trip resistor thermal failure TTF failure to trip load current LBF breaker pole flashover failure FOBF phase discordance breaker failure PDBF or close resistor thermal failure CTF MER Logic Mask Triggers Event Report Generation Ele...

Page 140: ...etting the A1 contact closes for one second when a breaker operation alarm occurs These alarm conditions are defined in Section 2 Specifications Logic Mask MA1 FBF LBF LPF 50FT 50LD 50MD 52BV TTF 0 0 0 0 0 0 0 0 FOBF FOPF 59FO 59H ALRM TC TB TA 0 0 0 0 1 0 0 0 PDBF PDPF 87UA 87UB 87UC 86RS MDT CTF 0 0 0 0 0 0 0 0 CRFA CRPA TRFA TRPA CRFB CRPB TRFB TRPB 0 0 0 0 0 0 0 0 CRFC CRPC TRFC TRPC DOPA DOPB...

Page 141: ... failure occurs the A4 contact asserts the second trip coil in an attempt to open the breaker before the 86 lockout relay is asserted by the SEL 2BFR Relay 86BF Trip output Logic Mask MA4 FBF LBF LPF 50FT 50LD 50MD 52BV TTF 0 0 1 0 0 0 0 0 FOBF FOPF 59FO 59H ALRM TC TB TA 0 1 0 0 0 0 0 0 PDBF PDPF 87UA 87UB 87UC 86RS MDT CTF 0 1 0 0 0 0 0 0 CRFA CRPA TRFA TRPA CRFB CRPB TRFB TRPB 0 1 0 1 0 1 0 1 C...

Page 142: ...a relay trip input when the DRTE setting equals N The trip bits assert with a settable time delay and overcurrent element supervision when the DRTE setting equals Y Figure 5 12 Three Pole Instantaneous Retrip Using the A1 Output Contact Single Pole Instantaneous or Time Delayed Retrip You may use three programmable output contacts to perform single pole instantaneous or time delayed retrip of the ...

Page 143: ...ingle pole open intervals you may want to use a time delayed pickup timer between the relay output contact and the annunciator input or indicator lamp The time delay should be set longer than the maximum single pole open interval Thus only permanent output contact closures activate the annunciator Hot Resistor Indication When you use the SEL 2BFR Relay breaker resistor thermal protection elements ...

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Page 145: ... ALRM TC TB TA ROW 3 Relay Word Binary Representation PDBF PDPF 87UA 87UB 87UC 86RS MTD CTF ROW 4 Relay Word Binary Representation CRFA CRPA TRFA TRPA CRFB CRPB TRFB TRPB ROW 5 Relay Word Binary Representation CRFC CRPC TRFC TRPC DOPA DOPB DOPC 47Q MASK MA1 A1 Contact Hexadecimal Setting ROW 1 Relay Word Binary Representation FBF LBF LPF 50FT 50LD 50MD 52BV TTF ROW 2 Relay Word Binary Representati...

Page 146: ...sentation FBF LBF LPF 50FT 50LD 50MD 52BV TTF ROW 2 Relay Word Binary Representation FOBF FOPF 59F0 59H ALRM TC TB TA ROW 3 Relay Word Binary Representation PDBF PDPF 87UA 87UB 87UC 86RS MTD CTF ROW 4 Relay Word Binary Representation CRFA CRPA TRFA TRPA CRFB CRPB TRFB TRPB ROW 5 Relay Word Binary Representation CRFC CRPC TRFC TRPC DOPA DOPB DOPC 47Q MASK MA4 A4 Contact Hexadecimal Setting ROW 1 Re...

Page 147: ...y Word Binary Representation CRFC CRPC TRFC TRPC DOPA DOPB DOPC 47Q MASK MER Event Report Trigger Hexadecimal Setting ROW 1 Relay Word Binary Representation FBF LBF LPF 50FT 50LD 50MD 52BV TTF ROW 2 Relay Word Binary Representation FOBF FOPF 59F0 59H ALRM TC TB TA ROW 3 Relay Word Binary Representation PDBF PDPF 87UA 87UB 87UC 86RS MTD CTF ROW 4 Relay Word Binary Representation CRFA CRPA TRFA TRPA...

Page 148: ...aker Auxiliary Failure Timer 0 25 63 75 cycles 62AF Enable Breaker Auxiliary Failure Logic Y or N E62A Delayed Retrip Enable Y or N DRTE Retrip Seal in Delay 2BFR 2 0 25 63 75 cycles RTSD 2 Delayed Retrip Time Delay 0 25 63 75 cycles RTTD Breaker Resistor Single phase Overpower 0 10 3400 Watts 5 Amp 0 02 680 Watts 1 Amp 37OP Close Resistor Fail Energy 0 01 1000 Joules 5 Amp 0 002 200 0 Joules 1 Am...

Page 149: ... 1 Amps Volts and Joules settings are in secondary quanitites MOD Operate Current 0 10 45 00 Amps 5 Amp 0 02 9 0 Amps 1 Amp 50MD 86BF Reset Timer M1 TDPU 0 25 16 383 75 cycles 62M1 86BF Reset Timer M2 TDPU 0 25 16 383 75 cycles 62M2 Enable MOD Trip Logic Y N ModTrip Per Unit Current Transformer Ratio 1 10 000 CTR Per Unit Potential Transformer Ratio 1 10 000 PTR CB Open Time Warning 0 25 63 75 cyc...

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Page 221: ...e Control Enable Jumper C 3 Output Contact Soldered Wire Jumpers C 3 Optoisolated Input Control Voltage Jumpers C 4 IRIG B Installation C 4 EIA 232 Installation C 5 EIA 232 Cables C 6 TABLES Table C 1 AUX INPUT Pin Definitions C 5 FIGURES Figure B 1 SEL 2BFR 2 Conventional Terminal Block Model Main Board Troubleshooting Test Points and Jumper Locations B 1 Figure B 2 SEL 2BFR 2 Plug in Connector M...

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Page 223: ... trip inputs in the time delay retrip logic This delay is accomplished with the addition of a time delay pickup timer RTSD Retrip Seal In Delay No other versions of the SEL 2BFR or SEL BFR are affected by this modification This firmware differs from previous versions as follows Corrected time delayed breaker retrip logic For single pole trip e g TRIP A input asserted the logic erroneously latched ...

Page 224: ...2LP and 62LD timer setting logic correction SEL BFR R114 SEL BFR R414 SEL BFR R703 SEL BFR R802 SEL BFR R903 100 Series 60 Hz 5 Amp 200 Series 60 Hz 5 Amp 200 Series 60 Hz 1 Amp 200 Series 50 Hz 5 Amp 200 Series 50 Hz 1 Amp This firmware differs from previous versions as follows Seal in inhibit of 62LP and 62LD timer logic SEL BFR R113 SEL BFR R413 SEL BFR R702 SEL BFR R801 SEL BFR R902 100 Series...

Page 225: ... Code 990714 Appendix B B 1 SEL 2BFR 2 BFR Instruction Manual APPENDIX B INTERNAL DIAGRAMS Figure B 1 SEL 2BFR 2 Conventional Terminal Block Model Main Board Troubleshooting Test Points and Jumper Locations ...

Page 226: ...B 2 Appendix B Date Code 990714 SEL 2BFR 2 BFR Instruction Manual Figure B 2 SEL 2BFR 2 Plug in Connector Model Main Board Troubleshooting Test Points and Jumper Locations ...

Page 227: ...e Code Input Relay accepts demodulated IRIG B time code Communications Two EIA 232 serial communications ports Dimensions 5 25 x 19 0 x 14 5 13 34 cm x 48 26 cm x 36 83 cm H x W x D Depth D is to end of the rear panel terminal blocks Mounting Available in horizontal and vertical mounting configurations Dielectric Strength V I inputs 2500 Vac for 10 seconds Other 3100 Vdc for 10 seconds excludes EI...

Page 228: ...ument The relay requires difference voltage potentials that must be obtained from voltage transformers on both sides of the circuit breaker if flashover and thermal protection functions are to be used Control Circuits The control inputs are dry For example to assert the 52A input you must apply control voltage to the 52A input terminals Each input is individually isolated and a terminal pair is br...

Page 229: ...selection Available baud rates are 300 600 1200 2400 4800 and 9600 To select a baud rate for a particular port place the jumper so it connects a pin labeled with the desired port to a pin labeled with the desired baud rate CAUTION Do not select two baud rates for the same port This can damage the baud rate generator Password Protection Jumper Put JMP103 in place to disable password protection This...

Page 230: ...opy of SEL UPDATE 94 10 please contact the SEL factory The new interface board also provides field selectable input voltage selection The operating voltages and jumper selection for each logic input are shown in the table below Relay Terminals 39 40 41 42 43 44 45 46 47 48 49 50 Control Voltage JMP11 JMP12 JMP9 JMP10 JMP7 JMP8 JMP5 JMP6 JMP3 JMP4 JMP1 JMP2 250 V 125 V 48 V IRIG B Installation To s...

Page 231: ...the IRIG command or auto matically two consecutive frames are taken The older frame is updated by one second and the two frames are compared If they do not agree the relay considers the data erroneous and discards it The relay reads the time code automatically about once every five minutes The relay stops IRIG B data acquisition ten minutes before midnight on New Year s Eve so the relay clock may ...

Page 232: ...und Conxall DTE Device 25 Pin Male D Subconnector Cable 422 SEL BFR Relay 9 Pin Male Round Conxall DCE Device 25 Pin Male D Subconnector female chassis connector as viewed from outside rear panel GND 1 TXD 2 RTS 3 RXD 4 CTS 5 GND 9 GND 1 TXD 2 RTS 3 RXD 4 CTS 5 GND 9 7 GND 3 RXD 5 CTS 2 TXD 4 RTS 1 GND 6 DSR 8 DCD 20 DTR 7 GND 2 TXD IN 20 DTR IN 3 RXD OUT 8 CD OUT 1 GND ...

Page 233: ...nxall DTE Device 9 Pin Female D Subconnector Cable 331A SEL BFR Relay 9 Pin Male Round Conxall SEL PRTU 9 Pin Male Round Conxall DTE Data Terminal Equipment Computer Terminal Printer etc DCE Data Communications Equipment Modem etc GND 1 TXD 2 RTS 3 RXD 4 CTS 5 GND 1 TXD 2 RXD 4 CTS 5 12 7 GND 9 5 GND 2 RXD 8 CTS 3 TXD 7 RTS 1 DCD 4 DTR 6 DSR 9 RI ...

Page 234: ...C 8 Appendix C Date Code 990714 SEL 2BFR 2 BFR Instruction Manual Figure C 2 Horizontal Front and Real Panel Drawings ...

Page 235: ...Date Code 990714 Appendix C C 9 SEL 2BFR 2 BFR Instruction Manual Figure C 3 Vertical Front and Rear Panel Drawings ...

Page 236: ...C 10 Appendix C Date Code 990714 SEL 2BFR 2 BFR Instruction Manual Figure C 4 Relay Dimensions Panel Cutout and Drill Plan ...

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