RTC
®
5 PC Interface Board
Rev. 1.9 e
4 Layout and Interfaces
53
innovators for industry
RTC
®
5 as receiver
The following specifications apply to receiver signals
of the McBSP interface (CLKR0, FSR0, DR0):
• Signal level 3.3 V or 5 V TTL.
• McBSP mode:
– Single phase frame
– Single element per frame
– 32 bits per element
– DataDelay N bit
• The pulse diagram of the McBSP signals is shown
in
FrameSync pulse generated upon a rising edge (of
an external clock signal) is detected upon the
clock’s next falling edge (trailing edge of the
external clock pulse). The FrameSync pulse’s
length is irrelevant. Upon the (external) clock’s
next 32 falling edges, 32 data bits in the sequence
Bit #31…Bit #0 will be detected, provided they
are transmitted with rising edges. Take account of
the following information:
– The bit frequency (receiving frequency) is exclu-
sively determined by the incoming clock pulses
and has a maximum limit of 16 MHz.
– The last data bit (Bit #0) must be followed by
transmission of at least one additional external
clock pulse to ensure that the interface’s DSP
side acquires and buffers the data word. Simul-
taneously with this clock pulse, you can already
initiate another new transfer via a FrameSync
pulse.
• As of OUT 526: After a
McBSP data will internally be permanently
acquired and buffered as soon as (new) data is
transmitted. Newer data words overwrite older
ones.
– After a reset via
after activation of Processing-on-the-fly correc-
tion via
, the input values will be stored
to internal memory location 0.
– After activation of online positioning via
,
or
, the
input values will be stored to internal memory
locations 1 or 2 (see
).
– The most recent fully transferred values can be
queried from a corresponding memory location
via
.
The McBSP interface always ignores the first
FrameSync signal after a
or
, so available data won’t be trans-
mitted. If necessary, a dummy value should be
initially sent to the interface (this applies to both
Processing-on-the-fly applications and online
positioning). You can use
to check
for successful transmission.
• If using version OUT 525 or older, also see
“Version info” under
and
.
• As of OUT 532: After activation of Processing-on-
or
, the input values will be trans-
ferred to internal memory locations 0 and 3.
• As of OUT 537: After activation of Processing-on-
or
, the input values will be
transferred to internal memory locations 0
through 3.
4.4.7 Stepper Motor Control
The “STEPPER MOTOR” connector can supply signals
for controlling two stepper motors
(1)
. The pin-out is
shown in
All signals are referenced to PC ground GND.
The outputs (ENABLE, DIRECTION and CLOCK) are TTL-
level signals (5 V). The RTC
®
5 generates a periodic
clock signal of active-high 5
µ
s pulses (the CLOCK
signal is permanently LOW between these pulses).
The ENABLE signals can, for example, be used for
switching the motor current on and off. The
DIRECTION signals can set the direction and each
CLOCK pulse can be used to execute a single step.
The SWITCH inputs (active low) are connected inter-
nally to +3.3 V via 10 k
pull-up resistors to facilitate
integration of a final switch signal (3.3 V or 5 V TTL
signal or input referenced to ground).
(1) Stepper motor signals are available only for RTC
®
5 boards with
DSP version numbers 2 and higher (see
bits
#16-23). For older RTC
®
5 boards, stepper motor commands
will not execute.
23
SWITCH1 (1)
ENABLE1 (3)
DIRECTION1 (5)
CLOCK1 (7)
GND (9)
(2) SWITCH2
(4) ENABLE2
(6) DIRECTION2
(8) CLOCK2
(10) GND
Pin-out of (on-board) “STEPPER MOTOR” connector