RTC
®
5 PC Interface Board
Rev. 1.9 e
10 Commands And Functions
412
innovators for industry
Ctrl Command set_control_mode
Function
enables or disables the external control input for external list starts, locks or unlocks the
external control input for external list stops and resets the counter for external list starts to
zero.
Call
set_control_mode( Mode )
Parameter
Mode
(as an unsigned 32-bit value):
Bit #
Value
Description
Bit #0 (LSB)
= 1:
The external start input (via /START, /START2 or /Slave-START) is enabled.
= 0:
The external start input is disabled.
Bit #1
= 1:
An external list stop (/STOP, /STOP2, /Slave-STOP or
)
causes explicit cancellation of the external start queue’s entries (/START,
/START2, /Slave-START or
= 0:
no effect
Bit #2
= 1:
The track delay (defined via
,
or
) that postpones execution of the list start relative to
the triggering input signal or
command (see
"External List Start", page 210
) is deactivated.
= 0:
No effect. To define and activate the track delay (e.g. for Processing-on-the-fly
applications), use the command
.
Bit #3
= 1:
The external start input is
not
disabled by an external stop request.
= 0:
The external start input
is
disabled by an external stop request.
Bits #4-8
Reserved.
Bit #9
= 1:
Encoder resets of the two internal encoder counters (initiated by the
Processing-on-the-fly commands
) occur
after the subsequent start trigger (i.e. the subsequent external start signal or
command, possibly
postponed by a track delay defined via
, also see bit #2).
= 0:
Encoder resets occur immediately with each initiating Processing-on-the-fly
command.
Bits #10
= 1:
or
will be counted beginning with the most recent
etc.) triggered or simulated
external list start. The interval between subsequent external list starts (in
encoder pulses) will thus be constant (also see
). For
or an external stop signal, bit #10 will get reset to “0”. This
bit has no effect if the firmware version is 506 or lower (see
= 0:
or
will be counted beginning with the time point an
external list start was requested (i.e. with the corresponding
signal). The interval between subsequent external list starts (in encoder
pulses) can thus vary. This is standard for firmware version 506 or lower (see
).
Bits #12-15
reserved Version info
Comments
• If execution is aborted by the command
, then bit #0 and bit #10 will
get reset to zero, thus deactivating external start inputs and the counting of track
delays with respect to a possible triggering event.
• If bit #9 = 0, then there will generally be a small (random) time offset (10
µ
s jitter)
between the start signal at /START, /START2 and the actual list start. If bit #9 = 1, then
this 10
µ
s jitter won’t be present because the encoder reset then occurs synchronously
with the start signal.
• Also see
"External List Stop", page 209
and
"External List Start", page 210
.