SATEL Proof-TR4+/R4+/TR9
User Guide, Version 2.2
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CRC8 Partial
verifies the data in small blocks and they are delivered to DTE as sub messages
after validating. Once an error is detected, the rest of the message is ignored. In practice, if the
error appears in the middle of the message, the first part is forwarded to DTE and the data in
erroneous sub-message and after that will be lost.
CRC16 Full and CRC 8 Full check
adds checksum characters accordingly at the end of the user
data message. At the reception end the receiver receives first the whole package and if the
checksum matches the data message is forwarded to the serial port.
!
CRC-8 Partial and CRC-8 Full check activate an internal control on the radio link. These
checksum types can’t be
viewed in the serial line data flow.
CRC-16 Full check adds the checksum to data. It is possible include the checksum into the
received data in the serial line by setting the CRC16 Full check to OFF state at the receiving
radio(s).
In typical use case, if checksum is preferred in the system, it is recommended to use the
CRC-16 Full check -mode and set the parameter equally to the radios in the same radio
network. Additional data transfer delay will be added approximately according to the data
packet size to the total transfer delay.
8.8
TX delay
The transceiver can be configured to delay the beginning of a radio transmission by 1...65000
ms. The function can be used to prevent packet contention in a system, where all substations
would otherwise answer a poll of a base-station simultaneously. During this delay data sent to
the radio modem is buffered. Even when the priority setting is "RX", the radio modem is
prevented to change over to the receiving mode during the period of the TX delay. If TX delay is
not needed, its value should be set to 0 ms.
8.9
Add RSSI to data
RSSI info "\02RSSI:-nnn dBm\03" will be concatenated to the end of serial port messages, nnn is three
digit decimal number.
8.10
Separate RX/TX-frequencies
Modem can transmit (TX-frequency) and receive (RX-frequency) on separate frequencies. The
switch between the frequencies introduces an extra 40 ms delay in the data transfer that must
be taken account when designing the system.