– 3 –
Fig. 1-1.Optical Black Location (Top View)
Pin No.
Symbol
Pin Description
Waveform
Voltage
Table 1-1. CCD Pin Description
When sensor read-out
Fig. 1-2. CCD Block Diagram
1. OUTLINE OF CIRCUIT DESCRIPTION
1-1. CCD CIRCUIT DESCRIPTION
1. IC Configuration
The CCD peripheral circuit block basically consists of the fol-
lowing ICs.
IC911 (RJ23Y3BA1LG)
CCD imager
IC901 (MAXT)
V driver
IC902 (AD9971BCPZRL)
CDS, AGC, A/D converter,
H driver, vertical TG
2. IC911 (CCD)
[Structure]
1/2.33 inch 12.53 million picture element CCD
Effective pixels
4040 (H) X 3032 (V)
Pixels in total
4102 (H) X 3057 (V)
Optical black
Horizontal (H) direction: Front 2 pixels, Rear 60 pixels
Vertical (V) direction: Below 19 pixels, Above 6 pixels
Dummy bit number
Horizontal : 26 Vertical :6
33, 36,
21, 20,
16, 38
23, 26, 19,
29, 40,
39, 22
37, 32, 24,
25, 18, 17,
31, 30
2, 14, 34
V1A, V1B, V7A,
V7B, V9A, V9B,
V11A, V11B
V6, V8, V10,
V12,V13A,
V13B, V14
Vertical shift register clock pulse
Vertical shift register clock pulse
GND
-7 V, 0 V, 14.5 V
0 V
Vertical shift register clock pulse
GND
V2, V4,
V15A, V15B,
V15C, V16
-7 V, 0 V
-7 V, 0 V
OS
Power
CCD output
Substrate clock
DC
21.0 Vp-p
DC
Aprox. 7.3 V
14.5 V
OD
9
1
35
OFD
GND
Protection P well
LH1
End horizontal shift register clock pulse
Horizontal shift register clock pulse
H1A, H2A,
H1B, H2B
0 V, 3.3 V
6, 7,
12, 13
4
28, 27
V3, V5
Vertical shift register clock pulse
Substrate control
OFDC1, 2
11, 8
0 V, 3.3 V (When importing all
picture element: 3.3 V)
-7 V, 0 V, 14.5 V
RS
Reset pulse
3
PW
15
DC
3.3 Vp-p
-7 V
0 V, 3.3 V
DC
32 31
ø
V11A
25
26
27
28
29
30
ø
V11B
ø
V12
ø
V3
ø
V5
ø
V8
ø
V7B
33
ø
V2
34
GND
35
OS
ø
V1B
36
øV4
37
11 12
ø
H1B
15
14
13
ø
H2B
GND
PW
10
NC
9
OFD
8
OFDC2
OFDC1
7
ø
H2A
6
ø
H1A
5
NC
øV1A
øV16 38
GND 2
øLH1 4
øRS 3
øV15C
16
øV9B
17
øV9A
18
øV14
22
øV6
23
øV7A
24
øV13B
øV13A 40
OD 1
øV15A
21
øV15B
20
øV10
19
39
Pin 1
6
19
60
2
H
V
Pin 21
