Sanyo VCD-X220, Service Manual

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10
VIDEO-TIMING
CONTROLLER
SUB-CARRIER
GENERATION
SINE-TABLE
SERIAL
TO
PARALLEL
4:2:2 to
4:4:4
INTER-
u-FILTER
v-FILTER
y-FILTER
POLATION
H, V-SYNC
CLK_27
SLEEP
P[7:0]
MODE[3:0]
SVIDEO
MASTER
CBSWAP
COLOR-BURST
&
MODULATION
&
MIXER
CVBS/Y
DAC-
MAPPING
VBIAS VREF_O FSADJUST COMP
DAC
U10 BH4453F (POWER AMP)
U12 CS8553 (TV ENCODE)
IC BLOCK DIAGRAM & DESCRIPTION
Symbol Description
OUT1 Output 1 terminal
Pin
1
Symbol Description Pin
IN1 3 Input 1 terminal
IN2 5 Input 2 terminal
BIAS 6 BIAS terminal
GND 4 Ground
MUTE 2 Mute control terminal (mute = low)
OUT2 7 output 2 terminal
VCC 8 Power supply
Symbol Description
HSYNC
Horizonta sync,output in master mode or input in slave
mode,is synchronized by CLKtoo.
Pin
1
Symbol Description Pin
AGND 3 Analog ground
CVBS/Y 4 Composite output or luminance (with blanking and sync)
NC/VSS 2 No connection in PLCC.Analog ground in TQFP
VSYNC 32
Vertical sync,output in master mode or input in slave mode,
is synchronized by CLK.
P[7:0] 21
YCbCr pixel inputs (TTL compatible).Also,synchronized by
CLK with respect to the incoming HSYNC timing,the higher
index corresponds to a greater significance.
P[7:1] 22
YCbCr pixel inputs (TTL compatible).Also,synchronized by
CLK with respect to the incoming HSYNC timing,the higher
index corresponds to a greater significance.
P[7:2] 23
YCbCr pixel inputs (TTL compatible).Also,synchronized by
CLK with respect to the incoming HSYNC timing,the higher
index corresponds to a greater significance.
P[7:3] 24
YCbCr pixel inputs (TTL compatible).Also,synchronized by
CLK with respect to the incoming HSYNC timing,the higher
index corresponds to a greater significance.
P[7:4] 25
YCbCr pixel inputs (TTL compatible).Also,synchronized by
CLK with respect to the incoming HSYNC timing,the higher
index corresponds to a greater significance.
P[7:5] 26
YCbCr pixel inputs (TTL compatible).Also,synchronized by
CLK with respect to the incoming HSYNC timing,the higher
index corresponds to a greater significance.
P[7:6] 27
YCbCr pixel inputs (TTL compatible).Also,synchronized by
CLK with respect to the incoming HSYNC timing,the higher
index corresponds to a greater significance.
P[7:7] 28
YCbCr pixel inputs (TTL compatible).Also,synchronized by
CLK with respect to the incoming HSYNC timing,the higher
index corresponds to a greater significance.
CLKI 29 Pixel clock,27MHZ,twice the Y sample rate
VDD 31 Digital power
FSADJUST 5
Full scale adjust control pin. A resistor is connected to GND.
Used to control the fullscale output current on analog
outputs.
COMP 6
Compensation pin. A 0.1uF capacitor is used to bypass this
pin to VCC.
VAA 7 Analog power
VREFO 8
Voltage reference output ,typically 1.2V,may be used to
connect to VREFI input
VREFI/VRDAC 9
Voltage reference input ,typically 1.235V. A 0.11uF capacitor
must be used to decouple this input to GND. DAC current
switch reference input ,connect to Vrefo output
VBIAS 10 DAC bias voltage, 0.7 v less than COMP signal
NC 11 No connection in PLCC.Analog ground in TQFP
AGND 12 Analog ground
SLEEP 13 1:power down,reset 0:normal operation
SVIDEO 14
00:00 composite output same signal on both Y,C channels,
01:00 s-video output,Y,C channels
CBSWAP 15 0:Normal Cr,Cb sequence .1:swaps Cr ,Cb sequence
MASTER 16
in 0:slave mode,h and v sync are inputs. 01:00 master mode,
h and v sync are outputs.
MD[3:0] 17 Configuration inputs
MD[3:0] 18 Configuration inputs
MD[3:0] 20 Configuration inputs
MD[3:0] 19 Configuration inputs
GND 30 Digital ground