Sanyo MCD-ZX600F, Service Manual

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IC BLOCK DIAGRAM & DESCRIPTION
IC701 LC587008(4 bit Micro processor)
SCHEMATIC DIAGRAM (RADIO)
This is a basic schematic diagram.
Address
Pin No.
Function Option At reset
V
DD
V SS
24
23
Power supply
V
DD 1
2 V DD
22
21
LCD drive power supply
NON 1/1 bias 1/2 bias 1/3 bias
VDD
VDD1
VDD2
VSS
CUP1
CUP2 3
4
Switching pin used to supply the LCD drive voltage to the VDD1 and
V
2 PINS
DD
Connect a nonpolarized capacitor between CUP1 and CUP2 when
1/2 or 1/3 bias is used
Leave open when a bias other than 1/2 or 1/3 is used.
CFIN Input 25
System clock oscillator connections
Ceramic resonator connection (CF specifications)
RC component connection (RC specifications)
External signal input pin (CFOUT is left open)
This oscillator is stopped by the execution of aSTOP or SLOW
instruction.
CF specifications
RC specifications
External
Specifications
Not used
CFOUT Output
26
XTIN Input 20
XTOUT
Output
19
Referenc e calculation(cl ock specification s,LCD alternain g frequency),
system clock oscillator
32 kHz crystal resonator connection
65 kHz crystal resonator connection
This oscillator is stopped by the execution of aSTOP instruction.
65k specifications
32k specifications
38k specifications
Not used
S1
S2
S3
S4
Input
27
28
29
30
Input-only ports
Input pins used to read data into RAM
Built-in 7.8 ms and 1.95 ms chatter rejection circuits
Built-in pull-up/pull-down
resistors
Note: The 7.8 ms and 1.95 ms times are the times when f 0 is
32.768kHz.
Transistor to hold
a low or high level
Selection of either
pull-up or pull-
down resistor
The pull-up or pull-
down resistor are
on.
These pins go
to the floatin g
sta te when
res et is cleare d. Note:
K1
K2
K3
K4
I/O
31
32
33
34
I/O ports
Input pins used to output read data into RAM
Output pins used to output data from RAM
Built-in 7.8 ms and 1.95 ms input-mode chatter rejection circuits.
The selection of 7.8 or 1.95 ms is linked to that for the S ports.
Note: The 7.8 ms and 1.95 ms times are the times when f 0 is
32.768 kHz.
Transistors to hold
a low or high level
Selection of either
pull-up or pull-
down resistor
The pull-up or pull-
down resistors are
on.
The se pins go
to the floatin g
sta te when
res et is cleare d.
Note:
Input mode
Outpu t latch data is
set high.
M1
M2
M3
M4
I/O
35
36
37
38
I/O ports
Input pins used to read data into RAM
Output pins used to output data from RAM
M4 is used as the external clock input pin in Tm2 mode 3.
*The minimum period for the external clock is twice the cycle time.
Built-in pull-up/pull-down
resistors
The same as K1 to
K4 The same as K1 to
K4
A1
A2
A3
A4
I/O
11
12
13
14
I/O ports
Input pins used to read data into RAM
Output pins used to output data from RAM
Built-in pull-up/pull-down
resistors
The same as K1 to
K4
The same as K1 to
K4
P1
P2
P3
P4
I/O
15
16
17
18
I/O ports
Function: The same as pins A1 to A4
The same as K1 to
K4
The same as K1 to
K4
Pin I/O
QIP-80
Pin No.
Function Option At reset
So1
So2
So3
So4
I/O
7
8
9
10
I/O ports
Function: The same as for pins A1 to A4
Pins So1 to So3 area also used for the serial interface.
Use of these pins inserial mode can be selected under program
cotrol.
Pin functions: SO1:Serial input pin
SO2:Serial output pin
SO3:Serial clock pin
The serial clock pin can be switched between internal and external,
and between rising edge output and falling edge output.
Tra nsis tors to hold
a low or high leve l
Sel ecti on of eith er
pull -up or pull-
dow n resis tors
Inte rna l seria l clock
divi sor selecti on
The same as for K1
to K4
I 1/1
II 1/2
III 1/4
N1
N2
N3
N4
Output
39
40
41
42
Output-only ports
Output pins used to output data from RAM
An alarm signal can be output from pin N4.(Note that this is only
when the N4 output latch is low.)
An alarm signal modulated at 1,2 or 4 kHz can be output.(These
frequencies are output when f 0 is 32.768 kHz.)
A carrier signal can be output from N3.(Note that this is only
when the N3 output latch is low.)
Pins N1 to N4
outpu t circuit type:
Pins N1 to N4
output level
The outp ut level s on
pins N1 to N4 can be
spec ified as an opti on
INT Input 6
Input ports
External interrupt request inputs
Input pins used to read data into RAM
Input detection can be performed on either rising or falling edges.
Built-in pull-up/pull-down
resistors
Tran sistors to hold
a low or high level
Select ion of either
pull-up or pull-
down resist ors
Signal convers ion
(rising/f alling)
selectio n
RES
Input
5
LSI internal reset input
The reset input level can be selected to be either high or low.
Built-in pull-up/pull-down
resistors
Note: The reset pulse must be at least 500us.
*Onl y when the
inpu t resisto r open
spec ificat ion is
selec ted
TST
Input
43
Test input
QIP80 products: Connect to Vss.
Chip products : Leave open or connect to Vss.
Seg1,
Seg2 to
Seg35
Output
44,
45 to
78
LCD panel drive/general-purpose output
LCD panel drive
STATIC
1/2 bias-1/2 duty
1/2 bias-1/3 duty
1/2 bias-1/4 duty
1/3 bias-1/3 duty
1/3 bias-1/4 duty
Types I to V can be specified as mask options.
General-purpose output mode
CMOS
P-channel open drain
N-channel open drain
Types I to III can be specified as mask options.
LCD/g eneral -purpo se output contro l is handle d by the segme nt PLA,
and thus program control is not required.
These pins support output latch control on reset and in standby
states when the oscillators are stopped.
Arbit rary combinat ions of LCD drive and gene ral-p urpos e output s can
be used.
LCD driver/
general-purpose
output switching
LCD drive type
switching
STATIC
1/2 bias-1/2
duty
1/2 bias-1/3
duty
1/2 bias-1/4
duty
1/3 bias-1/3
duty
1/3 bias-1/4
duty
General-purpose
output circuit
switching
CMOS
P-channel
open drain
N-channel
open drain
Outpu t latc h con trol
in standb y mode s
LCD drive
All segment s on
All segments off
*:Determined by
mask options
General purpose
outputs
High level
Low level
Determined by
mask options
Note:When a
comb inatio n of
LCD drive and
gene ral-
purpo se
outpu ts,the
outpu t state is
eithe r:
All lit/hig h level
All off/low level.
These pins go to
the static drive
mode during the
reset period.
Continued from preceding page.
COM1
COM2
Output
2
1
LCD panel drive common polarity outputs
The table below shows how these pins are used depen ding on the duty
used.( values for alterna ting freque ncy reflect a typical specif ication of
32.768 MHz for f 0.)
COM1
Static duty 1/2 duty 1/3 duty 1/4 duty
The static drive
waveform is output
during the reset
period.
*There are cases
where the
alternati ng
frequenc y stops for
the CF,RC and
external clock
specifica tions.
(These cases differ
dependi ng on option
specifica tions.)
COM3
COM4 80
79 COM2
COM3
COM4
Alternation
frequency
32 Hz 32 Hz 32 Hz 42.7 Hz 32 Hz
Note: A cross( X ) indicates that the pin is not used with that duty type.