5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
Bootstrap Configuration:
Please note: this section can not be removed
BOOT_0=0 boot from SPI
BOOT_0=1 boot from UART
Placement on TOP_Layer
A4
BOOT_0
BOOT_0
SYS_POWER_ON
GPIO1
LCD_BL_ON
Amp_RESET
LRCLK
GPIO1
BCLK
ACLK
ADATAIO
LIW_RESETN
VCC3_3
LCD_POWER_ON
P3
LCD_BL_ON
P3
Amp_RESET P14
LVDS_SEL P16
SPI_WEN P4,18
LRCLK P14
BCLK P14
ACLK P14
ADATAIO P14
CP_C P7
LED_G P11
AU_OUT_PDN
P9
LIW_RESETN P18
Title
Size
Document Number
Rev
Date:
Sheet
of
SCHEMATIC,M/B VTV-L55612
COMPAL OPTOELECTRONICS CO., LTD
10
20
Wednesday, March 28, 2012
1A
401C54
Title
Size
Document Number
Rev
Date:
Sheet
of
SCHEMATIC,M/B VTV-L55612
COMPAL OPTOELECTRONICS CO., LTD
10
20
Wednesday, March 28, 2012
1A
401C54
Title
Size
Document Number
Rev
Date:
Sheet
of
SCHEMATIC,M/B VTV-L55612
COMPAL OPTOELECTRONICS CO., LTD
10
20
Wednesday, March 28, 2012
1A
401C54
R48
100/0402
R48
100/0402
R291
0
R291
0
R45
330/0402
R45
330/0402
GPIO I/F
U1K
ZR39748_BGA_A3
GPIO I/F
U1K
ZR39748_BGA_A3
GPIO_P0/SNDBUS[0]/LRCLK
F2
GPIO_P4/SNDBUS[4]/ACLK
F1
GPIO_P5/SNDBUS[5]/ADATAIO
G4
GPIO_P6/SNDBUS[6]
G3
GPIO_P7/SNDBUS[7]
G2
GPIO_P8/SNDBUS[8]
G1
GPIO_P9/SNDBUS[9]
H4
GPIO_P10/SNDBUS[10]
H3
GPIO_P11/SNDBUS[11]/PWM2
H2
GPIO_P12/SNDBUS[12]
H1
GPIO_P14/SNDBUS[14]
J4
GPIO_P1/SNDBUS[1]/BCLK
L3
GPIO_P16/SNDBUS16
N3
R47
330/0402
R47
330/0402
R464
0/0402
R464
0/0402
R63
0/0402
R63
0/0402
R188
0/0402
R188
0/0402
R461
0/0402
R461
0/0402
R46
330/0402
R46
330/0402
R64
0/NC
R64
0/NC
R66
4.7K
R66
4.7K
R65
4.7K
R65
4.7K
