Sanyo FISHER DVD-1500 AU, Service Manual

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IC801 TC90A41AF(DATA PROCESSOR)
No. Name I/O DESCRIPTION No. Name I/O DESCRIPTION
1 DPCK! I
Basic clock input
51
DVR I DMO basic power source
2 DVDD3 -
Digital power source 3.3V
52
DMO O Disc Equaliser output for DVD
3 SVCK1 I
Servo basic clock input
53
RASN O External RAM address selector
4 SVCK0 O Servo basic clock output 54
CASN O External RAM address selector
5 DVSS -
Digital power source 0V
55
MOEN O External RAM output Permission signal
6 DVDD3 -
Digital power source 3.3V
56
MWEN O External RAM read/write select
7 N.C -
N.C
57
DVSS - Digital power source 0V
8 HDWT I
MPU write signal
58
DVDD3 - Digital power source 3.3V
9 HDRD I
MPU read signal
59
MA9 O External RAM address bus
10 HCEN I
MPU chip selector
60
MA8 O External Ram address bus
11 HDO I/O MPU data buss 61
MA7 O External Ram address bus
12 HD! I/O MPU data buss 62
MA6 O External Ram address bus
13 HD2 I/O MPU data buss 63
MA5 O External Ram address bus
14 HD3 I/O MPU data buss 64
MA4 O External Ram address bus
15 HD4 I/O MPU data buss 65
MA3 O External Ram address bus
16 HD5 I/O MPU data buss 66
MA2 O External Ram address bus
17 HD6 I/O MPU data buss 67
MA1 O External Ram address bus
18 HD7 I/O MPU data buss 68
MA0 O External Ram address bus
19 DVSS -
Digital power source 0V
69
DVSS - Digital power source 0V
20 DVDD5 -
Digital power source 5V
70
DVDD5 - Digital power source 5V
21 HINT O MPU interrupt signal 71
MD7 I/O External Ram data bus
22 HAO I
MPU address buss
72
MD6 I/O External Ram data bus
23 HA1 I
MPU address buss
73
MD5 I/O External Ram data bus
24 PLCK I/O Read channel clock input 74
MD4 I/O External Ram data bus
25 ED0 -
N.C
75
MD3 I/O External Ram data bus
26 ED1 -
N.C
76
MD2 I/O External Ram data bus
27 ED2 -
N.C
77
MD1 I/O External Ram data bus
28 ED3 -
N.C
78
MD0 I/O External Ram data bus
29 ED4 -
N.C
79
SD7 O MPEG data output
30 ED5 -
N.C
80
SD6 O MPEG data output
31 ED6 -
N.C
81
SD5 O MPEG data output
32 ED7 -
N.C
82
SD4 O MPEG data output
33 TEST I
Low setting
83
DVSS - Digital power source 0V
34 PD0N O PLL phase error signal output 84
DVDD3 - Digital power source 5V
35 PD0P O PLL phase error signal output 85
SD3 O MPEG data output
36 PLLD O PLL detection result output 86
SD2 O MPEG data output
37 LPFN I
input for PLL loop filter
87
SD1 O MPEG data output
38 LPFO O output for PLL loop filter 88
SD0 O MPEG data output
39 VCOF O VCO filter output 89
SERR O MPEG data Reliability flag
40 SLCO O Basic power output for internal Comparator 90
SBGN O MPEG output sector synchronise signal
41 AVSS -
Analogue power source
91
SENB O MPEG data effective flag
42 AVR O Analogue power source for not PLL stem 92
SDCK O MPEG data Forwarding clock
43 VRC -
Resister division point voltage
93
DVSS - Digital power source
44 PVR O Analogue power source for PLL stem 94
SREQ I MPEG data request flag
45 AVDD -
Analogue power source
95
RSTN I Hard reset input
46 BAIS -
Second basic power 0V
96
DVDD3 - Digital power source
47 RVDD -
Power source 3.3V
97
STDA O Play status monitor data
48 RFIN I
RF signal input
98
STCK O Play status monitor synchronies signal
49 RVSS -
Power source 0V
99
UPWM O General purpose PWM output
50 RVR1 -
First basic power source
100
DVSS - Digital power source 0V
IC BLOCK DIAGRAM & DESCRIPTION
IC911 BA033FP(REGULATOR)
1 3 2
OUT
GND
V
CC