Sanyo DVD-SL38KR, Service Manual

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Z
D
501
3V
6
C
507
100U
F
/10V
C
508
104
C
506
47U
F
/50V
R
507
10K
R
503
0ohm
T
A
206
PL
A
Y
T
A
202
F.
S
H
IP
D
501
1N
4148
D
502
1N
4148
R
508
10K
1
2
3
S
N
501
REM
O
TE 3
8
KHz
C
503
100U
F
/16V
C
502
104
T
A
203
PO
W
E
R
/S
T
B
T
A
201
B.
SHI
P
T
A
205
OP
EN/
C
LOSE
R
502
10 O
H
M
R
504
22K
R
505
OP
EN
C
501
221
F1
1
F1
2
P16
4
P15
5
P14
6
P13
7
P12
8
P11
9
P10
10
P9
11
P8
12
P7
13
P6
14
P5
15
P4
16
P3
17
P2
18
P1
19
NX
20
NX
21
NX
22
NX
23
NX
24
1G
25
2G
26
3G
27
4G
28
5G
29
NP
30
F2
31
F2
32
NX
3
V
F
D
501
HNV-
0
5
S
S
4
8
PC
O
N
DGND VFD
C
E
VFD
C
L
K
V
F
D-
DA
IR A
GND
F2 F1
1 2 3 4 5 6 7 8 9
10 11 12 13 14
C
N
501
CON1
4
R
509
10K
+5
V
C
509
104
D
C
-22V
T
A
204
STOP
R
515
51K
SW
1
1
IR
_IN
2
SDA
3
SCL
4
DO
5
DI
6
VS
S
7
CLK
8
STB
9
K1
10
K2
11
K3
12
K4
13
VDD
14
S1/ K S1
15
S2/ K S2
16
S3/ K S3
17
S4/ K S4
18
S5/ K S5
19
S6/ K S6
20
S7
21
S8
22
S9
23
S1
0
24
S1
1
25
S
12/G
1
1
26
VE
E
27
S
13/G
1
0
28
S
14/G
9
29
S
15/G
8
30
S
16/G
7
31
G6
32
G5
33
G4
34
G3
35
G2
36
G1
37
VDD
38
PW CTL
39
LED3
40
LED2
41
LED1
42
VSS
43
OSC
44
IC
501
T
P
6312
R
517
0 O
H
M
R
519
OP
EN
R
520
OP
EN
R
522
0(O
P
E
N
)
R
526
33
SDA SCL
R
527
100K
+D
5
V
R
528
4.7k
Q
502
OP
EN
R
530
1K
(O
PE
N
)
R
531
1K
(O
PE
N
)
Q
501
2S
C
1623
R
532
100K
R
501
OP
EN
R
506
4.7K
or
P
T
6312
option
SCHEMATIC DIAGRAM (CONTROL)
This is a basic schematic diagram.
Assembly
Note
:
If
using
SST
family
Flash,
not
ins
tall
R138;
If
using
Intel
family
Flash,
not
ins
tall
R137.
During
W
ork
and
Download
mode,
s
hort
p
in2
a
nd
pin3
of
C
N
1
0
4
a
n
d
C
N
1
0
5
;
During
D
ebug
mode,
short
pin1
and
p
in2
o
f
CN10
4
a
n
d
C
N
1
0
5
.
If
u
s
e
+
3
.3
v
,n
o
t
i
nstall
R134
If
u
s
e
+
5
v
,n
o
t
in
stall
R133
D
u
ri
n
g
w
o
rk
in
s
ta
ll
R160/R161
0R
MEMRD
#
RESE
T
#
MEMW
R
#
MEMDA[0..15]
FLASHCS#
MEMAD[0..19]
SSTAD1
9
IntelAD19
SSTAD1
9
MEMDA5 MEMDA12 MEMDA15 MEMDA10 MEMDA11 MEMDA0 MEMDA3 MEMDA1 MEMDA2 MEMDA14 MEMDA4 MEMDA9 MEMDA7 MEMDA8 MEMDA13 MEMDA6
MEMCS1#
RAMCS#
MEMCS0#
MEMW
R
#
MEMRD
#
MEMDA13
MEMAD15
RAMCS#
GND
MEMAD13
GND
MEMDA2
MEMW
R
#
MEMAD7
MEMAD11
MEMDA9
MEMDA11 MEMAD5
MEMDA15
MEMAD4
MEMDA1 MEMAD14
MEMAD16
MEMRD
#
MEMAD8
MEMAD2
MEMDA4 MEMDA14
MEMDA5
MEMDA3
MEMAD12 MEMAD18 MEMDA7
MEMAD10
MEMDA12 MEMAD1
MEMDA0
MEMDA6
MEMDA8
MEMDA10
MEMAD0
MEMAD9
MEMAD6 MEMW
R
#
MEMAD17
MEMAD3
SD3
FLASHCS#
VCC_M
E
M
VCC_M
E
M
VCC_M
E
M
VCC_ME
M
MEMAD5 MEMAD18 MEMAD2 MEMAD4 MEMAD11
MEMAD19
MEMAD0 MEMAD16 MEMAD17 MEMAD14 MEMAD3
IntelAD19
MEMAD9 MEMAD7 MEMAD6 MEMAD10 MEMAD13 MEMAD1 MEMAD12 MEMAD15 MEMAD8
+3.3V
+5V-
ST
B
SD3
SD3
VCC
VCC
+3.3V
+5V-
ST
B
R133
0R/NC
R135
1K
R138
0R/NC
CN105 3 PINS HEADER 1 2 3
U105 AT24C02N-10SI-2.7
1 2 3 4
5 6 7 8
A0 A1 A2
GND
SDA SCL WP VCC
CN104 3 PINS HEADER 1 2 3
R132 4.7k
U104 SST39VF800
/T
S
O
P
18 19 20 21 22 23 24 25
27 29 37 44
48
1 2 3 4 5 6 7 8
31 33 35 38 40 42
17
46 30 32 34 36 39 41 43 45 15
47 26 28 11 12 16
9
13 14
A7 A6 A5 A4 A3 A2 A1 A0
GND
DQ0
VCC
DQ7
A16 A15 A14 A13 A12 A11 A10 A9 A8
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6
A17
GND
DQ8 DQ9
DQ10 DQ11 DQ12 DQ13 DQ14
DQ15/A-1
RY/BY
BYTE CE OE WE RST A18 A19
I-Vpp
I-WP#
R137
0R/NC
C147 0.1uF
CN103
DEBUG SRAM I/F
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2 4 6 8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 42 40
41
C148
0.1uF
R136 1K
R161
NM/0R
R160
NM/0R
R134
0R/NC
GND
MEMDA[0..15] MEMAD[0..19]
SDA
SCL
+3.3V
RESE
T
#
MEMCS0# MEMCS1#
RD- WR-
SD3 VCC +5V-
ST
B
This is a basic schematic diagram.
SCHEMATIC DIAGRAM (MEMORY)