5
CIRCUIT OPERATIONAL DESCRIPTION
DQ0
DQ15
UDQM
LDQM
CLK
CKE
A10
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #2
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #0
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #3
DATA CONTROL
CIRCUIT
DQ
BUFFER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #1
NOTE:
The cell array configuration is 4096 * 256 * 16
R
E
D
O
C
E
D
W
O
R
R
E
D
O
C
E
D
W
O
R
R
E
D
O
C
E
D
W
O
R
R
E
D
O
C
E
D
W
O
R
A0
A9
BS0
BS1
CS
RAS
CAS
WE
A11
SDROM PT48046TG-70 Block Diagram
Sm(SANYO_DVD-DX500)051220.indd 15
2005-12-29 8:58:46
