Sanyo DP46142, Service Manual

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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
0: Watchdog Timer Enabled
1: Watchdog Timer Disabled
Ask Chris change the ball
name to BOOT_OPT, WDT_EN_N,
do not confuse customer
0: MIPS BOOTSTRAP
1: EEPROM BOOTSTRAP
VOL+ MENU INPUT/EXIT CH+ VOL- CH-
POWER
2010/12/ 20 IR pin define changed
Adding option resistor
to save LED_G
2011/11/01
Preventing the flash on
LED 2011/11/01
Connecting to ground for
ADC8 calibration.
2011/11/09
Reserving for Panel PWM
150Hz. 2011/11/01
FP_KEY_IN1
IRR
VGA_SDA
VGA_SCL
RESETN
UART0_TX
UART0_RX
FP_KEY_IN2
WDT_EN_N_LED2
VGA_VSYNC_0
FP_GPIO
TVM_PWR_ON2
TVM_BOOT_LED1
WDT_EN_N_LED2 TVM_BOOT_LED1
UART0_TX
UART0_RX LED_R
FP_KEY_IN1 FP_KEY_IN2
FP_GPIO
Light_Sensor
LED_R
IRR
LED_G
Light_Sensor
VCC1_1_STB
VCC3_3_STB
VCC3_3_STB
VCC3_3_STB
VCC3_3_STB
VCC3_3_STB
VCC3_3_STB VCC3_3_STB
GND
GND
GND
VCC5_0_STB
VGA_SCL P7
VGA_SDA P7
TVM_PWR_ON2 P3
VGA_VSYNC_0 P7
RESETN P4
UART0_RX P7
UART0_TX P7
PG_MUTE P3,9
HDMI0_5V P5
HDMI0_HPD P5
HDMI1_5V P5
HDMI1_HPD P5
HDMI0_DDC_SCL P5
HDMI0_DDC_SDA P5
HDMI_CEC_IN P5
HDMI1_DDC_SDA P5
HDMI1_DDC_SCL P5
BL_C P3
TVM_PWR_ON1 P3
LED_G P10
HDMI2_HPD P5
HDMI2_5V P5
HDMI2_DDC_SDA P5
HDMI2_DDC_SCL P5
BL_ERR P3
PWM2 P3
FP_GPIO P4
Title
Size Document Number Rev
Date: Sheet of
SCHEMATIC,M/B VTV-L42612
COMPAL OPTOELECTRONICS CO., LTD
11 15 Tuesday, January 17, 2012
1
XXXXXX
Title
Size Document Number Rev
Date: Sheet of
SCHEMATIC,M/B VTV-L42612
COMPAL OPTOELECTRONICS CO., LTD
11 15 Tuesday, January 17, 2012
1
XXXXXX
Title
Size Document Number Rev
Date: Sheet of
SCHEMATIC,M/B VTV-L42612
COMPAL OPTOELECTRONICS CO., LTD
11 15 Tuesday, January 17, 2012
1
XXXXXX
R151
3.3K/1%
R151
3.3K/1%
C78
2.2uF/16V/0805
C78
2.2uF/16V/0805
TP8 TP8
C
387
100pF/
25V
/0402
C
387
100pF/
25V
/0402
R148
3.9K/1%/0402 R148
3.9K/1%/0402
GND
S3
SW PUSH/4P/90D/1.3MM
GND
S3
SW PUSH/4P/90D/1.3MM
2
4 3
1
L9
KLB0402E601SA L9
KLB0402E601SA
R145 0/NC R145 0/NC
R152
1.2K/1%
R152
1.2K/1%
GND
S6
SW PUSH/4P/90D/1.3MM
GND
S6
SW PUSH/4P/90D/1.3MM
2
4 3
1
R178
0/NC
R178
0/NC
C
374
100pF/
25V
/0402/
N
C
C
374
100pF/
25V
/0402/
N
C
R69
10K/1%/0402 R69
10K/1%/0402
D
17
A
Z5125/
N
C
D
17
A
Z5125/
N
C
R74
18K/1%/0402 R74
18K/1%/0402
1
2
C
385
100pF/
25V
/0402/
N
C
C
385
100pF/
25V
/0402/
N
C
L10
KLB0402E601SA L10
KLB0402E601SA
R103 10K/1%/NC R103 10K/1%/NC
1 2
R67 4.7K/0402 R67 4.7K/0402
D8
A
Z5125/
N
C
D8
A
Z5125/
N
C
L8
KLB0402E601SA L8
KLB0402E601SA
D
16
A
Z5125/
N
C
D
16
A
Z5125/
N
C
L64
PBY160808T-121Y-N 2.5A L64
PBY160808T-121Y-N 2.5A
1
2
R106
39K/1%/NC
R106
39K/1%/NC
1
2
C77
10nF/16V/0402
C77
10nF/16V/0402
GND
S2
SW PUSH/4P/90D/1.3MM
GND
S2
SW PUSH/4P/90D/1.3MM
2
4 3
1
R465 0/0402 R465 0/0402
C80
1uF/6.3V/0402 C80
1uF/6.3V/0402 R73
10K/1%/0402 R73
10K/1%/0402
R144
4.7K/NC
R144
4.7K/NC
R54
0/1206
R54
0/1206
1
2
R76
10K/1%/0402
R76
10K/1%/0402
R68 4.7K/0402/NC R68 4.7K/0402/NC
R154
3.3K/1%
R154
3.3K/1% GND
S1
SW PUSH/4P/90D/1.3MM
GND
S1
SW PUSH/4P/90D/1.3MM
2
4
3
1
R70 0/0402 R70 0/0402
R156
3.9K/1%/0402 R156
3.9K/1%/0402
R177 0/NC R177 0/NC
C82
1uF/6.3V/0402 C82
1uF/6.3V/0402
C
373
100pF/
25V
/0402
C
373
100pF/
25V
/0402
R153
10K/1%/0402
R153
10K/1%/0402
GND
S7
SW PUSH/4P/90D/1.3MM
GND
S7
SW PUSH/4P/90D/1.3MM
2
4 3
1
R127
4.7K
R127
4.7K
GND
S4
SW PUSH/4P/90D/1.3MM
GND
S4
SW PUSH/4P/90D/1.3MM
2
4 3
1
R149
3.9K/1%/0402 R149
3.9K/1%/0402
C79
10nF/16V/0402
C79
10nF/16V/0402
C
388
100pF/
25V
/0402
C
388
100pF/
25V
/0402
R72 0 R72 0
R150
10K/1%/0402
R150
10K/1%/0402
C372
4.7uF/6.3V/NC
C372
4.7uF/6.3V/NC
1
2
MCU I/F
U1L
ZR39748_BGA_A3
MCU I/F
U1L
ZR39748_BGA_A3
POWER_CTL1/TV_DEBUG[2]
D5
POWER_CTL2/TV_DEBUG[3]
C5
TVCPU_PWM0
D7
RESET_N
E1
TVCPU_I2C1C/UART0TX
A6
TVCPU_I2C1D/UART0RX
C7
HDMI0_SCL
E4
HDMI0_SDA
E3
GPIO_TV_P6/HDMI2_5VSENSE
C2
GPIO_TV_P7/HDMI2_HPD
B1
HDMI0_5VSENSE
D1
HDMI0_HPD
E2
VGA_SCL/TV_DEBUG[7]
B3
VGA_SDA/TV_DEBUG[8]
A3
ADC8_RBIAS
F6
GPIO_TV_P0/HDMI1_SCL
D4
GPIO_TV_P1/HDMI1_SDA
D3
GPIO_TV_P2/HDMI1_5VSENSE
C1
GPIO_TV_P3/HDMI1_HPD
D2
GPIO_TV_P4/HDMI2_SCL
C4
GPIO_TV_P5/HDMI2_SDA
C3
IOVDD_STBY1
G6
COREVDD_STBY
G7
CLK25M_VDD
F7
ADC8_IN0
C8
ADC8_IN1
D8
ADC8_IN2
C9
ADC8_IN3
D9
IRR
A2
T0/TV_DEBUG[7]
B4
T1/TV_DEBUG[8]
B6
INT0_N/TV_DEBUG[4]
C6
INT1_N/TV_DEBUG[5]
D6
INT2/TV_DEBUG[6]/AFE_VSYNC_IN
B2
WDT_EN_N
B5
BOOT_OPT
A5
HDMI_CEC
A1
IOVDD_STBY2
H6
CLKIN_RTC
A7
CLKOUT_RTC
B7
ADC8_IN6
D13
CN4
JWT A2001WR2-6P CN4
JWT A2001WR2-6P
1
2
3
4
5
6
R155
1.2K/1%
R155
1.2K/1%
R458 0/0402 R458 0/0402
D
13
A
Z5125/
N
C
D
13
A
Z5125/
N
C
C81
10nF/16V/0402
C81
10nF/16V/0402
R
75
30K
/1%
/0402
R
75
30K
/1%
/0402
1
2
R71 10K/1%/0402 R71 10K/1%/0402
C83
22pF/50V/0402
C83
22pF/50V/0402
GND
S5
SW PUSH/4P/90D/1.3MM
GND
S5
SW PUSH/4P/90D/1.3MM
2
4 3
1