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IC BLOCK DIAGRAM & DESCRIPTION
IC818 SST39VF800A-70(Flash)
CONTROL LOGIC
CE#
OE#
WE#
WP#
RY/BY#
RESET#
BYTE#
A18-A0,A-1
ADDRESS BUFFER
&
LATCH CIRCUIT
CHARGE PUMP
&
VOLTAGE
REFERENCE
CIRCUIT
IN/OUTPUT BUFFER
&
DATA LATCH
DQ15-DQ0
128Kx16
or
256Kx8
FLUSH
BANK2
384Kx16
or
788Kx8
FLUSH
BANK1
LOW DECODER
COLUMN DECODER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
AD
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
Symbols
A18,A17
A16-A0,A-1
A18-A15
A18-A10
DQ15-DQ0
CE#
OE#
WE#
BYTE#
RY/BY#
WP#
RESET#
VDD
VSS
Pin Name
Bank Selective Address
Flush Bank Address
Flush Bank Block Address
Flush Bank Sector Sddress
Data Input/Output
Chip Enable
Output Enable
Write Enable
Bait Pin
Ladey/Beje Output
Write Protect
Reset
Power Supply
Ground
Functions
Selects bank 1 when "L" and bank 2.
Sapply address for flush bank.
Select flush bank for erease.
Select flush bank sector for erease.
To activate the flush bank when CE# is "L".
To activate the data output buffer .
To control the write, erease and program.
Bait mode when "L" and word mode when "H".
Output "L" when write and ezcept "H".
To activate hardware write protect when "L".
To activate hardware reset when "L".
2.7V~3.6V supply.
To output data during read cycle and receive input data during write
cycles. Data is internaliy latched during a writecycle. The output are
high inpedance when OE#,CE# is "H".
