- 13 -
9
3
10
1
12
18
23
14
17
19
24
20
13
15
16
8
11
2
7
6
4
22
21
5
V
SSP
1
V
SSP
2
mute
mute
INPUT
STAGE
PWM
MODULATOR
CONTROL
AND
HANDSHAKE
DRIVER
HIGH
DRIVER
LOW
RELEASE1
SWITCH1
ENABLE1
INPUT
STAGE
PWM
MODULATOR
CONTROL
AND
HANDSHAKE
DRIVER
LOW
DRIVER
HIGH
RELEASE2
SWITCH2
ENABLE2
MODE
OSCILLATOR
MANAGER
TEMPERATURE SENSOR
CURRENT PROTECTION
STABI
V
SSP
1
V
SSA
1
V
SSA
2
V
SSD
HW
V
SSP
2
BOOT1
BOOT2
OUT1
OUT2
IN1-
IN1+
SGND1
SGND2
IN2+
IN2-
OSC
MODE
IC BLOCK DIAGRAM & DESCRIPTION
IC597 TDA8921TH (2x50 Class-D Power Amplifier)
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
V
DDA
2
V
DDA
1
V
DDP
1
V
DDP
2
PROT
STABI
V
SSP
1
V
SSA
1
V
SSA
2
V
SSD
HW
V
SSP
2
BOOT1
BOOT2
OUT1
OUT2
IN1-
IN1+
SGND1
SGND2
IN2+
IN2-
OSC
MODE
TDA8921TH
VSSA2
SGND2
VDDA2
IN2-
IN2+
MODE
OSC
IN1+
IN1-
VDDA1
SGND1
VSSA1
PROT
VDDP1
BOOT1
OUT1
VSSP1
STABI
HW
VSSP2
OUT2
BOOT2
VDDP2
VSSD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
negative analog supply voltage for channel 2
signal ground for channel 2
positive analog supply voltage for channel 2
negative audio channel 2 input
positive audio channel 2 input
mode select input : (standby, mute or operationg)
oscillator frequency adjustment or tracking input
positive audio channel 1 input
negative audio channel 1 input
positive analog supply voltage for channel 1
signal ground for channel 1
negative analog supply voltage for channel 1
time constant capacitor for protection delay
positive power supply voltage for channel 1
bootstrap capacitor for channel 1
channel 1 PWM output
negative power supply voltage for channel 1
decouping capacitor of internal stabilizer for logic supply
handle wafer ; must be connected to VSSD
negative power supply voltage for channel 2
channel 2 PWM output
bootstrap capacitor for channel 2
positive power supply voltage for channel 2
negative digital supply voltage
SYMBOL PIN DESCRIPTION
Description
LED Output Pin
Oscillator Input Pin
A resistor is connected to this pin to
determinc the oscillation frequency
Data Output Pin (N-Channel, Open-Drain)
This pin outputs scrial data at the falling
edge of the shift clock (starting from the lower bit)
Data Input Pin
This pin inputs serial data at the rising edge
of the shift clock (starting from the lower bit)
Clock Input Pin
This pin reads serial data at the rising edge
and outputs data at the falling edge.
Pin No.
1 to 4
5
6
7
8
I/O
O
I
O
I
I
Pin Name
LED1 to LED4
OSC
DOUT
DIN
(Schmitt Trigger)
CLK
(Schmitt Trigger)
This pin reads serial data at the rising cdge
and outputs data at the falling cdge.
Serial Interface Strobe Pin
The data input after the STB has fallen is
processed as a command.
When this pin "HIGH",CLK is ignored,
Key Data Input Pins
The data inputted to these pins are fatched
at the end of the display cycle.
Logic Ground Pin
Logic Power Supply
High-Voltage Segment Output Pins
Also acts as the Key Source
Pull-Down Level
High Voltage Segment/Grid Output Pins
High-Voltage Grid Output Pins
8
9
10, 11
12, 44
13, 43
14 to 29
30
31 to 38
39 to 42
I
I
I
-
-
O
-
O
O
CLK
(Schmitt Trigger)
STB
(Schmitt Trigger)
K1 to K2
VSS
VDD
SG1/KS1 to SG16/KS16
VEE
SG17/GR12 to SG24/GR5
GR4 to GR1
Description
Pin No.
I/O
Pin Name
IC601 PT6315 (VFD Driver / Controller IC)
