
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IC BLOCK DIAGRAM & DESCRIPTION
CONTROL LOGIC
CE#
OE#
WE#
A18-A0
ADDRESS BUFFER
&
LATCH CIRCUIT
CHARGE PUMP
&
VOLTAGE
REFERENCE
CIRCUIT
IN/OUTPUT BUFFER
&
DATA LATCH
DQ15.DQ0
256Kx16
FLUSH
BANK1
256Kx16
FLUSH
BANK2
LOW DECODER
COLUMN DECODER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
NC
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
A0
A1
A15
A14
A13
A12
A11
A10
A9
A8
WE#
NC
NC
NC
NC
NC
NC
A18
A17
A78
A6
A5
A4
A3
A2
ACE#
STM.
NAME
FUNCTION
A18
A17-A0
A17-A15
A17-A10
DQ15-DQ0
CE#
OE#
WE#
VDD
GND
NC
Bank Selective Address
Flush Bank Address
Flush Bank Block Address
Flush Bank Sector Sddress
Data Input/Output
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
Selects bank 1 when "L" and bank 2 when "H".
Sapply address for flush bank.
Select flush bank for erease.
Select flush bank sector for erease.
To activate the flush bank when CE# is low.
To activate the data output buffer .
To control the write, erease and program.
207V~3.6V supply.
Not connect to internal chip.
To output data during read cycle and receive input data during write
cycles. Data is internaliy latched during a writecycle. The output are
high inpedance when OE#,CE# is high.
IC118 LE28DW8102T-90-MPB(FLASH MEMORY)
IC475 LA4663)POWER IC)
5
7
8
14
13
12
9
10
11
6
2
3
4
1
+OUT2
-OUT2
PWR
GND2
+OUT1
-OUT1
PWR
GND1
Rlpple Filter/
Starting Time
IN2
PRE
GND
IN1
SIGNAL
MUTE
STAND BY
Vcc1 Vcc2
Summary of Contents for DC-DAV821
Page 22: ... 27 MPEG AND FRONT END P W BOARD CHECK WAVEFORM 7 8 10 DVD CD 12 11 ...
Page 23: ... 28 MPEG AND FRONT END P W BOARD CHECK WAVEFORM 13 14 15 16 17 18 Surround ON ...
Page 25: ... 30 MPEG AND FRONT END P W BOARD CHECK WAVEFORM 52 53 54 55 56 57 ...
Page 26: ... 31 MPEG AND FRONT END P W BOARD CHECK WAVEFORM 58 59 60 61 62 63 ...
Page 27: ... 32 MPEG AND FRONT END P W BOARD CHECK WAVEFORM 64 65 66 67 68 69 ...
Page 28: ... 33 MPEG AND FRONT END P W BOARD CHECK WAVEFORM 70 71 72 73 78 79 S VIDEO COMPOSITE VIDEO ...
Page 67: ... 65 SCHEMATIC DIAGRAM MPEG This is a basic schematic diagram ...
Page 68: ... 66 WIRING DIAGRAM MPEG A SIDE ...
Page 69: ... 67 WIRING DIAGRAM MPEG B SIDE ...
Page 71: ... 69 WIRING DIAGRAM POWER AMP for SS ...
Page 72: ... 70 WIRING DIAGRAM PRE AMP for SS ...
Page 74: ... 72 WIRING DIAGRAM POWER AMP for KR ...
Page 75: ... 73 WIRING DIAGRAM PRE AMP for KR ...
Page 76: ... 74 SCHEMATIC DIAGRAM TUNER This is a basic schematic diagram ...
Page 77: ... 75 WIRING DIAGRAM TUNER ...
Page 78: ... 76 SCHEMATIC DIAGRAM FRONT This is a basic schematic diagram ...
Page 79: ... 78 SCHEMATIC DIAGRAM DVD This is a basic schematic diagram ...
Page 80: ... 79 WIRING DIAGRAM DVD A SIDE WIRING DIAGRAM DVD B SIDE ...