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-8-
F2KT/KV
SIGNAL
CLAMPING
LINE
MEMORY
SAMPLE-
AND-
HOLD
LP
LP
DIVIDER
BY 2
6 MHz
CCO
LP
SAMPLE-
AND-
HOLD
LINE
MEMORY
DIVIDER
BY 192
FREQUENCY
PHASE
DETECTOR
SIGNAL
CLAMPING
SANDCASTLE
DETECTOR
16
14
9
5
10
1
3
4,8
12
11
GND1
Vp2
GND2
2
6
13
15
7
i.c.
n.c.
n.c.
n.c.
n.c.
±
(B-Y)
±
(R-Y)
TDA4661
addition
stages
output
buffers
colour-difference
output sugnals
±
(R-Y)
±
(B-Y)
colour-difference
input signals
pre-amplifiers
analogue supply
digital supply
sandcstle
pulse input
Vp1
3MHz shifting clock
TDA4661 <1H DELAY LINE>
AGC
RAMP
PULSE
SHAPER
TRIGGER
PULSE INFERFACE
∫
CORRECT
LINEARUTY
CORRECTION
S-C CORR.
PALABOLA
CORR.
ETH
CORR.
ETH
CORR.
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TA8859AP
ETH IN
VERT F/B
GND
EW F/B
Vcc
ETH DRIVE
VERT. DRIVE
SCL
SDA
TRIG IN
TA8859AP <DEFLECTION CORRECTION>
GND
VERTICAL
DRIVE
VERTICAL
OUTPUT
V-OUTPUT
VCC
6
4
3
1
5
LA7833
THERMAL
PROTECTION
PUMP UP
7
2
V-DRIVE PLS
INPUT
LA7833 <VERTICAL OUTPUT>