
3.5"-SBC-WLU - User Guide, Rev. 1.8
// 55
Pin
Signal
Description
Note
27
GND
Ground
28
-
29
PERn1
PCIe Lane 1 receiver pair (-)
30
-
31
PERp1
PCIe Lane 1 receiver pair (+)
32
-
33
GND
Ground
34
-
35
PETn1
PCIe Lane 1 transmitter pair (-)
36
-
37
PETp1
PCIe Lane 1 transmitter pair (+)
38
DEVSLP
Device sleep
39
GND
Ground
40
-
41
PERn0 /
PCIe Lane 0 receiver pair (-) / SATA receiver pair (+)
42
-
43
PERp0 / SATA_B-
PCIe Lane 0 receiver pair (+) / SATA receiver pair (-)
44
-
45
GND
Ground
46
-
47
PETn0 / SATA_A-
PCIe Lane 0 transmitter pair (-) / SATA transmitter pair (-)
48
-
49
PETp0 /
PCIe Lane 0 transmitter pair (+) / SATA transmitter pair (+)
50
PERST# / -
PCIe reset
51
GND
Ground
52
CLKREQ# / -
Reference clock request signal
53
REFCLKn
PCIe reference clock pair (-)
54
PEWAKE# / -
PCIe wake
55
REFCLKp
PCIe reference clock pair (+)
56
-
57
GND
Ground
58
-
59
Key
60
Key
61
Key
62
Key
63
Key
64
Key
65
Key
66
Key
67
-
68
SUSCLK
32.768 kHz clock supply input