
3.5"-SBC-VR1000 - User Guide, Rev. 1.7
// 52
Pin
Signal
Description
Note
27
GND
Ground
28
NC
No connection
29
M2M_RXN1
PCIe Lane 1 receiver pair (-)
30
NC
No connection
31
M2M_RXP1
PCIe Lane 1 receiver pair (+)
32
NC
No connection
33
GND
Ground
34
NC
No connection
35
M2M_TXN1
PCIe Lane 1 transmitter pair (-)
36
NC
No connection
37
M2M_TXP1
PCIe Lane 1 transmitter pair (+)
38
DEVSLP
Device sleep
39
GND
Ground
40
NC
No connection
41
PCIE_RXN
PCIe Lane 0 receiver pair (-)
42
NC
No connection
43
PCIE_RXP
PCIe Lane 0 receiver pair (+)
44
NC
No connection
45
GND
Ground
46
NC
No connection
47
PCIE_TXN
PCIe Lane 0 transmitter pair (-)
48
NC
No connection
49
PCIE_TXP
PCIe Lane 0 transmitter pair (+)
50
PERST#
PCIe reset
51
GND
Ground
52
CLKREQ#
Reference clock request signal
53
REFCLKn
PCIe reference clock pair (-)
54
PEWAKE#
PCIe wake
55
REFCLKp
PCIe reference clock pair (+)
56
NC
No connection
57
GND
Ground
58
NC
No connection
59
Key
60
Key
61
Key
62
Key
63
Key
64
Key
65
Key
66
Key
67
NC
No connection
68
NC
No connection