AT INTERFACE and ATA COMMANDS
6-
46 WA31273A / WA32543A / WA33203A / WA3216A / WA31083A / WA32162A
6-6-4 DMA Data Transfer Commands (optional)
This class comprises:
•
Read DMA (C8h)
•
Write DMA (C9h)
Data transfers using DMA commands differ in two ways from PIO transfers:
•
data transfers are performed using the slave-DMA channel
•
no intermediate sector interrupts are issued on multi-sector commands.
Initiation of the DMA transfer commands is identical to the Read Sector or Write Sector
commands except that the host initializes the slave-DMA channel prior to issuing the
command.
The interrupt handler for DMA transfers is different in that:
•
no intermediate sector interrupts are issued on multi-sector commands
•
the host resets the DMA channel prior to reading status from the drive.
The DMA protocol allows high performance multi-tasking operating system to
eliminate processor overhead associated with PIO transfers.
a) Command phase
1) Host initializes the slave-DMA channel.
2) Host updates the Command Block Registers.
3) Host writes command code to the Command Register.
b) Data phase - the register contents are not valid during a DMA data Phase.
1) The slave-DMA channel qualifies data transfers to and from the drive with DMARQ.
c) Status phase
1) Drive generates the interrupt to the host.
2) Host resets the slave-DMA channel.
3) Host reads the Status Register and Error Register.