Samsung
Confidential
19) Clock Running
DRAW
VRMPWRGD
DDR2 POWER
17) VRM3_CPU_PWRGD
MAX 1999
ONTOP B’D
10-1) CHP3_SLPS4*/S5*
SC452
ISL6227
RSTIN#
CPURST#
PROPRIETARY INFORMATION THAT IS
POWER S/W
CLOCK
PART NO.
Rev. 0.1
DATE
REV
SAMSUNG
A
11) KBC3_PWRON
RESET#
CK505
6) KBC3_SUSPWRON
7) P3.3V_AUX
CLPWROK
THIS DOCUMENT CONTAINS CONFIDENTIAL
DEV. STEP
1-1) PRTC_BAT
MICOM
PWRGOOD
Discrete
12) P5V
5) KBC3_CHKPWRSW*
9) KBC3_RSMRST*
10-2) CHP3_SLPS3*
22) PLT3_RST*
4) KBC3_RST*
EN
EN
SLP_S4#
* KBC3_LANRST# assert 100ms after LAN Power stable
3
4
APPROVAL
RST Circuit
1-2) CHP3_RTCRST*
22) CL3_RST*
14) P1.2V
P1.5V
SC470
SC486
7) P1.05V_CL
SLP_S3#
ALWAYS
2) VDC
10ms Delay
CK_PWRGD
CL_RST#
PCIRST#
SAMSUNG PROPRIETARY
2
CLPWROK
7) P1.5V_AUX
D
3) MICOM_P3V
B
S4_STATE#
SLP_M#
LAST EDIT
Battery
CPU
20) KBC3_PWRGDMCH
7) P5V_AUX
12) P0.9V
GFX_CORE
12) P1.25V
12) P1.05V
LAN100_SLP
PRTC
1
RES#
PAGE
3
POWER SEQUENCE
RSMRST#
16) VCC_CORE
PWROK
SLP_S5#
PRTC
RTC
PLTRST#
INTVRMEN
POWER
20) KBC3_PWRGD
CHECK
ELECTRONICS
7) P1.8V_AUX
C
4
SUS_STAT#
GMCH
7) P1.05V_AUX
2
SAMSUNG ELECTRONICS CO’S PROPERTY.
EXCEPT AS AUTHORIZED BY SAMSUNG.
COM-22C-015(1996.6.5) REV. 3
ICH8-M
PWROK
CPUPWRGD
16) VCC_CORE
Switched
Power
CL_RST#
23) CPU1_CPURST*
P5V_AUX & P3V_AUX
8) SUSPWRGD
SC486
99ms Delay
7) P1.5V_CL
P1.25V / P1.05V
B
7) P3.3V_AUX
7) P5V_AUX
12) P3.3V
14) P1.8V
3) P12V_ALWS
Switched
Power
12) GFX_CORE
12) P1.5V
13) VCCP_PWRGD
15) KBC3_VRON
7) P1.05V_LAN
1
C
TITLE
A
MODULE CODE
18) CLK3_PWRGD*
21) CPU1_PWRGDCPU
12) P2.5V
ZHOU JUN
GUO LEI
KEVIN LEE
3/9/2007
MP
1.0
March 9, 2007 12:03:21 PM
BA41-00727/8A
4
53
TORINO 2
MAIN
POWER SEQUENCE
D:/users/mentor/Torino2/SR/T2_SR_0309
OF
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
GFX.
D
RTCRST#
3) P5V_ALWS
IMVP6
