Samsung SPINPOINT V40 Series Product Manual Download Page 109

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DISK DRIVE OPERATION

SpinPoint V40

Product Manual

101

6.7.4.6

Host terminating an Ultra DMA data in burst

The values for the timings for each of the Ultra DMA modes are contained in 6.7.4.2.

DVH

CRC

DMARQ

(device)

DMACK-

(host)

STOP

(host)

HDMARDY-

(host)

DSTROBE

(device)

DD(15:0)

DA0, DA1, DA2,

CS0-, CS1-

ACK

MLI

IORDYZ

ACK

ZAH

MLI

DVS

RFS

NOTE

−

The definitions for the STOP, HDMARDY and DSTROBE signal lines are no longer in

effect after DMARQ and DMACK are negated.

Figure 6-8

Host terminating an Ultra DMA data in burst

Summary of Contents for SPINPOINT V40 Series

Page 1: ...Product Manual 3 5 Hard Disk Drives SPINPOINT V40 JULY 7 2001 Rev 1 0 ...

Page 2: ...ii SpinPoint V40 Product Manual ...

Page 3: ...ation 16 4 4 CABLE CONNECTORS 16 4 4 1 DC Power Connector 16 4 4 2 AT Bus Interface Connector 16 4 5 JUMPER BLOCK CONFIGURATIONS 18 4 6 DRIVE INSTALLATION 20 4 7 SYSTEM STARTUP PROCEDURE 21 4 7 1 Drive Installation to Access the Full Capacity Using 32GB Clip 22 CHAPTER 5 DISK DRIVE OPERATION 23 5 1 HEAD DISK ASSEMBLY HDA 23 5 1 1 Base Casting Assembly 23 5 1 2 DC Spindle Motor Assembly 23 5 1 3 Di...

Page 4: ... Drive I O Read 40 6 2 3 7 DIOW Drive I O Write 40 6 2 3 8 DMACK DMA Acknowledge 41 6 2 3 9 DMARQ DMA Request 41 6 2 3 10 INTRQ Drive Interrupt 41 6 2 3 11 IOCS16 Drive 16 bit I O 41 6 2 3 12 IORDY I O Channel Ready 42 6 2 3 13 PDIAG Passed Diagnostics 42 6 2 3 14 RESET Drive Reset 42 6 3 LOGICAL INTERFACE 46 6 3 1 General 46 6 3 1 1 Bit Conventions 46 6 3 1 2 Environment 46 6 3 2 I O Register Add...

Page 5: ... 4 24 5 Smart read data D0h 73 6 4 24 6 SMART read log sector D5h 75 6 4 24 7 SMART return status DAh 75 6 4 24 8 SMART save attribution value D3h 75 6 4 24 9 SMART write log sector D6h 75 6 4 25 Standby 96h E2h 76 6 4 26 Standby Immediate 94h E0h 76 6 4 27 Write Buffer E8h 76 6 4 28 Write Long 32h with retry 33h without retry 76 6 4 29 Write DMA CAh 76 6 4 30 Write Multiple Command C5h 77 6 4 31 ...

Page 6: ...Table 3 4 Performance Specifications 8 Table 3 5 Power Requirements 9 Table 3 6 Environmental Specifications 10 Table 3 6 Environmental Specifications continued 11 Table 3 7 Reliability Specifications 11 Table 4 1 Power Connector Pin Assignment 16 Table 4 2 Logical Drive Parameters 21 Table 6 1 AT Bus Interface Signals 43 Table 6 2 Interface Signals Description 45 Table 6 3 I O Port Function Selec...

Page 7: ...7 Figure 5 3 Read Write 88C5200 33 Figure 6 1 Register transfer to from device 90 Figure 6 2 PIO data transfer to from device 92 Figure 6 3 Multiword DMA data transfer 94 Figure 6 4 Initiating an Ultra DMA data in burst 96 Figure 6 5 Sustained Ultra DMA data in burst 98 Figure 6 6 Host pausing an Ultra DMA data in burst 99 Figure 6 7 Device terminating an Ultra DMA data in burst 100 Figure 6 8 Hos...

Page 8: ......

Page 9: ...e helpful to the reader 1 1 User Definition The SpinPoint V40 product manual is intended for the following readers Original Equipment Manufacturers OEMs Distributors 1 2 Manual Organization This manual provides information about installation principles of operation and interface command implementation It is organized into the following chapters Chapter 1 SCOPE Chapter 2 DESCRIPTION Chapter 3 SPECI...

Page 10: ... second Mbytes s Megabytes per second MHz Megahertz Mil Millinches Ms Milliseconds MV Millivolts Ns Nanoseconds Rpm Rotations per minute Tpi Tracks per inch V Volts W Watts This manual uses the following conventions Computer Message Computer message refers to items you type at the computer keyboard These items are listed in all capitals in Courier New font For example FORMAT C S Commands and Messa...

Page 11: ...n An active low signal name is listed with a dash character following the signal name For example IOR Notes Notes are used after tables to provide you with supplementary information Host In general the system in which the drive resides is referred to as the host 1 4 Reference For additional information about the AT interface refer to ATA 2 AT Attachment 2 Revision 3 January 1995 ATA 3 Attachment 3...

Page 12: ...3 5 inch form factor The interface connectors are the standard 40 pin for AT Interface and 4 pin for DC power supplies The SpinPoint V40 incorporates Advanced GMR Giant Magneto Resistive head and Noise Predictive PRML Partial Response Maximum Likelihood signal processing technologies These advanced technologies allow for an areal density of over 29 18 gigabits per square inch and storage capacity ...

Page 13: ...timum performance and compliance with applicable industry and governmental regulations Special attention has been given in the areas of safety power distribution shielding audible noise control and temperature regulation The SpinPoint V40 hard disk drives satisfy the following standards and regulations Underwriters Laboratory UL Standard 1950 Information technology equipment including business equ...

Page 14: ...SV2001H SV3012H SV4002H SV6003H SV6014H SV8004H Number of Disks 1 1 1 2 2 2 Number of R W heads 1 2 2 3 4 4 Maximum recording density bpi 504K Maximum flux density fci 536K Track density tpi 57 500 55 000 52 000 Data tracks per surface maximum 55 850 Encoding method Noise Predictive PRML Interface Ultra ATA 66 100 Actuator type Rotary Voice Coil Servo type Embedded Sector Servo Number of Cylinder ...

Page 15: ...ogical Configurations Table 3 3 Logical Configurations DESCRIPTION SV2001H SV3012H SV4002H SV6003H SV6014H SV8004H Default logical mode Number of cylinders Number of heads cylinders Number of sectors heads 38 869 16 63 58 246 16 63 77 622 16 63 116 374 16 63 116 375 16 63 155 127 16 63 Total Number of logical sectors 39 179 952 58 711 968 78 242 976 117 304 992 117 306 000 156 368 016 Capacity 20 ...

Page 16: ...Motor spin down time Typical 7 sec Buffer size 2048 Kbytes NOTES Seek time is defined as the time from the receipt of a read write or seek command until the actuator has repositioned and settled on the desired track with the drive operating at nominal DC input voltages and nominal operating temperature Average seek time is determined by averaging the time to complete 1 000 seeks of random length A...

Page 17: ...Volts Typical Power Watts Maximum Power Watts Spin up 750 2070 26 28 71 Normal 400 235 4 8 Idle 415 225 4 8 Random Seek 1 410 320 6 0 OD Read Write 2 425 225 5 0 Standby 60 15 0 8 Sleep 60 15 0 8 1 Random seek 30 Duty cycle seek commands with logical random location 2 Read Write OD On track Read Write operation at OD 256 sector commands ...

Page 18: ...0 70 C 20 C 15 hr Relative Humidity non condensing Operation Non operation Maximum wet bulb temperature Operating Non operating 5 85 5 95 30 C 40 C Altitude relative to sea level Operating Non operating 650 10 000 feet 1 000 40 000 feet Vibration 1 2 oct min sweep sine Operating 5 21Hz 21 300Hz 300 500Hz Non operating 5 21Hz 21 500Hz 0 034 double amplitude 1 5 G P P 0 5 G P P 0 195 double amplitud...

Page 19: ...G 350G 150G 200G 2K rad sec 2 20K rad sec 2 20K rad sec 2 Acoustic Noise Typical Sound Power Idle Random Read Write Quite Seek 3 1 bels 3 3 bels 3 1 bels 3 7 Reliability Specifications Table 3 7 Reliability Specifications DESCRIPTION SV2001H SV3012H SV4002H SV4002H SV6014H SV8004H Recoverable Read Error 10 in 1011 bits Non Recoverable Read Error 1 sector in 1014 bits MTBF POH 500 000 hours MTTR ty...

Page 20: ...TION This chapter describes how to unpack mount configure and connect a SpinPoint V40 hard disk drive It also describes how to install the drive in systems 4 1 Space Requirements Figure 4 1 shows the external dimensions of the drive Figure 4 1 Mechanical Dimension ...

Page 21: ...ents electronic component damage due to electrostatic discharge To avoid accidental damage to the drive do not use a sharp instrument to open the ESD protection bag 4 Save the packing material for possible future use 4 3 Mounting Refer to your system manual for complete mounting details 1 Be sure that the system power is off 2 For mounting use four 6 32 UNC screws CAUTION To avoid stripping the mo...

Page 22: ...INSTALLATION SpinPoint V40 Product Manual 14 Figure 4 2 Mounting Dimensions in Millimeters ...

Page 23: ...e specified length for the mounting screw described in Figure 4 3 The specified screw length allows full use of the mounting hole threads while avoiding damage or placing unwanted stress on the PCB Figure 4 3 Mounting Screw Clearance CAUTION Using mounting screws that are longer than the maximum lengths specified in Figure 4 3 voids the warranty of the drive ...

Page 24: ...of the Printed Circuit Board PCB Figure 4 4 Table 4 1 lists the pin assignments Table 4 1 Power Connector Pin Assignment Pin Number Power Line Designation 1 12V DC 2 12V Return Ground 3 5V Return Ground 4 5V DC 4 4 2 AT Bus Interface Connector The AT Bus interface connector on the drive connects the drive to an adapter or an on board AT adapter in the computer JHST is a 40 pin Universal Header wit...

Page 25: ...INSTALLATION SpinPoint V40 Product Manual 17 Figure 4 4 DC Power Connector Configuration Jumper Block AT Bus Interface Connector JHST ...

Page 26: ...l capacity of the drive as the Slave in certain old PC systems Cable Select Mode with 32GB Clip Select this mode to limit the capacity of the drive to 32 GB and use the Cable Select feature of the AT Bus Interface for Master Slave selection or to help install the drive to access the full capacity of the drive using Cable Select feature in certain old PC systems NOTES The 32GB Clip may be required ...

Page 27: ...Product Manual 19 Figure 4 5 Jumper Pin Locations on the Drive PCBA Master Master Mode with 32GB Clip Slave Slave Mode with 32GB Clip Cable Select Cable Select Mode with 32GB Clip Figure 4 6 Options for Jumper Block Configuration ...

Page 28: ...ng a 40 pin ribbon cable Ensure that pin 1 of the drive is connected to pin 1 of the motherboard connector To install the drive in a system without a 40 pin AT bus connector on its motherboard an AT bus adapter kit is required The kit includes an adapter board and a ribbon cable to connect the board to the drive Figure 4 7 indicates the cable and power cord connections required for proper drive in...

Page 29: ...opriate parameters for the installed drive according to Table 4 2 III When using Pre Defined type select any drive type that does not exceed the maximum capacity of the drive Table 4 2 shoes the logical parameters that provide the maximum capacity of SpinPoint V40 family drives 6 If the system recognizes the drive but experiences problems on properly handling the full capacity of the drive run Dis...

Page 30: ...ility program To set up the drive using 32GB clip follow the instructions provided below 1 Install a 32 GB clip jumper see section 4 5 2 Boot up the system enter SYSTEM SETUP change the settings for the drive to Auto and exit SYSTEM SETUP NOTE At this point in the installation the drive capacity is limited to 32GB No further steps are needed if the drive is intended to be used as 32 gigabytes 3 To...

Page 31: ... subassemblies cannot be adjusted or field repaired CAUTION To avoid contamination in the HDA never remove or adjust its cover and seals Disassembling the HDA voids your warranty SpinPoint V40 disk drive models and capacities are distinguished by the number of heads and disks The SV4002H has one 1 disk and two 2 read write heads The SV8004H has two 2 disks and four 4 read write heads 5 1 1 Base Ca...

Page 32: ...DISK DRIVE OPERATION SpinPoint V40 Product Manual 24 Figure 5 1 Exploded Mechanical View ...

Page 33: ...ite heads with the PCBA via a connector through the base casting The flexible circuit contains a read write Preamplifier IC 5 1 5 Voice Coil Motor and Actuator Latch Assemblies The rotary voice coil motor consists of upper and lower permanent magnets and magnetic yokes fixed to the base casting and a rotary over molded coil on the head stack assembly Each magnet consists of two alternating poles a...

Page 34: ... to perform the ATA interface control buffer data flow management disk format read write control and error correction functions of an embedded disk drive controller The DSP communicates with the disk controller module by reading from and writing to its various internal registers To the DSP core the registers of the disk controller appear as unique memory or I O locations that are randomly accessed...

Page 35: ...DISK DRIVE OPERATION SpinPoint V40 Product Manual 27 Figure 5 2 SID2001 AT Controller Block Diagram kzw j p j kzw j p i j k j o p j k ljj j i t p k p o p ...

Page 36: ...ransfer of one sector of the selected single sector write operation is automated Automatic Task File registers updates during automatic multi sector transfers Programmable methods of IRQ assertion allow automation to work with different BIOS implementations and different device drivers Capability to execute multiple consecutive Auto Write commands without loss of data in the buffer 96 byte host FI...

Page 37: ... started based on buffer full or empty status A prioritized five ports architecture is implemented All ports except the refresh port utilize 22 bit buffer address pointers The data path to the buffer RAM can be configured as 16 bit path in ATA mode SDRAM is fixed at 16 Mbits external 32 byte Page Mode accesses along with RAS refresh are implemented The full buffer bandwidth of SID2001 is 145 Mbyte...

Page 38: ...d zero latency read operations with minimal DSP intervention Disk Transfer Length registers monitoring in Disk Sequencer Programmable Wrap To registers Ability to specify at which sector to wrap Wrap To register independent of the stopping sector Index counter for power management command support Time out support when waiting for Sync Index Sector and End of Servo burst to relieve DSP of overhead ...

Page 39: ...k AT disk controller and servo clock from the External Reference clock input 5 2 2 6 Power Management Power management features are incorporated into each block of the SID2001 This allows the designer to tailor the amount of power management to the specified design Other power management features include Independent power management control for each block DSP block powered down and up when needed ...

Page 40: ...d on the fly 5 2 3 1 Time Base Generator The time base generator provides the write frequency and serves as a reference clock to the synchronizer during non read mode 5 2 3 2 Automatic Gain Control The AGC accepts a differential signal from the pre amp and provide a constant output amplitude to the analog filter It s capable of accepting signal ranges from 40 mV to 400 mVppd 5 2 3 3 Asymmetry Corr...

Page 41: ...DISK DRIVE OPERATION SpinPoint V40 Product Manual 33 Figure 5 3 Read Write 88C5200 ...

Page 42: ...ration track following mode settle mode and velocity control mode 1 Track following mode is used when heads are on track This is a position loop with an integrator in the compensation 2 Settle mode is used for all accesses head switches short track seeks and long track seeks Settle mode is a position loop with velocity damping Settle mode does not use feed forward 3 Velocity control mode is used f...

Page 43: ... controller also generates a preamble field inserts an address mark and transmits the data to the ENDEC in the R W IC where the data is encoded into the 32 34 GCR format and pre compensates for non linear transition shift The amount of write current is set by the SID2001 DSP and Interface Disk Controller through the serial interface to the preamp The SID2001 switches the Preamplifier and Write Dri...

Page 44: ...EP 99h E6h STANDBY IMMEDIATELY 94h E0h READ BUFFER E4h WRITE BUFFER E8h WRITE SAME E9h 5 5 2 Write Caching Write caching improves both single and multi sector write performance by reducing delays introduced by rotational latency When the drive writes a pattern of multiple sequential data it stores the data to a cache buffer and immediately sends a COMMAND COMPLETE message to the host before it wri...

Page 45: ...rror correction polynomial is capable of correcting One 233 bit burst error Ten 3 bytes burst error Up to 60 bytes with reassure pointer off line correction These errors are corrected on the fly with no performance degradation 5 5 6 SMART The intent of Self monitoring Analysis and Reporting Technology SMART is to protect user data and to minimize the likelihood of unscheduled system downtime that ...

Page 46: ...DISK DRIVE OPERATION SpinPoint V40 Product Manual 38 Blank Page ...

Page 47: ...serted at the low level active low No dash or a plus character at the beginning or end of a signal name indicates it is asserted high active high An asserted signal may be driven high or low by an active circuit or it may be pulled to the correct state by the bias circuitry Control signals that are asserted for one function when high and asserted for another function when low are named with the as...

Page 48: ... this signal During power on initialization or after RESET is negated DASP is asserted by Drive 1 within 400 msec to indicate that Drive 1 is present Drive 0 allows up to 450 msec for Drive 1 to assert DASP If Drive 1 is not present Drive 0 may assert DASP to drive an activity LED DASP is negated following acceptance of the first valid command by Drive 1 or after 31 seconds whichever comes first A...

Page 49: ...leared nIEN in the Device Control register If nIEN 1 or the drive is not selected this output is in a high impedance state regardless of the presence or absence of a pending interrupt INTRQ is negated by Assertion of RESET or The setting of SRST of the Device Control register or The host writing to the Command register or The host reading from the Status register On PIO transfers INTRQ is asserted...

Page 50: ...alid Execute Drive Diagnostics command Drive 1 negates PDIAG within 1 msec to indicate to Drive 0 that it is busy and has not yet passed its drive diagnostics If Drive 1 is present then Drive 0 waits for up to 5 seconds from the receipt of a valid Execute Drive Diagnostics command for Drive 1 to assert PDIAG Drive 1 clears BSY before asserting PDIAG as PDIAG is used to indicate that Drive 1 has pa...

Page 51: ...tor Signal Name Pin No Direction AT System BUS RESET 1 RESET DRV Ground 2 Ground DB7 3 SD7 DB8 4 SD8 DB6 5 SD6 DB9 6 SD9 DB5 7 SD5 DB10 8 SD10 DB4 9 SD4 DB11 10 SD11 DB3 11 SD3 DB12 12 SD12 DB2 13 SD2 DB13 14 SD13 DB1 15 SD1 DB14 16 SD14 DB0 17 SD0 DB15 18 SD15 Ground 19 Ground Keypin 20 No Connection ...

Page 52: ...nd 22 Ground IOW 23 IOW Ground 23 Ground IOR 25 IOR Ground 26 Ground IORDY 27 IORDY Reserved 28 No Connection DMACK 29 DMACK Ground 30 Ground INTRQ 31 INTRQ IOCS16 32 IOCS16 ADDR1 33 SA1 PDIAG CBLID 34 PDIAG ADDR0 35 SA0 ADDR2 36 SA2 CS1FX 37 CS0 CS3FX 38 CS1 DASP 39 DASP Ground 40 Ground Drive Intercommunication Signals Drive 1 Drive 0 Host 34 PDIAG 34 34 34 39 DASP 39 39 39 ...

Page 53: ...7 I O Bit 5 DD6 5 I O Bit 6 DD7 3 I O Bit 7 DD8 4 I O Bit 8 DD9 6 I O Bit 9 DD10 8 I O Bit 10 DD11 10 I O Bit 11 DD12 12 I O Bit 12 DD13 14 I O Bit 13 DD14 16 I O Bit 14 DD15 18 I O Bit 15 DIOR 25 I Drive I O Read DIOW 23 I Drive I O Write DMACK 29 I DMA Acknowledge DMARQ 21 O DMA Request INTRQ 31 O Drive Interrupt IOCS16 32 O Drive 16 bit I O IORDY 27 O I O Channel Ready PDIAG 34 I O Passed Diagn...

Page 54: ...ice 0 both devices shall execute the command and Device 1 shall post its status to Device 0 via PDIAG Drives are selected by the DEV bit in the Drive Head register see 6 3 4 9 and by a jumper or switch on the device designating it as either Device 0 or Device 1 When DEV 0 Device 0 is selected When DEV 1 Device 1 is selected When a single device is attached to the interface it shall be set as Devic...

Page 55: ...n the device are assumed to be linearly mapped with an initial definition of LBA 0 Cylinder 0 head 0 sector 1 Irrespective of translate mode geometry set by the host the LBA address of a given sector does not change LBA cylinder heads_per_cylinder heads sectors_per_track sector 1 ...

Page 56: ...DA2 DA1 DA0 READ DIOR WRITE DIOW Control Block Registers N N X X X High Impedance Not Used N A 0 X X High Impedance Not Used N A 1 0 X High Impedance Not Used N A 1 1 0 Alternate Status Device Control N A 1 1 1 Device Address Not Used Command Block Registers A N 0 0 0 Data Data A N 0 0 1 Error Register Features A N 0 1 0 Sector Count Sector Count A N 0 1 1 Sector Number Sector Number A N 0 1 1 LBA...

Page 57: ...rive is in progress nWTG 0 nHS3 through nHS0 are the one s complement of the binary coded address of the currently selected head For example if nHS3 through nHS0 are 1100b respectively then head 3 is selected nHS3 is the most significant bit nDS1 is the drive select bit for drive 1 When drive 1 is selected and active nDS1 0 nDS0 is the drive select bit for drive 0 When drive 0 is selected and acti...

Page 58: ...essful 6 3 4 4 Error Register 1F1h This register contains status from the last command executed by the drive or a Diagnostic Code At the completion of any command except Execute Drive Diagnostic the contents of this register are valid when ERR 1 in the Status register Following a power on a reset or completion of an Execute Drive Diagnostic command this register contains a Diagnostic Code see Tabl...

Page 59: ...er address for any disk access In LBA mode this register contains bits 8 15 of the LBA At the end of the command this register is updated to reflect the current disk address 6 3 4 8 Command Register 1F7h This register contains the command code being sent to the drive Command execution begins immediately after this register is written The executable commands the command codes and the necessary para...

Page 60: ...µsec following transfer of 512 bytes of data during execution of a Write Format Track or Write Buffer command or 512 bytes of data and the appropriate number of ECC bytes during the execution of a Write Long command DRDY Drive Ready indicates that the drive is capable of responding to a command When there is an error this bit does not change until the host reads the Status register Then the bit ag...

Page 61: ...he drive sets BSY within 400 nsec sets up the sector buffer for a write operation sets DRQ within 700 µsec and clears BSY within 400 nsec of setting DRQ Upon receipt of a Class 3 command the drive sets BSY within 400 nsec sets up the sector buffer for a write operation sets DRQ within 20 msec and clears BSY within 400 nsec of setting DRQ NOTE DRQ may be set so quickly on Class 2 and Class 3 that t...

Page 62: ... Max Address F8h D 1 Read Sector s w retry 20h y y y y 1 Read Sector s w o retry 21h y y y y 1 Read Verify Sector s w retry 40h y y y y 1 Read Verify Sector s w o retry 41h y y y y 1 Recalibrate 1xh D 1 Seek 7xh y y y 1 Set Features EFh y D 1 Set Max Address F9h y y y 1 Set Multiple Mode C6h y D 1 Sleep Mode 99h E6h D 1 Smart B0h y 1 y y D 1 Standby 96h E2h y D 1 Standby Immediate 94h E0h D 2 Writ...

Page 63: ...e Device Head register y means both the device and head parameters are used D Only the drive parameter is valid and not the head parameter d The device parametric is valid the usage of the head parameter is vendor specific D Address to Device 0 but both devices execute it 1 Smart Enable Disable Auto save 2 Maintained for compatibility ...

Page 64: ...te this command If Drive 1 is present Drive 1 asserts PDIAG within 5 seconds Drive 0 waits up to 6 seconds for Drive 1 to assert PDIAG If Drive 1 has not asserted PDIAG indicating a failure Drive 0 appends 80h to its own diagnostic status Both drives execute diagnostics If a Drive 1 diagnostic failure is detected when Drive 0 status is read then Drive 1 status is obtained by setting the DRV bit an...

Page 65: ...o the data fields in the sectors on the specified logical track The ID fields are not written by this command In LBA mode this command formats a single logical track including the specified LBA 6 4 6 Identify Device ECh The Identify Device command enables the host to receive parameter information from the device When the command is issued the device sets the BSY bit prepares to transfer the 256 wo...

Page 66: ...is 1st character C is on bits DD15 through DD8 of the first word 2nd character o is on bits DD7 through DD0 of the first word 3rd character p is on bits DD15 through DD8 of the second word 4th character y is on bits DD7 through DD0 of the second word etc Table 6 6 IDENTIFY DEVICE information Word Content Description General configuration bit significant information 15 0 ATA device set to 0 14 8 Re...

Page 67: ...ting Bit assignments 15 9 Reserved 8 1 Multiple sector setting is valid 59 0XXXh 7 0 xxh Current setting for number of sectors 60 61 XXXXh Total number of user addressable sectors LBA mode only Word 57 specifies the low world of the capacity 62 0000h Reserved Multiword DMA Transfer Capability 15 8 Multiword DMA transfer mode active 63 XX07h 7 0 7 Multiword DMA transfer modes supported support mode...

Page 68: ... 13 5 0 Reserved 4 0 Removable Media Status Notification feature set supported 3 0 Advanced Power Management feature set supported 2 0 CFA feature set supported 1 0 READ WRITE DMA QUEUED supported 83 4000h 0 0 DOWNLOAD MICROCODE command supported Command set feature supported extension 15 14 01 Word 84 is valid 84 4000h 13 0 0 Reserved Command set feature enabled The default manufacturing setting ...

Page 69: ...10 Ultra DMA mode 2 1 Active 0 Not Active 9 Ultra DMA mode 1 1 Active 0 Not Active 8 Ultra DMA mode 0 1 Active 0 Not Active 7 0 1Fh Ultra DMA transfer mode supported 7 5 Reserved 0 4 Ultra DMA mode 4 1 Support 3 Ultra DMA mode 3 1 Support 2 Ultra DMA mode 2 1 Support 1 Ultra DMA mode 1 1 Support 88 001Fh 0 Ultra DMA mode 0 1 Support 89 92 0000h Reserved 93 4101h Hardware reset result The contents ...

Page 70: ...ntents Corresponding Time out Period 0 00h Timeout Disabled 1 240 01h FOh value 5 seconds 241 251 F1h FBh value 240 30 minutes 252 FCh 21 minutes 253 FDh 8 hours 254 FEh Reserved 255 FFh 21 minutes 15 seconds 6 4 8 Idle Immediate 95h E1h This command causes the drive to set BSY enter Idle Mode clear BSY and generate an interrupt The interrupt is generated even though the drive may not have fully t...

Page 71: ...initializes a slave DMA channel prior to issuing the command Data transfers are qualified by DMARQ and are performed by the slave DMA channel The drive issues only one interrupt per command to indicate that data transfer has stopped and the status is available Any unrecoverable error encountered during execution of a Read DMA command results in the termination of data transfer prior to the sector ...

Page 72: ...ivisible by the block count as many full blocks as possible are transferred followed by a final partial block transfer The partial block transfer shall be for n sectors where n Remainder Sector Count Block Count If the Read Multiple command is attempted before the Set Multiple Mode command has been executed or when Read Multiple commands are disabled then the Read Multiple operation is rejected wi...

Page 73: ...s specified in the Sector Count register A sector count of 0 requests 256 sectors The transfer begins at the sector specified in the Sector Number register See 6 6 1 for the DRQ IRQ and BSY protocol on data transfers If the drive is not already on the desired track an implied seek is performed Once at the desired track the drive searches for the appropriate ID field If retries are disabled and two...

Page 74: ...mode where the error occurred The Sector Count register contains the number of sectors not yet verified 6 4 17 Recalibrate 1xh This command moves the read write heads from anywhere on the disk to cylinder 0 Upon receipt of the command the drive sets BSY and issues a seek to cylinder zero The drive then waits for the seek to complete before updating status clearing BSY and generating an interrupt I...

Page 75: ...bytes of ECC apply on Read Long Write Long commands C2h Disable Automatic Acoustic management feature set CCh Enable reverting to power on defaults When the drive receives this command it sets BSY checks the contents of the Feature register clears BSY and generates an interrupt If the value in the Feature register is not supported or is invalid the drive posts an Aborted Command error Refer to sec...

Page 76: ...ins the maximum cylinder high or LBA bits 23 16 value to be set Device Head If LBA is set to one the maximum address value is an LBA value If LBA is cleared to zero the maximum address value is a CHS value DEV shall indicate the selected device Bits 3 0 contain the native max address head number IDENTIFY DEVICE word 3 minus one or LBA bits 27 24 value to be set Normal outputs Register 7 6 5 4 3 2 ...

Page 77: ...Y DEVICE word 55 the content of word 56 or 65 535 whichever is less 5 If the content of word 61 60 as determined by a successful SET MAX ADDRESS command is greater than 16 514 064 then word 54 shall equal the whole number result of 16 514 064 ý the content of word 55 the content of word 56 or 65 535 whichever is less The content of words 58 57 shall be equal to the new content of word 54 as determ...

Page 78: ...is not supported an Aborted Command error is posted and Read Multiple and Write Multiple commands are disabled If the Sector Count register contains 0 when the command is issued Read and Write Multiple commands are disabled At power on or after a hardware reset the default mode is Read and Write Multiple disabled And on software reset the default mode of Read and Write Multiple will not be changed...

Page 79: ...A D1h SMART READ ATTRIBUTE THRESHOLDS D2h SMART ENABLE DISABLE ATTRIBUTE AUTOSAVE D3h SMART SAVE ATTRIBUTE VALUES D4h SMART EXECUTE OFF LINE IMMEDIATE D5h SMART READ LOG SECTOR D6h SMART WRITE LOG SECTOR D7h Obsolete D8h SMART ENABLE OPERATIONS D9h SMART DISABLE OPERATIONS DAh SMART RETURN STATUS DBh SMART ENABLE DISABLE AUTOMATIC OFF LINE DCh DFh Reserved E0h FFh Vendor specific 6 4 24 1 Smart di...

Page 80: ...he autosave routine the device shall not set BSY to one or clear DRDY to zero If the device receives a command from the host while executing its autosave routine it shall respond to the host within two seconds 6 4 24 3 Smart enable operations D8h This command enables access to all SMART capabilities within the device Prior to receipt of this command SMART data are neither monitored nor saved by th...

Page 81: ...vities and is interrupted by a SMART EXECUTE OFF LINE IMMEDIATE command from the host the device shall abort its off line data collection activities and service the host within two seconds after receipt of the command The device shall then re initiate its off line data collection activities in response to the new EXECUTE OFF LINE IMMEDIATE command 6 4 24 5 Smart read data D0h This command returns ...

Page 82: ...Off line data collection capability The following describes the definition for the off line data collection capability bits If the value of all of these bits is equal to zero then this device implements no off line data collection Bit 0 EXECUTE OFF LINE IMMEDIATE implemented bit If the value of this bit equals one then the SMART EXECUTE OFF LINE IMMEDIATE command is implemented by this device If t...

Page 83: ...omplying with this standard Bits 2 15 reserved The data structure checksum is the two s compliment of the result of a simple eight bit addition of the first 511 bytes in the data structure 6 4 24 6 SMART read log sector D5h This command returns the indicated log sector to the host 6 4 24 7 SMART return status DAh This command is used to communicate the reliability status of the device to the host ...

Page 84: ...ds access the same 512 bytes within the buffer 6 4 28 Write Long 32h with retry 33h without retry This command is similar to the Write Sectors command except that it writes the data and the ECC bytes directly from the sector buffer the drive does not generate the ECC bytes itself Only single sector Write Long operations are supported The transfer of the ECC bytes shall be 8 bits wide and 4 or devi...

Page 85: ...Multiple Mode command has been executed or when Write Multiple commands are disabled the Write Multiple operation is rejected with an aborted command error Disk errors encountered during execution of Write Multiple commands are posted after the attempted disk write of the block or partial block transfer The Write Multiple command ends with the sector in error even if it was in the middle of a bloc...

Page 86: ...mber of the last sector written in CHS mode or the logical block address in LBA mode If an error occurs during a write of more than one sector writing terminates at the sector where the error occurs The Command Block registers contain the cylinder head and sector number of the sector where the error occurred in CHS mode or the logical block address in LBA mode The host may then read the command bl...

Page 87: ... Block registers with their default values e If it was a hardware reset Drive 0 waits for DASP to be asserted by Drive 1 f If operational Drive 1 asserts DASP g Drive 0 waits for PDIAG to be asserted if Drive 1 asserts DASP h If operational Drive 1 clears BSY i If operational Drive 1 asserts PDIAG j Drive 0 clears BSY No interrupt is generated when initialization is complete The default values for...

Page 88: ...V Read Verify Sector s V V V V V V V V V V Recalibrate V V V V V V Seek V V V V V V Set Features V V V V V Set Max Address V V V V Set Multiple Mode V V V V V Sleep V V V V V SMART command V V V V V Standby V V V V V Standby Immediate V V V V V Write Buffer V V V V V Write DMA V V V V V V V Write Long V V V V V V V Write Multiple V V V V V V V Write Sector s V V V V V V V Invalid Command V V V V V...

Page 89: ...equires a reset to be activated see 6 4 22 6 5 3 2 Standby mode When a Standby command is received or an Auto Power Down sequence is enabled and the Auto Power Down Count is zero then the drive enters Standby mode In Stand By mode the drive interface is capable of accepting commands but the media is not immediately accessible 6 5 3 3 Idle mode When an Idle command is received or an Auto Power Down...

Page 90: ... requests and commands complete execution in the shortest possible time See specific power related commands 0 The power conditions in each mode are shown in Table 6 15 Table 6 15 Power Conditions MODE SRST BSY DRDY Interface Active Media SLEEP x x 0 STANDBY x 0 1 Yes 0 IDLE x 0 1 Yes 1 NORMAL x x x Yes 1 See 6 4 22 1 Active 0 Inactive x Doesn t care ...

Page 91: ...tor s 20h SMART Read Data SMART Read Log Sector Execution includes the transfer of one or more 512 byte 512 bytes on Read Long sectors of data from the drive to the host a The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Drive Head registers b The host writes the command code to the Command register c The drive sets BSY and prepares for data transfer ...

Page 92: ...is presented the drive is prepared to transfer data and it is at the host s discretion that the data is transferred 6 6 1 2 PIO Read Aborted Command a b e Setup Issue Read Command Status BSY 0 BSY 1 BSY 0 DRDY 1 DRQ 1 DRQ 0 Assert Negate INTRQ INTRQ Although DRQ 1 there is no data to be transferred under this condition 6 6 2 PIO Data Out Commands This class includes Download Microcode 92h Format 5...

Page 93: ...ars DRQ and sets BSY f When the drive has completed processing of the sector it clears BSY and asserts INTRQ If transfer of another sector is required the drive also sets DRQ g After detecting INTRQ the host reads the Status registers h The drive clears the interrupt i If transfer of another sector is required the above sequence is repeated from d 6 6 2 1 PIO Write Command a b e e Setup Issue Tran...

Page 94: ... Mode C6h Sleep 99h E6h SMART Disable Operation SMART Enable Disable Autosave SMART Enable Operation SMART Execute Off line Immediate SMART Return Status Standby 96h E2h Standby Immediate 94h E0h Execution of these commands involves no data transfer a The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Drive Head registers b The host writes the command c...

Page 95: ...rs is different in that No intermediate sector interrupts are issued on multi sector commands The host resets the DMA channel prior to reading status from the drive The DMA protocol allows a high performance multi tasking operating system to eliminate processor overhead associated with PIO transfers a Command phase 1 Host initializes the slave DMA channel 2 Host updates the Command Block registers...

Page 96: ...and DMA data transfer Reset DMA Status BSY 0 BSY 1 BSY x DRQ x BSY 1 nIEN 0 BSY 0 6 6 4 2 Aborted DMA transfer Initialize DMA Command DMA data Reset DMA Status BSY 0 BSY 1 BSY x DRQ 1 BSY 1 nIEN 0 BSY 0 6 6 4 3 Aborted DMA Command Initialize DMA Command Reset DMA Status BSY 0 BSY 1 BSY 1 BSY 0 nIEN 0 ...

Page 97: ...gs 6 7 1 Register transfers Figure 6 1 defines the relationships between the interface signals for register transfers Peripherals reporting support for PIO mode 3 or 4 shall power up in a PIO mode 0 1 or 2 For PIO modes 3 and above the minimum value of t0 is specified by word 68 in the IDENTIFY DEVICE parameter list Table 6 16 defines the minimum value that shall be placed in word 68 IORDY will be...

Page 98: ...tion of IORDY are described in the following three cases 3 1 Device never negates IORDY devices keeps IORDY released no wait is generated 3 2 Device negates IORDY before tA but causes IORDY to be asserted before tA IORDY is released prior to negation and may be asserted for no more than 5 ns before release no wait generated 3 3 Device negates IORDY before tA IORDY is released prior to negation and...

Page 99: ...th t2 or t2i to ensure that t0 is equal to or greater than the value reported in the devices IDENTIFY DEVICE data A device implementation shall support any legal host implementation 2 This parameter specifies the time from the negation edge of DIOR to the time that the data bus is no longer driven by the device tri state 3The delay from the activation of DIOR or DIOW until the state of IORDY is fi...

Page 100: ...egation of IORDY are described in the following three cases 3 1 Device never negates IORDY devices keeps IORDY released no wait is generated 3 2 Device negates IORDY before tA but causes IORDY to be asserted before tA IORDY is released prior to negation and may be asserted for no more than 5 ns before release no wait generated 3 3 Device negates IORDY before tA IORDY is released prior to negation ...

Page 101: ...mmand inactive time The three timing requirements of t0 t2 and t2i shall be met The minimum total cycle time requirements are greater than the sum of t2 and t2i This means a host implementation may lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value reported in the devices IDENTIFY DEVICE data A device implementation shall support any legal host implementation...

Page 102: ...gate DMARQ within the tL specified time once DMACK is asserted and reassert it again at a later time to resume the DMA operation Alternatively if the device is able to continue the transfer of data the device may leave DMARQ asserted and wait for the host to reassert DMACK 2 This signal may be negated by the Host to suspend the DMA transfer in process 3 This figure shows the transfer of two words ...

Page 103: ... tLW DIOW to DMARQ delay max 40 40 35 tM CS 1 0 valid to DIOR DIOW min 50 30 25 tN CS 1 0 hold min 15 10 10 tZ DMACK to tri state max 20 25 25 NOTE t0 is the minimum total cycle time tD is the minimum command active time and tK tKR or tKW as appropriate is the minimum command recovery time or command inactive time The actual cycle time equals the sum of the actual command active time and the actua...

Page 104: ... 7 4 1 Initiating an Ultra DMA data in burst The values for the timings for each of the Ultra DMA modes are contained in 6 7 4 2 DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 tZAD DA0 DA1 DA2 CS0 CS1 tUI tZAD tACK tACK tENV tENV tZIORDY tFS tFS tDVS tAZ tDVH tACK NOTE The definitions for the STOP HDMARDY and DSTROBE signal lines are not in effect until DMARQ and DMACK are a...

Page 105: ...150 0 150 0 100 0 100 0 75 Limited interlock time see Note 3 tMLI 20 20 20 20 20 20 Interlock time with minimum see Note 3 tUI 0 0 0 0 0 0 Unlimited interlock time see Note 3 tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to release from asserted or negated tZAH 20 20 20 20 20 20 Minimum delay time required for output tZAD 0 0 0 0 0 Drivers to assert or negate from released tENV 20 ...

Page 106: ...ined minimum tLI is a limited time out that has a defined maximum 4 The test load for tDVS and tDVH shall be a lumped capacitor load with no cable or receivers Timing for tDVS and tDVH shall be met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value 5 tZIORDY may be greater than tENV since the device has a pull up on IORDY giving it a known state when re...

Page 107: ... 6 7 4 2 DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 device tSR tRFS tRP NOTES 1 The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY is negated 2 If the tSR timing is not satisfied the host may receive zero one or two more data words from the device Figure 6 6 Host pausing an Ultra DMA data in burst ...

Page 108: ...es are contained in 6 7 4 2 tAZ tIORDYZ CRC DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 DA0 DA1 DA2 CS0 CS1 tACK tLI tMLI tDVS tLI tACK tACK tZAH tDVH tSS tLI NOTE The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 6 7 Device terminating an Ultra DMA data in burst ...

Page 109: ...are contained in 6 7 4 2 tDVH CRC tAZ DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 DA0 DA1 DA2 CS0 CS1 tACK tMLI tLI tLI tIORDYZ tACK tACK tZAH tMLI tDVS tRFS tRP NOTE The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 6 8 Host terminating an Ultra DMA data in burst ...

Page 110: ... DMA modes are contained in 6 7 4 2 DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tUI tACK tENV tZIORDY tLI tDVS tDVH tACK tACK tUI NOTE The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 6 9 Initiating an Ultra DMA data out burst ...

Page 111: ... 0 at host HSTROBE at device DD 15 0 at device tDVH tCYC tCYC tDVS tDVS tDS tDH t2CYC tDH tDVH t2CYC NOTE DD 15 0 and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Figure 6 10 Sustained Ultra DM...

Page 112: ...6 7 4 2 DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host tSR tRFS tRP NOTES 1 The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY is negated 2 If the tSR timing is not statisfied the device may receive zero one or two more data words from the host Figure 6 11 Device pausing an Ultra DMA data out burst ...

Page 113: ...odes are contained in 6 7 4 2 DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tACK tLI tMLI tDVS tLI tLI tACK tIORDYZ tACK CRC tDVH tSS NOTE The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 6 12 Host terminating an Ultra DMA data out burst ...

Page 114: ...s are contained in 6 7 4 2 DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tACK tMLI tDVS tLI tLI tACK CRC tDVH tACK tIORDYZ tMLI tRP tRFS NOTE The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 6 13 Device terminating an Ultra DMA data out burst ...

Page 115: ...n handling the SpinPoint V40 drives 5 Do not touch the components on the PCB 6 Observe the environmental limits specified for this product as listed in section 3 6 7 If it becomes necessary to move your computer system turn off the power to automatically park the heads Parking the heads moves the heads to a safe non data landing zone and locks the heads in place This helps prevent the media and th...

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Summary of Contents for SPINPOINT V40 Series

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Samsung SPINPOINT V40 Series, Product Manual, Page: 109 / 115

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