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SpinPoint P80

 

Product Manual Rev. 01

 

i

 

TABLE OF CONTENTS 

CHAPTER 1

 

SCOPE .................................................................................................................................. 1

 

1.1

 

U

SER 

D

EFINITION

.............................................................................................................................. 1

 

1.2

 

M

ANUAL 

O

RGANIZATION

................................................................................................................. 2

 

1.3

 

T

ERMINOLOGY AND 

C

ONVENTIONS

................................................................................................. 2

 

1.4

 

R

EFERENCE

....................................................................................................................................... 3

 

CHAPTER 2

 

DESCRIPTION .................................................................................................................... 4

 

2.1

 

I

NTRODUCTION

.................................................................................................................................. 4

 

2.2

 

K

EY 

F

EATURES

.................................................................................................................................. 4

 

2.3

 

S

TANDARDS AND 

R

EGULATIONS

....................................................................................................... 5

 

2.4

 

H

ARDWARE 

R

EQUIREMENTS

............................................................................................................ 5

 

CHAPTER 3

 

SPECIFICATIONS.............................................................................................................. 6

 

3.1

 

S

PECIFICATION 

S

UMMARY

................................................................................................................ 6

 

3.2

 

P

HYSICAL 

S

PECIFICATIONS

.............................................................................................................. 7

 

3.3

 

L

OGICAL 

C

ONFIGURATIONS

............................................................................................................. 7

 

3.4

 

P

ERFORMANCE 

S

PECIFICATIONS

...................................................................................................... 8

 

3.5

 

P

OWER 

R

EQUIREMENTS

................................................................................................................... 9

 

3.6

 

E

NVIRONMENTAL 

S

PECIFICATIONS

................................................................................................ 10

 

3.7

 

R

ELIABILITY 

S

PECIFICATIONS

....................................................................................................... 11

 

CHAPTER 4

 

INSTALLATION ............................................................................................................... 12

 

4.1

 

S

PACE 

R

EQUIREMENTS

................................................................................................................... 12

 

4.2

 

U

NPACKING 

I

NSTRUCTIONS

............................................................................................................ 13

 

4.3

 

M

OUNTING

...................................................................................................................................... 13

 

4.3.1

 

Orientation............................................................................................................................... 13

 

4.3.2

 

Clearance................................................................................................................................. 15

 

4.3.3

 

Ventilation................................................................................................................................ 16

 

4.4

 

C

ABLE 

C

ONNECTORS

...................................................................................................................... 16

 

4.4.1

 

DC Power Connector............................................................................................................... 16

 

4.4.2

 

AT-Bus Interface Connector .................................................................................................... 16

 

4.5

 

J

UMPER 

B

LOCK 

C

ONFIGURATIONS

................................................................................................ 18

 

4.6

 

D

RIVE 

I

NSTALLATION

..................................................................................................................... 20

 

4.7

 

S

YSTEM 

S

TARTUP 

P

ROCEDURE

...................................................................................................... 21

 

4.7.1

 

Drive Installation to Access the Full Capacity Using 32GB Clip............................................ 22 

        4.7.2        Drive Installation to Access the Over than 128GB(or 137GB)……………………………….23 

CHAPTER 5

 

DISK DRIVE OPERATION ............................................................................................. 24

 

5.1

 

H

EAD 

/ D

ISK 

A

SSEMBLY 

(HDA) ..................................................................................................... 24

 

5.1.1

 

Base Casting Assembly ............................................................................................................ 24

 

5.1.2

 

DC Spindle Motor Assembly .................................................................................................... 24

 

5.1.3

 

Disk Stack Assembly................................................................................................................. 26

 

5.1.4

 

Head Stack Assembly ............................................................................................................... 26

 

5.1.5

 

Voice Coil Motor and Actuator Latch Assemblies ................................................................... 26

 

5.1.6

 

Air Filtration System................................................................................................................ 26

 

5.2

 

D

RIVE 

E

LECTRONICS

...................................................................................................................... 27

 

5.2.1

 

Digital Signal Process and Interface Controller ..................................................................... 27

 

5.2.2

 

AT Disk Controller................................................................................................................... 27

 

5.2.2.1

 

The Host Interface Control Block ..............................................................................................................29

 

5.2.2.2

 

The Buffer Control Block ...........................................................................................................................30

 

5.2.2.3

 

The Disk Control Block ..............................................................................................................................30

 

5.2.2.4

 

The Disk ECC Control Block .....................................................................................................................31

 

5.2.2.5

 

Frequency Synthesizer ................................................................................................................................31

 

5.2.2.6

 

Power Management.....................................................................................................................................31

 

Summary of Contents for SP0401N

Page 1: ...P80 Series Product Manual SAMSUNG 3 5 Hard Disk Drives April 21 2003 Rev 01 ...

Page 2: ......

Page 3: ...CONNECTORS 16 4 4 1 DC Power Connector 16 4 4 2 AT Bus Interface Connector 16 4 5 JUMPER BLOCK CONFIGURATIONS 18 4 6 DRIVE INSTALLATION 20 4 7 SYSTEM STARTUP PROCEDURE 21 4 7 1 Drive Installation to Access the Full Capacity Using 32GB Clip 22 4 7 2 Drive Installation to Access the Over than 128GB or 137GB 23 CHAPTER 5 DISK DRIVE OPERATION 24 5 1 HEAD DISK ASSEMBLY HDA 24 5 1 1 Base Casting Assembl...

Page 4: ...3 6 DIOR Drive I O Read 39 6 2 3 7 DIOW Drive I O Write 39 6 2 3 8 DMACK DMA Acknowledge 40 6 2 3 9 DMARQ DMA Request 40 6 2 3 10 INTRQ Drive Interrupt 40 6 2 3 11 IOCS16 Drive 16 bit I O 40 6 2 3 12 IORDY I O Channel Ready 41 6 2 3 13 PDIAG Passed Diagnostics 41 6 2 3 14 RESET Drive Reset 41 6 3 LOGICAL INTERFACE 45 6 3 1 General 45 6 3 1 1 Bit Conventions 45 6 3 1 2 Environment 45 6 3 2 I O Regi...

Page 5: ... 37h extended 72 6 4 29 Set Multiple Mode C6h 74 6 4 30 Sleep 99h E6h 74 6 4 31 Standby 96h E2h 75 6 4 32 SMART B0h 75 6 4 32 1 Smart disable operation D9h 75 6 4 32 2 Smart enable disable attribute autosave D2h 76 6 4 32 3 Smart enable operations D8h 76 6 4 32 4 Smart execute off line immediate D4h 76 6 4 32 5 Smart read data D0h 77 6 4 32 6 SMART read log sector D5h 79 6 4 32 7 SMART return stat...

Page 6: ...iming requirements 101 6 7 4 3 Sustained Ultra DMA data in burst 102 6 7 4 4 Host pausing an Ultra DMA data in burst 103 6 7 4 5 Device terminating an Ultra DMA data in burst 104 6 7 4 6 Host terminating an Ultra DMA data in burst 105 6 7 4 7 Initiating an Ultra DMA data out burst 106 6 7 4 8 Sustained Ultra DMA data out burst 107 6 7 4 9 Device pausing an Ultra DMA data out burst 108 6 7 4 10 Hos...

Page 7: ...lues 55 Table 6 6 Diagnostic Codes 57 Table 6 7 IDENTIFY DEVICE information 58 Table 6 8 Automatic Standby Timer Periods 64 Table 6 9 Security password content 68 Table 6 10 Security Erase Unit password 69 Table 6 11 Security Set Password data content 69 Table 6 12 Identifier and security level bit interaction 70 Table 6 13 Set Feature Register Definitions 71 Table 6 14 Transfer mode values 71 Tab...

Page 8: ...28 Figure 5 3 Read Write 88C5500 34 Figure 6 1 Register transfer to from device 96 Figure 6 2 PIO data transfer to from device 98 Figure 6 3 Multiword DMA data transfer 100 Figure 6 4 Initiating an Ultra DMA data in burst 102 Figure 6 5 Sustained Ultra DMA data in burst 104 Figure 6 6 Host pausing an Ultra DMA data in burst 105 Figure 6 7 Device terminating an Ultra DMA data in burst 106 Figure 6 ...

Page 9: ...lpful to the reader 1 1 User Definition The SpinPoint P80 product manual is intended for the following readers Original Equipment Manufacturers OEMs Distributors 1 2 Manual Organization This manual provides information about installation principles of operation and interface command implementation It is organized into the following chapters Chapter 1 SCOPE Chapter 2 DESCRIPTION Chapter 3 SPECIFICA...

Page 10: ... per second Mbytes s Megabytes per second MHz Megahertz mil Millinches ms Milliseconds mV Millivolts ns Nanoseconds Rpm Rotations per minute Tpi Tracks per inch V Volts W Watts This manual uses the following conventions Computer Message Computer message refers to items you type at the computer keyboard These items are listed in all capitals in Courier New font For example FORMAT C S Commands and M...

Page 11: ...character following the signal name For example IOR Notes Notes are used after tables to provide you with supplementary information Host In general the system in which the drive resides is referred to as the host 1 4 Reference For additional information about the AT interface refer to ATA 2 AT Attachment 2 Revision 3 January 1995 ATA 3 Attachment 3 Interface Revision 7b 27 January 1997 ATA 4 AT At...

Page 12: ...ms to the industry standard 3 5 inch form factor The 40 conductor or 80 conductor AT interface connectors are used depending on the transfer mode The SpinPoint P80 incorporates Advanced GMR Giant Magneto Resistive head and Noise Predictive PRML Partial Response Maximum Likelihood signal processing technologies These advanced technologies allow for an a real density of about 60 Gigabits per square ...

Page 13: ...ompliance with applicable industry and governmental regulations Special attention has been given in the areas of safety power distribution shielding audible noise control and temperature regulation The SpinPoint P80 hard disk drives satisfy the following standards and regulations Underwriters Laboratory UL Standard 1950 Information technology equipment including business equipment Canadian Standar...

Page 14: ...inPoint P80 hard disk drives 3 1 Specification Summary Table 3 1 Specifications DESCRIPTION SP0401N SP0802N SP1203N SP1604N Number of Disks 1 1 2 2 Number of R W heads 1 2 3 4 Maximum recording density Kbpi 630 Track density tpi 93 000 Encoding method Noise Predictive PRML Interface Ultra ATA 133 Actuator type Rotary Voice Coil Servo type Embedded Sector Servo Spindle speed rpm 7 200 0 35 ...

Page 15: ... 3 3 Logical Configurations DESCRIPTION SP0401N SP0802N SP1203N SP1604N Default logical mode Number of cylinders Number of heads cylinders Number of sectors heads 77 622 16 63 155 127 16 63 232 632 16 63 310 101 16 63 Total Number of logical sectors 78 242 976 156 368 016 234 493 056 312 581 808 Capacity 40 06 GB 80 06 GB 120 06 GB 160 04 GB Maximum number of logical cylinders in CHS mode is 16 38...

Page 16: ...time is defined as the time from the receipt of a read write or seek command until the actuator has repositioned and settled on the desired track with the drive operating at nominal DC input voltages and nominal operating temperature Average seek time is determined by averaging the time to complete 1 000 seeks of random length Average latency is the time required for the drive to rotate 1 2 of a r...

Page 17: ...12 Volts Typical Power Watts Spin up 1 2 Disk 600 600 1900 1900 N A Normal 600 600 300 400 6 6 7 8 Idle 480 480 300 400 6 0 7 2 Random Seek 1 7 8 9 0 Read Write 2 6 8 8 0 Standby 0 3 0 3 Sleep 0 3 0 3 1 Random seek 30 Duty cycle seek commands with logical random location 2 Read Write OD On track Read Write operation at OD 256 sector commands ...

Page 18: ...lative Humidity non condensing Operation Non operation Maximum wet bulb temperature Operating Non operating 8 90 5 95 30 C 40 C Altitude relative to sea level Operating Non operating 1 000 10 000 feet 1 000 40 000 feet Vibration 1 2 oct min sweep sine Operating Linear 5 21Hz 21 300Hz 300 500Hz Random 10 300Hz 300 400Hz 400 800Hz Non operating 5 21Hz 21 500Hz 0 034 double amplitude 1 5 G P P 0 5 G ...

Page 19: ... Write 350G 200G 200G 2K rad sec 2 20K rad sec 2 20K rad sec 2 Acoustic Noise Typical Sound Power Idle Random Read Write 2 5 bels 2 7 bels 2 disk 2 7 bels 2 9 bels 2 disk 3 7 Reliability Specifications Table 3 7 Reliability Specifications DESCRIPTION SP0401N SP0802N SP1203N SP1604N Recoverable Read Error 10 in 1011 bits Non Recoverable Read Error 1 sector in 1014 bits MTBF POH 600 000 hours MTTR t...

Page 20: ...ALLATION This chapter describes how to unpack mount configure and connect a SpinPoint P80 hard disk drive It also describes how to install the drive in systems 4 1 Space Requirements Figure 4 1 shows the external dimensions of the drive Figure 4 1 Mechanical Dimension ...

Page 21: ...revents electronic component damage due to electrostatic discharge To avoid accidental damage to the drive do not use a sharp instrument to open the ESD protection bag 4 Save the packing material for possible future use 4 3 Mounting Refer to your system manual for complete mounting details 1 Be sure that the system power is off 2 For mounting use four 6 32 UNC screws CAUTION To avoid stripping the...

Page 22: ...INSTALLATION SpinPoint P80 Product Manual Rev 01 14 Figure 4 2 Mounting Dimensions in Millimeters ...

Page 23: ... the specified length for the mounting screw described in Figure 4 3 The specified screw length allows full use of the mounting hole threads while avoiding damage or placing unwanted stress on the PCB Figure 4 3 Mounting Screw Clearance CAUTION Using mounting screws that are longer than the maximum lengths specified in Figure 4 3 voids the warranty of the drive ...

Page 24: ...of the Printed Circuit Board PCB Figure 4 4 Table 4 1 lists the pin assignments Table 4 1 Power Connector Pin Assignment Pin Number Power Line Designation 1 12V DC 2 12V Return Ground 3 5V Return Ground 4 5V DC 4 4 2 AT Bus Interface Connector The AT Bus interface connector on the drive connects the drive to an adapter or an on board AT adapter in the computer JHST is a 40 pin Universal Header wit...

Page 25: ...INSTALLATION SpinPoint P80 Product Manual Rev 01 17 Figure 4 4 DC Power Connector Configuration Jumper Block AT Bus Interface Connector JHST ...

Page 26: ...full capacity of the drive as the Slave in certain old PC systems Cable Select Mode with 32GB Clip Select this mode to limit the capacity of the drive to 32 GB and use the Cable Select feature of the AT Bus Interface for Master Slave selection or to help install the drive to access the full capacity of the drive using Cable Select feature in certain old PC systems NOTES The 32GB Clip may be requir...

Page 27: ...uct Manual Rev 01 19 Figure 4 5 Jumper Pin Locations on the Drive PCBA Master Master Mode with 32GB Clip Slave Slave Mode with 32GB Clip Cable Select Cable Select Mode with 32GB Clip Figure 4 6 Options for Jumper Block Configuration ...

Page 28: ...ibbon cable Ensure that pin 1 of the drive is connected to pin 1 of the motherboard connector For UDMA mode 2 or higher use a 80 conductor ribbon cable To install the drive in a system without a 40 pin AT bus connector on its motherboard an AT bus adapter kit is required The kit includes an adapter board and a ribbon cable to connect the board to the drive Figure 4 7 indicates the cable and power ...

Page 29: ...gram then follow step 5 Perform one of the following steps that applies to your system I Select Auto Detect if it is supported II When using User Defined type enter the appropriate parameters for the installed drive according to Table 4 2 III When using Pre Defined type select any drive type that does not exceed the maximum capacity of the drive Table 4 2 shoes the logical parameters that provide ...

Page 30: ...llation the drive capacity is limited to 32GB No further steps are needed if the drive is intended to be used as 32 gigabytes 3 To access the full capacity reboot the system with the Disk Manager diskette Disk Manager will install Dynamic Drive Overlay on the drive The Dynamic Drive Overlay will take control of the drive from the BIOS each time the system is booted and enable access to the entire ...

Page 31: ...the description below 1 Intel chipset motherboard system 1 2 Windows XP or Windows 2000 Users 48 bit LBA BIOS support is not necessary Simply follow the Large Hard Drive Installation Instructions If the system currently has 48 bit LBA BIOS support no additional changes are needed follow these instructions 1 2 Windows Me Windows 98SE and Windows 98 Users If the BIOS does not currently support 48 bi...

Page 32: ...e subassemblies cannot be adjusted or field repaired CAUTION To avoid contamination in the HDA never remove or adjust its cover and seals Disassembling the HDA voids your warranty SpinPoint P80 disk drive models and capacities are distinguished by the number of heads and disks The SP0802N has one 1 disk and two 2 read write heads The SP1604N has two 2 disks and four 4 read write heads 5 1 1 Base C...

Page 33: ...SpinPoint P80 Product Manual Rev 01 25 Figure 5 1 Exploded Mechanical View ...

Page 34: ... write heads with the PCBA via a connector through the base casting The flexible circuit contains a read write Preamplifier IC 5 1 5 Voice Coil Motor and Actuator Latch Assemblies The rotary voice coil motor consists of upper and lower permanent magnets and magnetic yokes fixed to the base casting and a rotary over molded coil on the head stack assembly Each magnet consists of two alternating pole...

Page 35: ...re to perform the ATA interface control buffer data flow management disk format read write control and error correction functions of an embedded disk drive controller The DSP communicates with the disk controller module by reading from and writing to its various internal registers To the DSP core the registers of the disk controller appear as unique memory or I O locations that are randomly access...

Page 36: ...DISK DRIVE OPERATION SpinPoint P80 Product Manual Rev 01 28 Figure 5 2 88I5522 AT Controller Block Diagram kzw j p j kzw j p i j k j o p j k ljj j i t p k p o p ...

Page 37: ...rst sector Auto Write command execution first sector of a multiple sector write operation is automated or the transfer of one sector of the selected single sector write operation is automated Automatic Task File registers updates during automatic multi sector transfers Programmable methods of IRQ assertion allow automation to work with different BIOS implementations and different device drivers Ca...

Page 38: ...ers The data path to the buffer RAM can be configured as 16 bit path in ATA mode Additional functionality is provided in the Buffer Control block through the following features Increased automation to support minimal latency read operations with minimal latency Capability to support the execution of multiple consecutive Auto Write commands without loss of data due to overwriting of data Auto write...

Page 39: ...hesizer The frequency synthesizer is a clock frequency generation circuit used to generate a DSP clock AT disk controller and servo clock from the External Reference clock input 5 2 2 6 Power Management Power management features are incorporated into each block of the 88I5522 This allows the designer to tailor the amount of power management to the specified design Other power management features i...

Page 40: ...puted on the fly 5 2 3 1 Time Base Generator The time base generator provides the write frequency and serves as a reference clock to the synchronizer during non read mode 5 2 3 2 Automatic Gain Control The AGC accepts a differential signal from the pre amp and provide a constant output amplitude to the analog filter It s capable of accepting signal ranges from 40 mV to 400 mVppd 5 2 3 3 Asymmetry ...

Page 41: ...SpinPoint P80 Product Manual Rev 01 33 Figure 5 3 Read Write 88C5520 ...

Page 42: ...rack following mode is used when heads are on track This is a position loop with an integrator in the compensation 2 Settle mode is used for all accesses head switches short track seeks and long track seeks Settle mode is a position loop with velocity damping Settle mode does not use feed forward 3 Velocity control mode is used for acceleration and deceleration of the actuator for a seek of two or...

Page 43: ...s a preamble field inserts an address mark and transmits the data to the ENDEC in the R W IC where the data is encoded into the 32 34 GCR format and pre compensates for non linear transition shift The amount of write current is set by the 88I5522 DSP and Interface Disk Controller through the serial interface to the preamp The 88I5522 switches the Preamplifier and Write Driver IC to write mode and ...

Page 44: ... of data stored is the logical block or a multiple of the 512 byte sector Therefore all accesses to cache memory must be in multiples of the sector size The following commands empty the cache IDENTIFY DRIVE ECh FORMAT TRACK 50h EXECUTE DRIVE DIAGNOSTIC 90h READ LONG 23h WRITE VERIFY 3Ch INITIALIZE DEVICE PARAMETER 91h SLEEP 99h E6h STANDBY IMMEDIATELY 94h E0h READ BUFFER E4h WRITE BUFFER E8h WRITE...

Page 45: ...t ECC Correction The drive uses a Reed Solomon code to perform error detection and correction For each 512 byte block the software error correction polynomial is capable of correcting One 191 bit burst error Up to 48 bytes with reassure pointer off line correction These errors are corrected on the fly with no performance degradation 5 5 6 SMART The intent of Self monitoring Analysis and Reporting ...

Page 46: ... asserted at the low level active low No dash or a plus character at the beginning or end of a signal name indicates it is asserted high active high An asserted signal may be driven high or low by an active circuit or it may be pulled to the correct state by the bias circuitry Control signals that are asserted for one function when high and asserted for another function when low are named with the...

Page 47: ...ignal During power on initialization or after RESET is negated DASP is asserted by Drive 1 within 400 msec to indicate that Drive 1 is present Drive 0 allows up to 450 msec for Drive 1 to assert DASP If Drive 1 is not present Drive 0 may assert DASP to drive an activity LED DASP is negated following acceptance of the first valid command by Drive 1 or after 31 seconds whichever comes first Any time...

Page 48: ...s cleared nIEN in the Device Control register If nIEN 1 or the drive is not selected this output is in a high impedance state regardless of the presence or absence of a pending interrupt INTRQ is negated by Assertion of RESET or The setting of SRST of the Device Control register or The host writing to the Command register or The host reading from the Status register On PIO transfers INTRQ is asser...

Page 49: ...ecute Drive Diagnostics command Drive 1 negates PDIAG within 1 msec to indicate to Drive 0 that it is busy and has not yet passed its drive diagnostics If Drive 1 is present then Drive 0 waits for up to 5 seconds from the receipt of a valid Execute Drive Diagnostics command for Drive 1 to assert PDIAG Drive 1 clears BSY before asserting PDIAG as PDIAG is used to indicate that Drive 1 has passed it...

Page 50: ...nector Signal Name Pin No Direction AT System BUS RESET 1 RESET DRV Ground 2 Ground DB7 3 SD7 DB8 4 SD8 DB6 5 SD6 DB9 6 SD9 DB5 7 SD5 DB10 8 SD10 DB4 9 SD4 DB11 10 SD11 DB3 11 SD3 DB12 12 SD12 DB2 13 SD2 DB13 14 SD13 DB1 15 SD1 DB14 16 SD14 DB0 17 SD0 DB15 18 SD15 Ground 19 Ground Keypin 20 No Connection ...

Page 51: ...round IOW 23 IOW Ground 23 Ground IOR 25 IOR Ground 26 Ground IORDY 27 IORDY Reserved 28 No Connection DMACK 29 DMACK Ground 30 Ground INTRQ 31 INTRQ IOCS16 32 IOCS16 ADDR1 33 SA1 PDIAG CBLID 34 PDIAG ADDR0 35 SA0 ADDR2 36 SA2 CS1FX 37 CS0 CS3FX 38 CS1 DASP 39 DASP Ground 40 Ground Drive Intercommunication Signals Drive 1 Drive 0 Host 34 PDIAG 34 34 34 39 DASP 39 39 39 ...

Page 52: ...D5 7 I O Bit 5 DD6 5 I O Bit 6 DD7 3 I O Bit 7 DD8 4 I O Bit 8 DD9 6 I O Bit 9 DD10 8 I O Bit 10 DD11 10 I O Bit 11 DD12 12 I O Bit 12 DD13 14 I O Bit 13 DD14 16 I O Bit 14 DD15 18 I O Bit 15 DIOR 25 I Drive I O Read DIOW 23 I Drive I O Write DMACK 29 I DMA Acknowledge DMARQ 21 O DMA Request INTRQ 31 O Drive Interrupt IOCS16 32 O Drive 16 bit I O IORDY 27 O I O Channel Ready PDIAG 34 I O Passed Di...

Page 53: ...oth devices shall execute the command and Device 1 shall post its status to Device 0 via PDIAG Drives are selected by the DEV bit in the Drive Head register see 6 3 4 9 and by a jumper or switch on the device designating it as either Device 0 or Device 1 When DEV 0 Device 0 is selected When DEV 1 Device 1 is selected When a single device is attached to the interface it shall be set as Device 0 Thr...

Page 54: ...s on the device are assumed to be linearly mapped with an initial definition of LBA 0 Cylinder 0 head 0 sector 1 Irrespective of translate mode geometry set by the host the LBA address of a given sector does not change LBA cylinder heads_per_cylinder heads sectors_per_track sector 1 ...

Page 55: ... DA0 READ DIOR WRITE DIOW Control Block Registers N N X X X High Impedance Not Used N A 0 X X High Impedance Not Used N A 1 0 X High Impedance Not Used N A 1 1 0 Alternate Status Device Control N A 1 1 1 Device Address Not Used Command Block Registers A N 0 0 0 Data Data A N 0 0 1 Error Register Features A N 0 1 0 Sector Count Sector Count A N 0 1 1 Sector Number Sector Number A N 0 1 1 LBA bits 0...

Page 56: ...k drive is in progress nWTG 0 nHS3 through nHS0 are the one s complement of the binary coded address of the currently selected head For example if nHS3 through nHS0 are 1100b respectively then head 3 is selected nHS3 is the most significant bit nDS1 is the drive select bit for drive 1 When drive 1 is selected and active nDS1 0 nDS0 is the drive select bit for drive 0 When drive 0 is selected and a...

Page 57: ...6 3 4 4 Error Register 1F1h This register contains status from the last command executed by the drive or a Diagnostic Code At the completion of any command except Execute Drive Diagnostic the contents of this register are valid when ERR 1 in the Status register Following a power on a reset or completion of an Execute Drive Diagnostic command this register contains a Diagnostic Code see Table 6 6 7...

Page 58: ...linder address for any disk access In LBA mode this register contains bits 8 15 of the LBA At the end of the command this register is updated to reflect the current disk address 6 3 4 8 Command Register 1F7h This register contains the command code being sent to the drive Command execution begins immediately after this register is written The executable commands the command codes and the necessary ...

Page 59: ...llowing transfer of 512 bytes of data during execution of a Write Format Track or Write Buffer command or 512 bytes of data and the appropriate number of ECC bytes during the execution of a Write Long command DRDY Drive Ready indicates that the drive is capable of responding to a command When there is an error this bit does not change until the host reads the Status register Then the bit again ind...

Page 60: ... nsec sets up the sector buffer for a write operation sets DRQ within 700 µsec and clears BSY within 400 nsec of setting DRQ Upon receipt of a Class 3 command the drive sets BSY within 400 nsec sets up the sector buffer for a write operation sets DRQ within 20 msec and clears BSY within 400 nsec of setting DRQ NOTE DRQ may be set so quickly on Class 2 and Class 3 that the BSY transition is too sho...

Page 61: ...2 y y y Y 1 Read DMA Extended 25h y y y Y 1 Read Log Extended 2Fh y y y D 1 Read Long w retry 22h 2 y y y y 1 Read Long w o retry 23h 2 y y y y 1 Read Multiple C4h y y y y 1 Read Multiple Extended 29h y y y Y 1 Read Native Max Address F8h Y 1 Read Native Max Address Extended 27h Y 1 Read Sector s w retry 20h y y y Y 1 Read Sector s w o retry 21h 2 y y y Y 1 Read Sector s Extended 24h y y y Y 1 Rea...

Page 62: ... y y y 2 Write Long w o retry 33h 2 y y y y 3 Write Multiple C5h y y y Y 3 Write Multiple Extended 39h y y y Y 2 Write Sector s w retry 30h 2 y y y Y 2 Write Sector s w o retry 31h 2 y y y Y 2 Write Sector s Extended 34h y y y Y Legend CY Cylinder register SC Sector Count register DH Device Head register SN Sector Number register FR Feature register y The register contains a valid parameter for th...

Page 63: ...C3h DEVICE CONFIGURATION SET 00h BFh C4h FFh Reserved The DEVICE CONFIGURATION RESTORE command disables any setting previously made by a DEVICE CONFIGURATION SET command and returns the content of the IDENTIFY DEVICE command response to the original settings as indicated by the data returned from the execution of a DEVICE CONFIGURATION IDENTIFY command The DEVICE CONFIGURATION FREEZE LOCK command ...

Page 64: ...RESS EXT command 6 4 4 Execute Device Diagnostics 90h This command performs the internal diagnostic tests implemented by the drive The DRV bit is ignored Both drives if present shall execute this command If Drive 1 is present Drive 1 asserts PDIAG within 5 seconds Drive 0 waits up to 6 seconds for Drive 1 to assert PDIAG If Drive 1 has not asserted PDIAG indicating a failure Drive 0 appends 80h to...

Page 65: ...o the data fields in the sectors on the specified logical track The ID fields are not written by this command In LBA mode this command formats a single logical track including the specified LBA 6 4 7 Identify Device ECh The Identify Device command enables the host to receive parameter information from the device When the command is issued the device sets the BSY bit prepares to transfer the 256 wo...

Page 66: ...haracter C is on bits DD15 through DD8 of the first word 2nd character o is on bits DD7 through DD0 of the first word 3rd character p is on bits DD15 through DD8 of the second word 4th character y is on bits DD7 through DD0 of the second word etc Table 6 7 IDENTIFY DEVICE information Word Content Description General configuration bit significant information 15 0 ATA device set to 0 14 8 Retired 7 ...

Page 67: ...ssignments 15 9 Reserved 8 1 Multiple sector setting is valid 59 0XXXh 7 0 xxh Current setting for number of sectors 60 61 XXXXh Total number of user addressable sectors LBA mode only Word 57 specifies the low world of the capacity 62 0000h Reserved Multiword DMA Transfer Capability 15 8 Multiword DMA transfer mode active 63 XX07h 7 0 7 Multiword DMA transfer modes supported support mode 0 1 and 2...

Page 68: ...e supported 8 1 Set Max Security feature supported 7 1 Set Address Offset Reserved Area Boot INCITS TR27 2001 6 1 Set Features subcommand required to spin up after power up 5 1 Power up standby feature set supported 4 1 Removable media status notification feature set supported 3 1 Advanced Power Management feature set supported 2 1 CFA feature set supported 1 1 READ WRITE DMA QUEUED supported 0 1 ...

Page 69: ...errupt enabled 7 1 Release interrupt enabled 6 1 Look ahead enabled 5 1 Write cache enabled 4 1 PACKET Command feature set enabled 3 1 Power Management feature set enabled 2 1 Removable Media feature set enabled 1 1 Security Mode feature set enabled 0 1 SMART feature set enabled continued ...

Page 70: ...orted 5 General purpose logging feature set supported 4 1 Valid Configure Stream command has been executed 3 1 Media Card Pass Through command feature set enabled 2 1 Media serial number is valid 1 1 SMART self test supported 87 4003h 0 1 SMART error logging supported Ultra DMA transfer modes 15 8 0Xh Current active Ultra DMA transfer mode 15 Reserved 0 14 Ultra DMA mode 6 1 Active 0 Not Active 13...

Page 71: ...e 7 1 0 Reserved 0 1 Shall be set to one AAM 15 8 Vendor s recommended AAM value 94 XXXXh 7 0 Current AAM value 95 99 0000h Reserved 100 103 Maximum User LBA for 48 bit address 100 LSB 104 127 Reserved Security status 8 Maximum 5 Enhanced security erase supported 4 Expired 3 Frozen 2 Locked 1 Enabled 128 0021h 0 Supported 129 159 0000h Vendor specific 160 255 0000h Reserved ...

Page 72: ... Contents Corresponding Time out Period 0 00h Timeout Disabled 1 240 01h FOh value 5 seconds 241 251 F1h FBh value 240 30 minutes 252 FCh 21 minutes 253 FDh 8 hours 254 FEh Reserved 255 FFh 21 minutes 15 seconds 6 4 9 Idle Immediate 95h E1h This command causes the drive to set BSY enter Idle Mode clear BSY and generate an interrupt The interrupt is generated even though the drive may not have full...

Page 73: ... by DMARQ and are performed by the slave DMA channel The drive issues only one interrupt per command to indicate that data transfer has stopped and the status is available Any unrecoverable error encountered during execution of a Read DMA command results in the termination of data transfer prior to the sector where the error was detected The drive generates an interrupt to indicate that data trans...

Page 74: ...t evenly divisible by the block count as many full blocks as possible are transferred followed by a final partial block transfer The partial block transfer shall be for n sectors where n Remainder Sector Count Block Count If the Read Multiple command is attempted before the Set Multiple Mode command has been executed or when Read Multiple commands are disabled then the Read Multiple operation is r...

Page 75: ...tors as specified in the Sector Count register A sector count of 0 requests 256 sectors The transfer begins at the sector specified in the Sector Number register See 6 6 1 for the DRQ IRQ and BSY protocol on data transfers If the drive is not already on the desired track an implied seek is performed Once at the desired track the drive searches for the appropriate ID field If retries are disabled a...

Page 76: ... read write heads from anywhere on the disk to cylinder 0 Upon receipt of the command the drive sets BSY and issues a seek to cylinder zero The drive then waits for the seek to complete before updating status clearing BSY and generating an interrupt If the drive cannot reach cylinder 0 it posts a Track 0 Not Found error 6 4 20 Security Disable Password F6h The SECURITY DISABLE PASSWORD command tra...

Page 77: ...mand aborted Frozen mode shall be disabled by power off or hardware reset If SECURITY FREEZE LOCK shall be issued when the device is in Frozen mode the command executes and the device shall remain in Frozen mode Commands disabled by SECURITY FREEZE LOCK are SECURITY SET PASSWORD SECURITY UNLOCK SECURITY DISABLE PASSWORD SECURITY ERASE PREPARE SECURITY ERASE UNIT 6 4 24 Security Set Password F1h Th...

Page 78: ...r and the device is in high security level then the password supplied shall be compared with the stored Master password If the device is in maximum security level then the unlock shall be rejected If the Identifier bit is set to user then the device shall compare the supplied password with the stored User password If the password compare fails then the device shall return command aborted to the ho...

Page 79: ...f ECC apply on Read Long Write Long commands C2h Disable Automatic Acoustic management feature set CCh Enable reverting to power on defaults When the drive receives this command it sets BSY checks the contents of the Feature register clears BSY and generates an interrupt If the value in the Feature register is not supported or is invalid the drive posts an Aborted Command error Refer to section 6 ...

Page 80: ...A bits 15 8 value to be set Cylinder High Contains the maximum cylinder high or LBA bits 23 16 value to be set Device Head If LBA is set to one the maximum address value is an LBA value If LBA is cleared to zero the maximum address value is a CHS value DEV shall indicate the selected device Bits 3 0 contain the native max address head number IDENTIFY DEVICE word 3 minus one or LBA bits 27 24 value...

Page 81: ...61 60 ý the content of IDENTIFY DEVICE word 55 the content of word 56 or 65 535 whichever is less 5 If the content of word 61 60 as determined by a successful SET MAX ADDRESS command is greater than 16 514 064 then word 54 shall equal the whole number result of 16 514 064 ý the content of word 55 the content of word 56 or 65 535 whichever is less The content of words 58 57 shall be equal to the ne...

Page 82: ...unt is not supported an Aborted Command error is posted and Read Multiple and Write Multiple commands are disabled If the Sector Count register contains 0 when the command is issued Read and Write Multiple commands are disabled At power on or after a hardware reset the default mode is Read and Write Multiple disabled And on software reset the default mode of Read and Write Multiple will not be cha...

Page 83: ...AD ATTRIBUTE THRESHOLDS D2h SMART ENABLE DISABLE ATTRIBUTE AUTOSAVE D3h SMART SAVE ATTRIBUTE VALUES D4h SMART EXECUTE OFF LINE IMMEDIATE D5h SMART READ LOG SECTOR D6h SMART WRITE LOG SECTOR D7h Obsolete D8h SMART ENABLE OPERATIONS D9h SMART DISABLE OPERATIONS DAh SMART RETURN STATUS DBh SMART ENABLE DISABLE AUTOMATIC OFF LINE DCh DFh Reserved E0h FFh Vendor specific 6 4 32 1 Smart disable operatio...

Page 84: ...f the autosave routine the device shall not set BSY to one or clear DRDY to zero If the device receives a command from the host while executing its autosave routine it shall respond to the host within two seconds 6 4 32 3 Smart enable operations D8h This command enables access to all SMART capabilities within the device Prior to receipt of this command SMART data are neither monitored nor saved by...

Page 85: ... and is interrupted by a SMART EXECUTE OFF LINE IMMEDIATE command from the host the device shall abort its off line data collection activities and service the host within two seconds after receipt of the command The device shall then re initiate its off line data collection activities in response to the new EXECUTE OFF LINE IMMEDIATE command 6 4 32 5 Smart read data D0h This command returns the De...

Page 86: ...FFh Off line data collection capability The following describes the definition for the off line data collection capability bits If the value of all of these bits is equal to zero then this device implements no off line data collection Bit 0 EXECUTE OFF LINE IMMEDIATE implemented bit If the value of this bit equals one then the SMART EXECUTE OFF LINE IMMEDIATE command is implemented by this device ...

Page 87: ...g with this standard Bits 2 15 reserved The data structure checksum is the two s compliment of the result of a simple eight bit addition of the first 511 bytes in the data structure 6 4 32 6 SMART read log sector D5h This command returns the indicated log sector to the host 6 4 32 7 SMART return status DAh This command is used to communicate the reliability status of the device to the host at the ...

Page 88: ...access the same 512 bytes within the buffer 6 4 36 Write DMA CAh 35h extended This command executes in a similar manner to Write Sector s except for the following The host initializes a slave DMA channel prior to issuing the command Data transfers are qualified by DMARQ and are performed by the slave DMA channel The drive issues only one interrupt per command to indicate that data transfer has ter...

Page 89: ...e Mode command has been executed or when Write Multiple commands are disabled the Write Multiple operation is rejected with an aborted command error Disk errors encountered during execution of Write Multiple commands are posted after the attempted disk write of the block or partial block transfer The Write Multiple command ends with the sector in error even if it was in the middle of a block Subse...

Page 90: ...r number of the last sector written in CHS mode or the logical block address in LBA mode If an error occurs during a write of more than one sector writing terminates at the sector where the error occurs The Command Block registers contain the cylinder head and sector number of the sector where the error occurred in CHS mode or the logical block address in LBA mode The host may then read the comman...

Page 91: ...registers with their default values e If it was a hardware reset Drive 0 waits for DASP to be asserted by Drive 1 f If operational Drive 1 asserts DASP g Drive 0 waits for PDIAG to be asserted if Drive 1 asserts DASP h If operational Drive 1 clears BSY i If operational Drive 1 asserts PDIAG j Drive 0 clears BSY No interrupt is generated when initialization is complete The default values for the Co...

Page 92: ...V V V Read Verify Sector s V V V V V V V V V V Recalibrate V V V V V V Seek V V V V V V Set Features V V V V V Set Max Address V V V V Set Multiple Mode V V V V V Sleep V V V V V SMART command V V V V V Standby V V V V V Standby Immediate V V V V V Write Buffer V V V V V Write DMA V V V V V V V Write Long V V V V V V V Write Multiple V V V V V V V Write Sector s V V V V V V V Invalid Command V V V...

Page 93: ... a reset to be activated see 6 4 30 6 5 3 2 Standby mode When a Standby command is received or an Auto Power Down sequence is enabled and the Auto Power Down Count is zero then the drive enters Standby mode In Stand By mode the drive interface is capable of accepting commands but the media is not immediately accessible 6 5 3 3 Idle mode When an Idle command is received or an Auto Power Down sequen...

Page 94: ... requests and commands complete execution in the shortest possible time See specific power related commands Table 6 4 The power conditions in each mode are shown in Table 6 20 Table 6 20 Power Conditions MODE SRST BSY DRDY Interface Active Media SLEEP x x 0 STANDBY x 0 1 Yes 0 IDLE x 0 1 Yes 1 NORMAL x x x Yes 1 See 6 4 30 1 Active 0 Inactive x Doesn t care ...

Page 95: ...0h SMART Read Data SMART Read Log Sector Execution includes the transfer of one or more 512 byte 512 bytes on Read Long sectors of data from the drive to the host a The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Drive Head registers b The host writes the command code to the Command register c The drive sets BSY and prepares for data transfer d When ...

Page 96: ...us is presented the drive is prepared to transfer data and it is at the host s discretion that the data is transferred 6 6 1 2 PIO Read Aborted Command a b e Setup Issue Read Command Status BSY 0 BSY 1 BSY 0 DRDY 1 DRQ 1 DRQ 0 Assert Negate INTRQ INTRQ Although DRQ 1 there is no data to be transferred under this condition 6 6 2 PIO Data Out Commands This class includes Download Microcode 92h Forma...

Page 97: ... and sets BSY f When the drive has completed processing of the sector it clears BSY and asserts INTRQ If transfer of another sector is required the drive also sets DRQ g After detecting INTRQ the host reads the Status registers h The drive clears the interrupt i If transfer of another sector is required the above sequence is repeated from d 6 6 2 1 PIO Write Command a b e e Setup Issue Transfer Re...

Page 98: ...iple Mode C6h Sleep 99h E6h SMART Disable Operation SMART Enable Disable Autosave SMART Enable Operation SMART Execute Off line Immediate SMART Return Status Standby 96h E2h Standby Immediate 94h E0h Execution of these commands involves no data transfer a The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Drive Head registers b The host writes the comma...

Page 99: ...ifferent in that No intermediate sector interrupts are issued on multi sector commands The host resets the DMA channel prior to reading status from the drive The DMA protocol allows a high performance multi tasking operating system to eliminate processor overhead associated with PIO transfers a Command phase 1 Host initializes the slave DMA channel 2 Host updates the Command Block registers 3 Host...

Page 100: ...Command DMA data transfer Reset DMA Status BSY 0 BSY 1 BSY x DRQ x BSY 1 nIEN 0 BSY 0 6 6 4 2 Aborted DMA transfer Initialize DMA Command DMA data Reset DMA Status BSY 0 BSY 1 BSY x DRQ 1 BSY 1 nIEN 0 BSY 0 6 6 4 3 Aborted DMA Command Initialize DMA Command Reset DMA Status BSY 0 BSY 1 BSY 1 BSY 0 nIEN 0 ...

Page 101: ...1 Register transfers Figure 6 1 defines the relationships between the interface signals for register transfers Peripherals reporting support for PIO mode 3 or 4 shall power up in a PIO mode 0 1 or 2 For PIO modes 3 and above the minimum value of t0 is specified by word 68 in the IDENTIFY DEVICE parameter list Table 6 21 defines the minimum value that shall be placed in word 68 IORDY will be suppor...

Page 102: ...egation of IORDY are described in the following three cases 3 1 Device never negates IORDY devices keeps IORDY released no wait is generated 3 2 Device negates IORDY before tA but causes IORDY to be asserted before tA IORDY is released prior to negation and may be asserted for no more than 5 ns before release no wait generated 3 3 Device negates IORDY before tA IORDY is released prior to negation ...

Page 103: ...r t2i to ensure that t0 is equal to or greater than the value reported in the devices IDENTIFY DEVICE data A device implementation shall support any legal host implementation 2 This parameter specifies the time from the negation edge of DIOR to the time that the data bus is no longer driven by the device tri state 3The delay from the activation of DIOR or DIOW until the state of IORDY is first sam...

Page 104: ...d negation of IORDY are described in the following three cases 3 1 Device never negates IORDY devices keeps IORDY released no wait is generated 3 2 Device negates IORDY before tA but causes IORDY to be asserted before tA IORDY is released prior to negation and may be asserted for no more than 5 ns before release no wait generated 3 3 Device negates IORDY before tA IORDY is released prior to negati...

Page 105: ...nactive time The three timing requirements of t0 t2 and t2i shall be met The minimum total cycle time requirements are greater than the sum of t2 and t2i This means a host implementation may lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value reported in the devices IDENTIFY DEVICE data A device implementation shall support any legal host implementation 2 This...

Page 106: ...l negate DMARQ within the tL specified time once DMACK is asserted and reassert it again at a later time to resume the DMA operation Alternatively if the device is able to continue the transfer of data the device may leave DMARQ asserted and wait for the host to reassert DMACK 2 This signal may be negated by the Host to suspend the DMA transfer in process 3 This figure shows the transfer of two wo...

Page 107: ...OW to DMARQ delay max 40 40 35 tM CS 1 0 valid to DIOR DIOW min 50 30 25 tN CS 1 0 hold min 15 10 10 tZ DMACK to tri state max 20 25 25 NOTE t0 is the minimum total cycle time tD is the minimum command active time and tK tKR or tKW as appropriate is the minimum command recovery time or command inactive time The actual cycle time equals the sum of the actual command active time and the actual comma...

Page 108: ...es 6 7 4 1 Initiating an Ultra DMA data in burst The values for the timings for each of the Ultra DMA modes are contained in 6 7 4 2 DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 tZAD DA0 DA1 DA2 CS0 CS1 tUI tZAD tACK tACK tENV tENV tZIORDY tFS tFS tDVS tAZ tDVH tACK NOTE The definitions for the STOP HDMARDY and DSTROBE signal lines are not in effect until DMARQ and DMACK a...

Page 109: ... 150 0 100 0 100 0 75 0 60 Limited interlock time see Note 3 tMLI 20 20 20 20 20 20 20 Interlock time with minimum see Note 3 tUI 0 0 0 0 0 0 0 Unlimited interlock time see Note 3 tAZ 10 10 10 10 10 10 10 Maximum time allowed for output drivers to release from asserted or negated tZAH 20 20 20 20 20 20 20 Minimum delay time required for output tZAD 0 0 0 0 0 0 Drivers to assert or negate from rele...

Page 110: ... defined minimum tLI is a limited time out that has a defined maximum 4 The test load for tDVS and tDVH shall be a lumped capacitor load with no cable or receivers Timing for tDVS and tDVH shall be met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value 5 tZIORDY may be greater than tENV since the device has a pull up on IORDY giving it a known state whe...

Page 111: ...2 DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 device tSR tRFS tRP NOTES 1 The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY is negated 2 If the tSR timing is not satisfied the host may receive zero one or two more data words from the device Figure 6 6 Host pausing an Ultra DMA data in burst ...

Page 112: ...modes are contained in 6 7 4 2 tAZ tIORDYZ CRC DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 DA0 DA1 DA2 CS0 CS1 tACK tLI tMLI tDVS tLI tACK tACK tZAH tDVH tSS tLI NOTE The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 6 7 Device terminating an Ultra DMA data in burst ...

Page 113: ...tained in 6 7 4 2 tDVH CRC tAZ DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 DA0 DA1 DA2 CS0 CS1 tACK tMLI tLI tLI tIORDYZ tACK tACK tZAH tMLI tDVS tRFS tRP NOTE The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 6 8 Host terminating an Ultra DMA data in burst ...

Page 114: ...ltra DMA modes are contained in 6 7 4 2 DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tUI tACK tENV tZIORDY tLI tDVS tDVH tACK tACK tUI NOTE The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 6 9 Initiating an Ultra DMA data out burst ...

Page 115: ...ost HSTROBE at device DD 15 0 at device tDVH tCYC tCYC tDVS tDVS tDS tDH t2CYC tDH tDVH t2CYC NOTE DD 15 0 and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Figure 6 10 Sustained Ultra DMA data ...

Page 116: ...in 6 7 4 2 DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host tSR tRFS tRP NOTES 1 The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY is negated 2 If the tSR timing is not statisfied the device may receive zero one or two more data words from the host Figure 6 11 Device pausing an Ultra DMA data out burst ...

Page 117: ...e contained in 6 7 4 2 DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tACK tLI tMLI tDVS tLI tLI tACK tIORDYZ tACK CRC tDVH tSS NOTE The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 6 12 Host terminating an Ultra DMA data out burst ...

Page 118: ...odes are contained in 6 7 4 2 DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tACK tMLI tDVS tLI tLI tACK CRC tDVH tACK tIORDYZ tMLI tRP tRFS NOTE The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 6 13 Device terminating an Ultra DMA data out burst ...

Page 119: ...ing the SpinPoint P80 drives 5 Do not touch the components on the PCB 6 Observe the environmental limits specified for this product as listed in section 3 6 7 If it becomes necessary to move your computer system turn off the power to automatically park the heads Parking the heads moves the heads to a safe non data landing zone and locks the heads in place This helps prevent the media and the heads...

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