SAMSUNG Proprietary-Contents may change without notice
SGH-V100 Circuit Description
2-
7
Rectangle OSD data in a frame memory can be copied to another place by OSD block copy function. This function
is available both in inter frame copy and in intra frame copy.
-System clock
System clock is 27 MHz.
3)
CODEC(STW5094)
CODEC(STW5094) is a low power Stereo Audio DAC device with Headphones Amplifiers for high quality MP3 and FM
radio listening. The STW5094 includes also an high performance low power combined PCM CODEC/FILTER tailored to
implement the audio front-end functions required by low voltage low power consumption digital cellular terminals with
added MP3 and FM radio listening.
STW5094 offers a number of porgrammable functions accessed through an I2C-bus compatible interface. The STW5094
Stereo Audio DAC section is suited for MP3, or any other stereo source, listening. It supports all the MP3 rates from
8kHz to 48kHz. The audio data serial interface is I2s compatible and can be programmed to handle 16 to 24 bit word
length input data. The internal D to A converters work with 18bit input resolution. The STW5094 Voice Codec section
can be configured either as a 14-bit linear or as an 8-bit companded PCM coder. The Voice Codec can be either the
standard 8kHz value or the extended 16kHz one. In addition to the Stereo Audio DAC and CODEC/FILTER function,
STW5094 includes a Tone/Ring/DTMF generator that can be used both in Audio Listening mode and in Voice Codec
mode, a sidetone control function tailored to handle an external on-hook off-hook button.
4)
FLASH MEMORY(INTEL)
The 3-Volt A Boot Block Flash Memory product line is a high performance memory utilize reliable. This
FLASH memory feature 1.65V - 2.5V or 2.7V - 3.6V I/Os and a low Vcc/Vpp operating range of 2.7V - 3.6V for Read,
Program, and Erase operations. Bus width of this memory is 16bit. A3 chip is multimedia processor, therefore A3 chip
needs operation program. The program is stored this memory by Downloader PGM. A3 system uses Intel's this memory,
GE28F160C3BC70. It is consisted of 16M bits flash memory. It has 16 bit data line, D[0~15] which is connected to A3
chip It has 20 bit address lines, A[1~20]. They are connected too. _XCSO, chip select signals in the A3 chip enable this
memory. This uses 3 volt supply voltage. During writing process, _X_WR is low and it enables writing process to flash
memory. During reading process, _X_RD is low and it output information which is located at the address from the A3
chip in the flash memory. Reading or writing procedure is processed after _X_WR or _X_RD is
5)
NAND FLASH MEMORY(K9F5608U08-DIB0)
This memory offered in 32Mx8bit, the K9F5608U08-DIB0 is 256Mbit with *M bit capacity. The device is offered in 3
Volt Vcc. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program
operation programs the 528-byte page in typical 200usec and an erase operation can be performed in typical 2msec on a
16K-byte block. Data in the page can be read out at 50nsec cycle time per word. The I/O pins serve as the ports for
address and data input/output as well as command input. The on-chip writ control automates all program and erase
functions including pulse repetition, where required, and internal verification and margining of data. This memory is an
optimum solution for large nonvolatile storage applications such solid state file storage and other portable applications
requiring non-volatility. A3 system uses SAMSUNG Semiconductor's memory, K9F5608U08-DIB0. It is consisted of 256M
bits NAND flash memory. Multimedia contents(MPEG and MP3) are stored this memory by downloader Program. It has
8bit I/O line, XD[0~7] which is connected to A3 chip These pins's function are used to input command, address and data,
and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs
are disabled. XA(0) is COMMAND LATCH ENABLE(CLE). The CLE input controls the activating path for commands
sent to the command register. When active high, commands are latched into the command register through the I/O ports