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SAMSUNG Proprietary-Contents may change without notice
Flow Chart of Troubleshooting
10-
9
This Document can not be used without Samsung's authorization
6
46
R
2
1
6
P
T
2
0
6
L
AP_CORE_1.4V
R623
5
46
R
R655
DV_2.8V
C635
SRAM_2.7V
2
0
6
P
T
TP633
2
2
6
R
C613
C614
2.8VDV_1
R606
R631
R604
R637
R639
R616
OSC601
1
D
N
G
2
4
2
D
N
G
1
T
O
H
T
O
H
3
TP699
C638
R640
C619
2.8VDV_1
84
6
R
DV_2.8V
C616
R614
2
46
R
C602
C649
TP625
C604
9
0
6
P
T
SDR_WE
Y9
Y20
C
N
1
2
Y
DSP_BDX0|TRACE_PKT6
Y3
DSP_BDR0|TRACE_PKT3
Y4
SDR_A12
Y5
SDR_A8
Y6
SDR_A5
Y7
SDR_A1
Y8
Y13
SDR_D20
Y14
SDR_D15
Y15
SDR_D11
Y16
Y17 SDR_D10
SDR_D3
Y18
SDR_D0
Y19
DSP_BCLKS0|TRACE_PKT0
Y2
SDR_D1
W6
SDR_A6
W7
SDR_A2
W8
SDR_RAS
W9
C
N
1
Y
SDR_DQM3
Y10
SDR_DQM1
Y11
SDR_D28
Y12
SDR_D23
W18
GIO28|UART_TXD1
W19
0
A
_
M
R
A
2
W
GIO27|UART_RXD1
W20
GIO30|I2C_CLK|SIF_CLK1
W21
1
A
_
M
R
A
3
W
DSP_BFSX0|TRACE_PKT4
W4
W5 SDR_A14
SDR_A11
W10
SDR_DQM2
W11
SDR_D29
W12
SDR_D24
W13
SDR_D19
W14
SDR_D13
W15
SDR_D8
W16
W17 SDR_D4
SDR_D5
3
V
2
A
_
M
R
A
4
V
3
1
A
_
M
R
A
5
V
DSP_BFSR0|TRACE_PKT1
V6
SDR_A9
V7
SDR_A4
V8
SDR_A0
V9
8
A
_
M
R
A
1
W
SDR_CS
V15
SDR_D12
V16
SDR_D9
V17
SDR_D2
V18
GIO33|PWM0|CLKOUT1B
V19
4
A
_
M
R
A
2
V
GIO29|SIF_EN1
V20
GIO32|SIF_DO
V21
5
A
_
M
R
A
3
U
3
A
_
M
R
A
4
U
9
A
_
M
R
A
1
V
SDR_DQM0
V10
SDR_D31
V11
V12 SDR_D27
SDR_D25
V13
SDR_D17
V14
SDR_D16
3
T
4
1
D
D
V
D
4
T
2
1
A
_
M
R
A
1
U
GIO34|PWM1|R2|CLKOUT2B
U18
GIO36|TMRC1
U19
7
A
_
M
R
A
2
U
GIO31|I2C_DATA|SIF_DI1
U20
GIO35|TMRC0
U21
6
A
_
M
R
A
3
1
D
D
V
D
1
R
D
S
_
D
D
V
D
9
R
6
1
A
_
M
R
A
1
T
GIO38|EXT_LINE_ID|B2
T18
GIO40|C_WEN
T19
0
1
A
_
M
R
A
2
T
GIO37|MIRQ|MRST
T20
12
T
K
L
C
S
M|
K
L
C
_
D
S
1
1
A
_
M
R
A
7
D
D
V
D
41
R
S
B
S
M|
D
M
C
_
D
S
8
1
R
3
OI
D
S
M|
3
A
T
A
D
_
D
S
9
1
R
5
1
A
_
M
R
A
2
R
2
OI
D
S
M|
2
A
T
A
D
_
D
S
0
2
R
GIO39|FIELD_VENC
R21
4
1
A
_
M
R
A
3
R
5
D
D
V
D
4
R
8
R
6
1
D
D
V
C
7
P
7
1
D
D
V
C
8
P
5
1
S
S
V
9
P
9
1
A
_
M
R
A
1
R
2
R
D
S
_
D
D
V
D
01
R
3
R
D
S
_
D
D
V
D
11
R
4
R
D
S
_
D
D
V
D
21
R
6
D
D
V
D
31
R
9
1
D
D
V
C
0
OI
D
S
M|
0
A
T
A
D
_
D
S
8
1
P
GIO10|INT10|DSP_BDX1
P19
1
2
A
_
M
R
A
2
P
GIO12|INT12|DSP_BFSX1
P20
1
OI
D
S
M|
1
A
T
A
D
_
D
S
1
2
P
8
1
A
_
M
R
A
3
P
7
1
A
_
M
R
A
4
P
4
1
D
D
V
C
3
1
S
S
V
8
N
0
D
_
M
R
A
1
P
6
1
S
S
V
01
P
7
1
S
S
V
11
P
8
1
S
S
V
21
P
9
1
S
S
V
31
P
8
1
D
D
V
C
41
P
51
P
5
1
D
D
V
C
GIO13|INT13|DSP_BDR1
N18
GIO14|INT14|DSP_BCLKR1
N19
2
D
_
M
R
A
2
N
GIO16|DSP_BCLKS1|CLKOUT0
N20
GIO11|INT11|DSP_BCLKX1
N21
1
D
_
M
R
A
3
N
2
2
A
_
M
R
A
4
N
7
N
M20
USB_DM
M21
6
D
_
M
R
A
3
M
0
2
A
_
M
R
A
4
M
7
M
2
1
D
D
V
C
1
1
S
S
V
8
M
3
D
_
M
R
A
1
N
4
1
S
S
V
4
1
N
51
N
7
L
9
S
S
V
8
L
5
D
_
M
R
A
1
M
2
1
S
S
V
4
1
M
3
1
D
D
V
C
5
1
M
2
D
D
V
_
B
S
U
8
1
M
GIO17|VBUSCHARGE|VLYNQ_RXD0
M19
4
D
_
M
R
A
2
M
GIO15|INT15|DSP_BFSR1
5
1
L
8
1
L
1
D
D
V
_
B
S
U
GIO19|VBUSVAL|VLYNQ_RXD2
L19
8
D
_
M
R
A
2
L
GIO18|VBUSEN|VLYNQ_RXD1
L20
USB_DP
L21
0
1
D
_
M
R
A
3
L
7
D
_
M
R
A
4
L
0
1
D
D
V
C
K20
K21
GIO21|VBUSLO|VLYNQ_TXD0
2
1
D
_
M
R
A
3
K
1
1
D
_
M
R
A
4
K
8
D
D
V
C
7
K
7
S
S
V
8
K
9
D
_
M
R
A
1
L
0
1
S
S
V
4
1
L
1
1
D
D
V
C
7
J
8
J
5
S
S
V
3
1
D
_
M
R
A
1
K
8
S
S
V
4
1
K
9
D
D
V
C
51
K
GIO23|PUCON|VLYNQ_TXD2
K18
GIO20|VBUSSES|VLYNQ_RXD3
K19
4
1
D
_
M
R
A
2
K
GIO22|CID|VLYNQ_TXD1
5
1J
CI0
J18
GIO25|IDEN|VLYNQ_SCRUN|CLKOUT1A
J19
FLASHSEL
J2
GIO24|PDCON|VLYNQ_TXD3
J20
J21
GIO26|VLYNQ_CLOCK|CLKOUT2A
EH_BMUX
J3
5
1
D
_
M
R
A
4
J
6
D
D
V
C
H21
1
E
C
_
M
E
3
H
H
E
B
_
M
E
4
H
1
D
D
V
C
7
H
2
D
D
V
C
8
H
1
S
S
V
9
H
EXTHOST
J1
4
1
J
6
S
S
V
7
D
D
V
C
2
1
H
3
D
D
V
C
31
H
4
D
D
V
C
41
H
5
D
D
V
C
51
H
CI4
H18
CI3
H19
Y
D
R_
F
C
2
H
CI1
H20
CI2
G21
TI
A
W_
F
C
3
G
R
W
OI
_
F
C
4
G
3
D
D
V
D
8
G
4
D
D
V
D
9
G
H
T
DI
W
S
U
B
1
H
2
S
S
V
0
1
H
3
S
S
V
1
1
H
4
S
S
V
1
1
G
0
1
D
D
V
D
2
1
G
1
1
D
D
V
D
3
1
G
4
1
G
2
1
D
D
V
D
G18
CI5
D
V
9
1
G
L
E
B
_
M
E
2
G
G20
CI7|TRACE_SYNC
CI6|TRACE_CLK
YI1|TRACE_PSTATE1
F19
6
1
SI
OI
_
F
C
2
F
YI0|TRACE_PSTATE0
F20
K
L
C
P
1
2
F
3
F
D
R
OI
_
F
C
2
D
D
V
D
4
F
0
E
C
_
M
E
1
G
8
D
D
V
D
0
1
G
9
D
D
V
D
E
O_
F
C
YI2|TRACE_PSTATE2
E20
FIELD_CCD
E21
E
O
_
M
E
3
E
1
D
D
V
D
4
E
5
E
C
N
TI
A
W
_
M
E
1
F
D
H
8
1
F
1
U
M
E
5
D
4
T
U
O
C
6
D
5
T
U
O
C
7
D
HSYNC
D8
3
T
U
O
Y
9
D
E
W
_
M
E
1
E
YI3|TRACE_PKT7
E18
YI6
E19
2
E
CARD_DETGIO8|INT8
YI5
D18
YI7
D19
2
D
1
E
C_
F
C
YI4
D20
M48XO
D21
E
C
_
H
S
A
L
F
3
D
4
D
2
E
C_
F
C
SIF_CLK0|AIMSIF_CLK
4
T
U
O
Y
0
1
D
TEST1
D11
A
D
D
V
2
1
D
VREFIN
D13
N
D
R
W
P
4
1
D
GIO4|INT4
D15
K
C
T
6
1
D
D17
M48XI
C21
TXD0|AIMSIF_DO
C3
SIF_DO0
C4
GIO9|INT9|DSP_XF
C5
1
T
U
O
C
6
C
2
T
U
O
C
7
C
6
T
U
O
C
8
C
9
C
1
T
U
O
Y
D1
SCANEN
C14
GIO2|INT2
C15
6
1
C
T
S
R
T
GIO6|INT6
C17
BTSEL0
C18
C
N
9
1
C
SIF_EN0|AIMSIF_EN
C2
C
N
0
2
C
3
T
U
O
C
7
B
VSYNC
B8
0
T
U
O
Y
9
B
SIF_DI0
C1
7
T
U
O
Y
0
1
C
TEST0
C11
A
S
S
V
21
C
V3
D
D
V
3
1
C
MXO
B19
RXD0|AIMSIF_DI
B2
SYSCLK
B20
C
N
1
2
B
GIO7|INT7
B3
4
B
0
U
M
E
GIO5|INT5
B5
GIO0|INT0
B6
CLKSEL
B11
IREF
B12
V3
S
S
V
3
1
B
S
M
T
4
1
B
2
D
D
V
L
L
P
51
B
TEST2
B16
71
B
1
D
D
V
L
L
P
C
N
8
1
B
AA4
SDR_A13
AA5
SDR_A10
AA6
SDR_A7
AA7
SDR_A3
AA8
SDR_CAS
AA9
C
N
1
B
5
T
U
O
Y
0
1
B
SDR_D18
AA16
SDR_D14
AA17
SDR_D7
AA18
SDR_D6
AA19
C
N
2
A
A
C
N
02
A
A
C
N
1
2
A
A
DSP_BCLKX0|TRACE_PKT5
AA3
DSP_BCLKR0|TRACE_PKT2
2
T
U
O
Y
9
A
C
N
1
A
A
SDR_CKE
AA10
SDR_CLK
AA11
AA12 SDR_D30
SDR_D26
AA13
SDR_D22
AA14
SDR_D21
AA15
C
N
0
2
A
C
N
1
2
A
RTCK
A3
GIO3|INT3
A4
A5
GIO1|INT1
0
T
U
O
C
6
A
7
T
U
O
C
7
A
K
L
C
V
8
A
BIAS
A13
O
D
T
4
1
A
2
S
S
V
L
L
P
51
A
I
D
T
6
1
A
1
S
S
V
L
L
P
71
A
BTSEL1
A18
MXI
A19
C
N
2
A
UCP601
C
N
1
C
N
2
C
N
1
A
6
T
U
O
Y
0
1
A
N
T
S
R
1
1
A
AOUT
A12
C639
ground
3
1
6
P
T
TP607
3
46
R
1
1
6
P
T
1
46
R
0
1
6
P
T
35
6
R
C618
R635
6
1
6
P
T
TP623
TP604
C617
TV_3.0V
C605
R634
15
6
R
2
2
6
P
T
0
5
6
R
4
46
R
7
46
R
25
6
R
9
4
6
R
C636
R636
5
0
6
R
R654
C637
DV_2.8V
C615
R656
02
6
P
T
12
6
P
T
DV_2.8V
DV_2.8V
R619
C620
TP614
7
1
6
P
T
ground
R627
C612
ground
R621
R624
R607
C640
R613
R620
CAM_DAT(7)
CAM_DAT(5)
CAM_DAT(3)
CAM_DAT(1)
MLCD_SCL
CAM_2.8EN
CAS_TX_EN
CAS_DATA_EN
H
_
N
_2
E
R
CASCHIP_EN
CAS_RST
CAS_CLK
CAM_STANBY
AP_PDN_H
SCL_CAM
SDA_CAM
1
U
M
E
0
U
M
E
SIF_EN1
SIF_DO1
MLCD_RESET
EMG_A_H
DM_EMG
TI
A
W
_
M
E
RESET_A_H
MLCD_BL_EN
SIF_DI1
SIF_CLK1
AK_MCLK
MLCD_CS
MLCD_SDO
MLCD_MCLK
nRESET_DMB
RTCK_A
BOOT_SEL1
A
_I
D
T
A
_
O
D
T
DA_OUT
)4
(
R
UART1_RXD
)3
(
R
SR_CAS
XA(3)
XA(7)
XA(10)
XA(13)
A_BCK
XD(6)
XD(7)
XD(14)
XD(18)
XD(21)
XD(22)
XD(26)
XD(30)
SR_CLK
SR_CKE
)0
(
R
BOOT_SEL0
A
_
T
S
R
T
TEST0
)5
(
R
SIF_DI0
MLCD_VSYNC
AP_WAKE_UP_H
IPC_INT_DM
UART_SEL
UART_RXD_C
TEST2
A
_
S
M
T
CLKSEL
H
_
N
_2
E
W
)1
(
R
MLCD_HSYNC
E
L
A_
D
N
CAM_DAT(4)
S
C
_
D
N
A
_
K
C
T
VREF_RGB
TEST1
)2
(
R
SIF_CLK0
E
O
_
D
C
L
M
UART_TXD_C
SIF_EN0
FLASHSEL
CAM_MCLK
EXTHOST
B
R
_
D
N
E
W_
D
N
C
N
Y
S
V
_
M
A
C
E
R
_
D
N
K
L
C
P
_
M
A
C
CAM_DAT(0)
C
N
Y
S
H
_
M
A
C
CAM_DAT(2)
E
L
C_
D
N
CAM_DAT(6)
H
_)
8(
D
AP_SCL
H
_)
9(
D
H
_)
1
1(
D
H
_)
2
1(
D
DMB_EN
H
_)
4
1(
D
H
_)
3
1(
D
H
_)
5
1(
D
EH_BMUX
CAM_RESET-
AP_PCM_CLK
CLK2M
H
_)
2(
D
AT45_nWP
PCM_DIN
H
_)
3(
D
H
_)
1
2(
A
H
_)
6(
D
TV_ON
H
_)
4(
D
H
_)
5(
D
H
_)
7(
D
H
_)
0
1(
D
AP_SDA
H
_)
2
1(
A
H
_)
1
1(
A
ND_WP
H
_)
7
1(
A
H
_)
5
1(
A
H
_)
6
1(
A
H
_)
0
2(
A
H
_)
8
1(
A
H
_)
9
1(
A
PCM_FSYNC
H
_)
2
2(
A
H
_)
0(
D
H
_)
3
2(
A
H
_)
1(
D
XD(2)
XD(9)
XD(12)
XD(16)
XD(17)
XD(25)
XD(27)
XD(31)
SR_DQM0
H
_)
0
1(
A
H
_)
4(
A
H
_)
7(
A
H
_)
8(
A
VCAM_EN
H
_)
3
1(
A
XD(24)
XD(29)
SR_DQM2
SR_CS
H
_)
9(
A
XA(0)
XA(4)
XA(9)
H
_)
4
1(
A
H
_)
3(
A
H
_)
6(
A
H
_)
5(
A
XD(20)
XD(23)
XD(28)
SR_DQM1
SR_DQM3
SR_RAS
XA(2)
XA(6)
XA(11)
XA(14)
A_LRCK
H
_)
2(
A
H
_)
1(
A
UART1_TXD
XD(5)
XD(4)
XD(8)
XD(13)
XD(19)
SR_WE
XA(1)
XA(5)
XA(8)
XA(12)
A_SDOUT
XD(1)
A_MSCK
XD(0)
XD(3)
XD(10)
XD(11)
XD(15)
XA(0:14)
XD(0:31)
H_
S
C_
C
PI
CAM_DAT(0:7)