Samsung S5PC110, Manual

Page: 742 / 2426

S5PC110_UM 1 PULSE WIDTH MODULATION TIMER
1-1
1
PULSE WIDTH MODULATION TIMER
1.1 OVERVIEW OF PULSE WIDTH MODULATION TIMER
The S5PC110 has five 32-bit Pulse Width Modulation (PWM) timers. These timers generate internal interrupts for
the ARM subsystem. In addition, Timers 0, 1, 2 and 3 include a PWM function, which drives an external I/O signal.
The PWM in timer 0 has an optional dead-zone generator capability to support a large current device. Timer 4 is
internal timers without output pins.
The Timers use the APB-PCLK as source clock. Timers 0 and 1 share a programmable 8-bit prescaler that
provides the first level of division for the PCLK. Timers 2, 3, and 4 share a different 8-bit prescaler. Each timer has
its own private clock-divider that provides a second level of clock division (prescaler divided by 2, 4, 8, or 16).
Alternatively, the timers can select a clock source from CMU. Timers 0, 1, 2, 3, and 4 select SCLK_PWM.
Each timer has its own 32-bit down-counter which is driven by the timer clock. The down-counter is initially loaded
from the Timer Count Buffer register (TCNTBn). If the down-counter reaches zero, the timer interrupt request is
generated to inform the CPU that the timer operation is complete. If the timer down-counter reaches zero, the
value of corresponding TCNTBn automatically reloads into the down-counter to start a next cycle. However, if the
timer stops, for example, by clearing the timer enable bit of TCONn during the timer running mode, the value of
TCNTBn is not reloaded into the counter.
The PWM function uses the value of the TCMPBn register. The timer control logic changes the output level if
down-counter value matches the value of the compare register in timer control logic. Therefore, the compare
register determines the turn-on time (or turn-off time) of a PWM output.
The TCNTBn and TCMPBn registers are double buffered to allow the timer parameters to be updated in the
middle of a cycle. The new values do not take effect until the current timer cycle completes.