Samsung S5PC110, Manual

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S5PC110_UM 4 NAND FLASH CONTROLLER
4-6
4.3.3 2048 BYTE 1-BIT ECC PARITY CODE ASSIGNMENT TABLE
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
MECCn_0 ~P64 ~P64’ ~P32 ~P32’ ~P16 ~P16’ ~P8 ~P8’
MECCn_1 ~P1024 ~P1024’ ~P512 ~P512’ ~P256 ~P256’ ~P128 ~P128’
MECCn_2
~P4 ~P4’ ~P2 ~P2’ ~P1 ~P1’ ~P2048 ~P2048’
MECCn_3 1 1 1 1 ~P8192 ~P8192’ ~P4096 ~P4096’
4.3.4 32 BYTE 1-BIT ECC PARITY CODE ASSIGNMENT TABLE
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
SECCn_0 ~P2 ~P2’ ~P1 ~P1’ ~P16 ~P16’ ~P8 ~P8’
SECCn_1 ~P128 ~P128` ~P64 ~P64` ~P32 ~P32` ~P4 ~P4’
4.3.5 1-BIT ECC MODULE FEATURES
The ECC Lock (MainECCLock and SpareECCLock) bit of the control register generates the 1-bit ECC. If
ECCLock is low, the hardware ECC modules generate the ECC codes.
•
1-bit ECC Register Configuration
The following table shows the configuration of 1-bit ECC value read from spare area of external NAND flash
memory. The format of ECC read from memory is important to compare the ECC parity code generated by the
hardware modules.
NOTE:
4-bit/ 8-bit/ 12-bit/ 16-bit ECC decoding scheme is different compared to 1-bit ECC.
•
NAND Flash Memory Interface
Register Bit [31:24] Bit [23:16] Bit [15:8] Bit [7:0]
NFMECCD0 Not used 2nd ECC Not used 1st ECC
NFMECCD1 Not used 4th ECC Not used 3rd ECC
Register Bit [31:24] Bit [23:16] Bit [15:8] Bit [7:0]
NFSECCD Not used 2nd ECC Not used 1st ECC