Samsung S5PC110, Manual

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S5PC110_UM 1 DRAM CONTROLLER
1-12
1.2.5.2 qos_cnt_f
To service latency sensitive commands faster, an adaptive DRAM QoS scheme called QoS fast can be enabled.
This policy cannot be done by the memory controller itself, but the IP has to observe its FIFO level.
For read transactions, for example, when the IP’s FIFO is less than 1/4th full, there is no margin of time available
between the FIFO and the memory controller. At this moment, if the IP flags the memory controller through it’s
qos_fast index path, the qos_cnt_f (
QoSControl(index).qos_cnt_f
) value that is specified for the IP is applied to
the command to give a higher QoS priority over other IP commands.
For write transactions, for example, when the IP’s FIFO is more than 3/4th full, there is almost no margin of time
available before the FIFO becomes full. At this moment, if the IP flags the memory controller through it’s index
path, the qos_cnt_f (
QoSControl(index).qos_cnt_f
) value that is specified for the IP is applied to the command
to give a higher QoS priority over other IP commands.
Figure 1-5
shows the adaptive DRAM QoS scheme configuration in SoC.
qos_fast qos_
fast
index
index
Figure 1-5 Adaptive DRAM QoS Scheme Configuration
Each IP is able to flag the memory controller by accessing a one-bit side-band channel.