S5PC110_UM
1 DRAM CONTROLLER
1-9
1.2.3.2 Dynamic Power Down
The SDRAM device has an active/ precharge power down mode. This mode is entered if CKE becomes LOW. To
enter active power down mode minimum one row of a bank must be open. To enter precharge power down mode
CKE must be low.
If no AXI transaction enters the controller and the command queue becomes empty for a specific number of cycles
(
PwrdnConfig.dpwrdn_cyc
bit-field), the controller changes the memory device’s state to active/ precharge
power down automatically. Then, there are two ways to enter the active/ precharge power down state and it is
selected by
MEMCONTROL.dpwrdn_type
bit.
1. Active/ precharge power down mode: Enter power down without considering whether there is a row open or
not,
2. Force precharge power down mode: Enter power down after closing all banks.
If a new AXI transaction enters the controller, the controller automatically wakes up the memory device from
power down state and executes in a normal operation state.
1.2.3.3 Dynamic Self Refresh
Similar to the dynamic power down feature (Refer to Section 2.3.2 Dynamic Power Down), if the command queue
is empty for a specific amount of cycles (
PwrdnConfig.dsref_cyc
bit-field), the memory device enters self-refresh
mode. Since exiting power down mode requires many cycles, we recommend to choose a greater cycle size for
dynamic self-refresh entry than dynamic power down.
1.2.3.4 Clock Stop
To reduce the I/O power of the memory device and the controller, it is possible to stop the clock if the LPDDR /
LPDDR2 is in idle mode, or self refresh mode and DDR2 is in self refresh mode. If this feature is enabled, the
controller automatically executes the clock stop feature.
1.2.3.5 Direct Command
Use the direct command feature to send a command to the memory device through the APB3 port. This way, you
force the memory device to enter active/ precharge power down, self-refresh or deep power down mode.
1.2.4 PRECHARGE POLICY
There are two ways for the controller to decide precharge policy, namely:
•
Bank selective precharge policy
•
Timeout
precharge
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...