Samsung S5PC110, Manual

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S5PC110_UM 2 CORESIGHT
2-5
Although Coresight’s registers can be accessed through system APB bus as well as JTAG port, the
address map of those registers are observed differently. While the memory map for JTAG port is same as shows
in
Figure 2-2
, the memory map for system view is same as the memory map for JTAG port + system register
offset. The debugger register map of S5PC110 is summarized in
Figure 2-3
.
Coresight ETB
Coresight CTI
CortexA8 CTI
Coresight FUNNEL
CortexA8 Debug
CortexA8 embedded trace
mactocell
ROM table
Reserved
Debugger view
System view
0x0000_7000 or 0x8000_7000
0x0000_6000 or 0x8000_6000
0x0000_5000 or 0x8000_5000
0x0000_4000 or 0x8000_4000
0x0000_3000 or 0x8000_3000
0x0000_2000 or 0x8000_2000
0x0000_1000 or 0x8000_1000
0x0000_0000 or 0x8000_0000 0xE0D0_7000
0xE0D0_6000
0xE0D0_5000
0xE0D0_4000
0xE0D0_3000
0xE0D0_2000
0xE0D0_1000
0xE0D0_0000
SecureJTAG
0xE0D0_8000 0x0000_8000 or 0x8000_8000
Figure 2-3 Debugger Register Map of S5PC110
2.1.2.4 Authentication for Secure JTAG Operation
S5PC110 supports Secure JTAG by using authentication signal of cortexA8 and coresight system.
To set the secure JTAG mode can program Secure JTAG key e-fuse bit.
• [79:0]: Secure JTAG hash key
• [80]: Secure JTAG lock on - 0: non-protection, 1: protected by Secure JTAG
Before authentication, the debugger should access Secure JTAG module mapped in debugger register map.
If Secure JTAG lock on bit is programmed as “1”, the authentication signals such as DBGEN, NIDEN, SPIDEN,
and SPNIDEN are all “0” before passing authentication.