Samsung S5PC110, Manual

Page: 362 / 2426

S5PC110_UM 4 POWER MANAGEMENT
4-2
4.2 FUNCTIONAL DESCRIPTION OF PMU
The total power consumption consists of static and dynamic power consumptions. Static power is consumed when
power to a circuit is supplied and there is no active operation in the circuit. On the other hand, dynamic power is
consumed when the signal to a circuit is changing and there are some active operations in the circuit. The static
power consumption is due to leakage current in the process, while dynamic power consumption is due to the
transition of gate state. The dynamic power consumption depends on the operating voltage, operating frequency,
and toggling ratios of the logic gate.
Various power-saving techniques have been developed, and some of them are shown and compared in
Table
4-1
.
Table 4-1 Comparison of Power Saving Techniques
State Retention
Power saving
techniques
Result Clock Power
Normal F/F Retention F/F
Frequency scaling
Reduce dynamic
power
Enable Supplied Keep state
Clock gating
Minimize dynamic
power
Disable Supplied Keep state
Power gating
Minimize leakage
power Disable
External power
supplied, while
internally gated
Lose state Keep state
Power off Nearly zero power Disable Externally off Lose state
Frequency scaling means that the frequency of clock to a specific module is lowered when the module is not
required to run fast. Dynamic power can be reduced by frequency scaling.
Clock gating means that the clock to a specific Intellectual Property (IP) module is disabled using clock gating
cells in SYSCON. To control these clock gating cells, set registers CLK_GATE_IP0-4 and CLK_GATE_BLOCK in
SYSCON. Clock gating technique is also applied in synthesis phase of chip development flow, where gate-level
netlist is generated from RTL code by synthesis tool. The clock gating cells inserted by synthesis tool are
controlled not by software, but by hardware automatically. When clock gating is applied, power to logic gate is still
supplied. Therefore, the states of Normal Flip-Flop (F/F) and Retention F/F are kept. Retention F/F is developed to
keep its state, even though power is not supplied due to power gating.
Power gating means that a current path to a specific power domain (a group of IP modules) is internally
disconnected using switch cells in that power domain. Therefore, power to that domain is not supplied. The switch
cell can be located between real power and virtual power (HEADER), or between real ground and virtual ground
(FOOTER).
To control the switch cells, set registers NORMAL_CFG, IDLE_CFG, and STOP_CFG in SYSCON. Note that
external power to S5PC110 is not "OFF". When power gating is applied, the states of normal F/Fs are lost, but the
states of retention F/Fs are kept. Therefore, there can be two power-gating techniques, as listed below:
•
Power gating without state retention
−
Normal F/F is used.
•
Wakeup reset is required. Power gating with state retention
−
Retention F/F is used.