S5PC110_UM
12 11BJPEG
12-9
12.6.6 INTERRUPT SIGNAL
Interrupt signal is generated under the following conditions, and the JPGINTST register identifies causes:
1. Compression or decompression process for one picture is complete,
2. Internal timer counting ends before completion of compression or decompression.
3. During compression, the byte size of output stream is larger than the predefined bound size in
ENC_STREAM_BOUND.
In condition 1, the normal process is finished. To clear the interrupt request, read the JPGINTST register and
JPGOPR register. If there is no encoding or decoding error, JPGINTST must be read as 0x40. If another value is
read, the operation result may not be correct.
In condition 2, TIMER_INT_STAT is read as 1 and it is cleared by writing 1 in TIMER_INT_STAT register. In this
case, JPEG requires reset or S/W reset before next operation.
In condition 3, ENC_STREAM_INT_STAT is read as 1, JPEG operation is stopped and there is no further memory
access by JPEG. This interrupt is cleared by writing 1 in ENC_STREAM_INT_STAT register. In this case, JPEG
needs reset or S/W reset before next operation.
12.6.7 INTERRUPT SETTING
If this JPGINTSE register is set, it invokes the interrupt when the input file for decompression is illegal.
To enable timer interrupt, set TIMER_INT_EN to 1 before start or restart.
To deal with an illegal input jpeg file for decompression, set RSTm_INT_EN , DATA_NUM_INT_EN or FINAL
MCU_NUM_INT_EN.
To enable compressed stream size interrupt, set ENC_STREAM_INT_EN to 1 before starting compression.
12.6.8 S/W RESET
JPEG IP has a register for S/W reset. Steps to perform S/W reset:
1. Set 1 in the SW_RESET register.
2. Wait until SW_RESET register value changes to 0.
3. After the value changes to 0, set the proper register for next operation and start the operation.
If JPEG core is terminated abnormally or holds operation, S/W reset is needed to start new operation.
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...