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Samsung S3F80JB, User Manual

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Samsung S3F80JB User Manual Download Page 173

S3F80JB  

 

INSTRUCTION SET 

 

 

6-45 

INCW

 —

 

Increment Word 

INCW 

dst 

Operation:

 dst 

 

←

  dst  +  1 

 

The contents of the destination (which must be an even address) and the byte following that 
location are treated as a single 16-bit value that is incremented by one. 

Flags: C: 

Unaffected. 

 

Z:

  Set if the result is "0"; cleared otherwise. 

 

S:

  Set if the result is negative; cleared otherwise. 

 

V:

  Set if arithmetic overflow occurred; cleared otherwise. 

 

D:

 Unaffected. 

 

H:

 Unaffected. 

Format: 

 

 

 

 

 

 

Bytes Cycles  Opcode 

(Hex) 

Addr Mode 

dst

 

 

opc dst 

 

 

 

2 8  A0 

RR 

 

 

 

 

 

 

 

8 A1 

IR 

 

Examples: 

Given:  R0  =  1AH, R1  =  02H, register 02H  =  0FH, and register 03H  =  0FFH: 

 

 

 

INCW RR0 

→

 

R0  =  1AH, R1  = 03H 

INCW @R1 

→

 

Register 02H  =  10H, register 03H  =  00H 

 

In the first example, the working register pair RR0 contains the value 1AH in register R0 and 02H 
in register R1. The statement "INCW  RR0" increments the 16-bit destination by one, leaving the 
value 03H in register R1. In the second example, the statement "INCW  @R1" uses Indirect 
Register (IR) addressing mode to increment the contents of general register 03H from 0FFH to 
00H and register 02H from 0FH to 10H. 

NOTE: 

A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an 
INCW instruction. To avoid this problem, we recommend that you use INCW as shown in the 
following example: 

LOOP: INCW  RR0 
 LD 

R2,R1 

 

OR R2,R0 

 

JR NZ,LOOP 

 

Summary of Contents for S3F80JB

Page 1: ...S3F80JB 8 BIT CMOS MICROCONTROLLERS USER S MANUAL Revision 1 1 ...

Page 2: ...ons intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmles...

Page 3: ... for additional information presented in the individual hardware module descriptions in Part II Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3F8 series microcontrollers Several summary tables are presented for orientation and reference Detailed descriptions of each instruction are presented in a standard format Each instruction description i...

Page 4: ...2 7 Register Set1 2 8 Register Set 2 2 8 Prime Register Space 2 9 Working Registers 2 10 Using the Register Pointers 2 11 Register Addressing 2 13 Common Working Register Area C0H CFH 2 15 4 Bit Working Register Addressing 2 16 8 Bit Working Register Addressing 2 18 System and User Stacks 2 20 Chapter 3 Addressing Modes Overview 3 1 Register Addressing Mode R 3 2 Indirect Register Addressing Mode ...

Page 5: ...egister IPR 5 12 Interrupt Request Register IRQ 5 14 Interrupt Pending Function Types 5 15 Interrupt Source Polling Sequence 5 16 Interrupt Service Routines 5 16 Generating interrupt Vector Addresses 5 17 Nesting of Vectored Interrupts 5 17 Instruction Pointer IP 5 17 Fast Interrupt Processing 5 17 Chapter 6 Instruction Set Overview 6 1 Flags Register FLAGS 6 6 Flag Descriptions 6 7 Instruction Se...

Page 6: ... External Interrupt Reset 8 7 Stop Error Detection Recovery 8 8 Power Down Modes 8 9 Idle Mode 8 9 Back up mode 8 10 Stop Mode 8 11 Sources to Release Stop Mode 8 12 System Reset Operation 8 14 Hardware Reset Values 8 15 Recommendation for Unusued Pins 8 19 Summary Table of Back Up Mode Stop Mode and Reset Status 8 20 Chapter 9 I O Ports Overview 9 1 Port Data Registers 9 4 Pull Up Resistor Enable...

Page 7: ...ter 11 Timer 1 Overview 11 1 Timer 1 Overflow interrupt 11 2 Timer 1 Capture interrupt 11 2 Timer 1 Match interrupt 11 3 Timer 1 Control Register T1CON 11 5 Chapter 12 Counter A Overview 12 1 Counter A Control Register CACON 12 3 Counter A Pulse Width Calculations 12 4 Chapter 13 Timer 2 Overview 13 1 Timer 2 Overflow Interrupt 13 2 Timer 2 Capture Interrupt 13 2 Timer 2 Match Interrupt 13 3 Timer...

Page 8: ...MUSR 15 6 Flash Memory Sector Address Registers 15 7 Sector Erase 15 8 Programming 15 12 Reading 15 17 Hard Lock Protection 15 18 Chapter 16 Low Voltage Detector Overview 16 1 LVD 16 1 LVD Flag 16 1 Low Voltage Detector Control Register LVDCON 16 3 Chapter 17 Electrical Data 4MHz Overview 17 1 Chapter 18 Electrical Data 8MHz Overview 18 1 Chapter 19 Mechanical Data Overview 19 1 Chapter 20 Develop...

Page 9: ... Register Pair 2 13 2 10 Register File Addressing 2 14 2 11 Common Working Register Area 2 15 2 12 4 Bit Working Register Addressing 2 17 2 13 4 Bit Working Register Addressing Example 2 17 2 14 8 Bit Working Register Addressing 2 18 2 15 8 Bit Working Register Addressing Example 2 19 2 16 Stack Operations 2 20 3 1 Register Addressing 3 2 3 2 Working Register Addressing 3 2 3 3 Indirect Register A...

Page 10: ... 4 Internal Power On Reset Circuit 8 5 8 5 Timing Diagram for Internal Power On Reset Circuit 8 6 8 6 Reset Timing Diagram for The S3F80JB in STOP mode by IPOR 8 7 8 7 Block Diagram for Back up Mode 8 10 8 8 Timing Diagram for Back up Mode Input and Released by LVD 8 10 9 1 S3F80JB I O Port Data Register Format 9 5 9 2 Pull up Resistor Enable Registers Port 0 and Port 2 only 9 6 10 1 Basic Timer C...

Page 11: ...ctor Address Register FMSECL 15 7 15 7 Sector Configurations in User Program Mode 15 8 15 8 Sector Erase Flowchart in User Program Mode 15 9 15 9 Byte Program Flowchart in a User Program Mode 15 13 15 10 Program Flowchart in a User Program Mode 15 14 16 1 Low Voltage Detect LVD Block Diagram 16 2 16 2 Low Voltage Detect Control Register LVDCON 16 3 17 1 Typical Low Side Driver Sink Characteristics...

Page 12: ...ypical High Side Driver Source Characteristics Port0 Port1 P2 4 2 7 P3 4 P3 5 and Port4 18 7 18 7 Stop Mode Release Timing When Initiated by an External Interrupt 18 8 18 8 Stop Mode Release Timing When Initiated by a Reset 18 8 18 9 Stop Mode Release Timing When Initiated by a LVD 18 9 18 10 Input Timing for External Interrupts Port 0 and Port 2 18 10 18 11 Input Timing for Reset nRESET Pin 18 10...

Page 13: ... 2 Flag Notation Conventions 6 8 6 3 Instruction Set Symbols 6 8 6 4 Instruction Notation Conventions 6 9 6 5 Opcode Quick Reference 6 10 6 6 Condition Codes 6 12 8 1 Reset Condition in STOP Mode When IPOR LVD Control Bit is 1 always LVD On 8 8 8 2 Reset Condition in STOP Mode When IPOR LVD Control Bit is 0 8 8 8 3 Set 1 Bank 0 Register Values After Reset 8 15 8 4 Set 1 Bank 1 Register Values Afte...

Page 14: ...17 11 17 8 Oscillation Characteristics 17 11 17 9 Oscillation Stabilization Time 17 12 17 10 AC Electrical Characteristics for Internal Flash ROM 17 13 18 1 Absolute Maximum Ratings 18 2 18 2 D C Electrical Characteristics 18 2 18 3 Characteristics of Low Voltage Detect Circuit 18 4 18 4 Data Retention Supply Voltage in Stop Mode 18 4 18 5 Input Output Capacitance 18 9 18 6 A C Electrical Characte...

Page 15: ...er Area 2 16 Standard Stack Operations Using PUSH and POP 2 21 Chapter 8 Reset To Enter STOP Mode 8 10 Chapter 10 Basic Timer and Timer 0 Configuring the Basic Timer 10 11 Programming Timer 0 10 12 Chapter 12 Counter A To Generate 38 kHz 1 3duty Signal Through P3 1 12 6 To Generate a one Pulse Signal Through P3 1 12 7 Chapter 15 Embedded Flash Memory Interface Sector Erase 15 10 Programming 15 15 ...

Page 16: ... Register 4 18 P0CONL Port 0 Control Register Low Byte 4 20 P0INT Port 0 External Interrupt Enable Register 4 21 P0PND Port 0 External Interrupt Pending Register 4 22 P0PUR Port 0 Pull up Resistor Enable Register 4 23 P1CONH Port 1 Control Register High Byte 4 24 P1CONL Port 1 Control Register Low Byte 4 25 P2CONH Port 2 Control Register High Byte 4 26 P2CONL Port 2 Control Register Low Byte 4 27 ...

Page 17: ...p on Equal 6 31 CPIJNE Compare Increment and Jump on Non Equal 6 32 DA Decimal Adjust 6 33 DA Decimal Adjust 6 34 DEC Decrement 6 35 DECW Decrement Word 6 36 DIV Divide Unsigned 6 38 DJNZ Decrement and Jump if Non Zero 6 39 EI Enable Interrupts 6 40 ENTER Enter 6 41 EXIT Exit 6 42 IDLE Idle Operation 6 43 INC Increment 6 44 INCW Increment Word 6 45 IRET Interrupt Return 6 46 JP Jump 6 47 JR Jump R...

Page 18: ...PUSHUI Push User Stack Incrementing 6 68 RCF Reset Carry Flag 6 69 RET Return 6 70 RL Rotate Left 6 71 RLC Rotate Left Through Carry 6 72 RR Rotate Right 6 73 RRC Rotate Right Through Carry 6 74 SB0 Select Bank 0 6 75 SB1 Select Bank 1 6 76 SBC Subtract With Carry 6 77 SCF Set Carry Flag 6 78 SRA Shift Right Arithmetic 6 79 SRP SRP0 SRP1 Set Register Pointer 6 80 STOP Stop Operation 6 81 SUB Subtr...

Page 19: ...ntroller is fabricated using a highly advanced CMOS process and is based on Samsung s newest CPU architecture The S3F80JB is the microcontroller which has 64 Kbyte Flash Memory ROM Using a proven modular design approach Samsung engineers developed S3F80JB by integrating the following peripheral modules with the powerful SAM8 RC core Internal LVD circuit and 16 bit programmable pins for external in...

Page 20: ...s One programmable 8 bit basic timer BT for oscillation stabilization control or watchdog timer software reset function One 8 bit timer counter Timer 0 with three operating modes Interval mode Capture and PWM mode One 16 bit timer counter Timer1 with two operating modes Interval and Capture mode One 16 bit timer counter Timer2 with two operating modes Interval and Capture mode Back up Mode When VD...

Page 21: ...P0 7 INT4 P1 0 1 7 Port0 Port1 Port2 LVD IPOR note Main OSC 8 Bit Basic Timer 16 Bit Timer1 Counter 16 Bit Timer2 Counter I O Port and Interrupt Control SAM8RC CPU 64K byte FLASH Memory 272 byte Register File Port3 Comparator Carrier Generator Counter A VDD XIN XOUT nRESET Figure 1 1 Block Diagram 32 pin NOTE IPOR can be enabled or disabled by IPOR LVD control bit in the smart option Refer to Figu...

Page 22: ...2 LVD IPOR note Main OSC 8 Bit Basic Timer 16 Bit Timer1 Counter 16 Bit Timer2 Counter I O Port and Interrupt Control SAM8RC CPU 64K byte FLASH Memory 272 byte Register File Port3 Port4 Comparator Carrier Generator Counter A VDD XIN XOUT P3 2 T0CK P3 3 T1CAP T2CAP P4 0 P4 7 P3 4 P3 5 nRESET Figure 1 2 Block Diagram 44 pin NOTE IPOR can be enabled or disabled by IPOR LVD control bit in the smart op...

Page 23: ...T2CAP SDAT P2 4 INT9 CIN0 P2 3 INT8 P2 2 INT7 P2 1 INT6 P2 0 INT5 P0 7 INT4 P0 6 INT4 P0 5 INT4 P0 4 INT4 P0 3 INT3 P0 2 INT2 P0 1 INT1 P0 0 INT0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS XOUT XIN TEST P2 5 INT9 CIN1 P2 6 INT9 CIN2 nRESET P2 7 INT9 CIN3 P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 Figure 1 3 Pin Assignment Diagram 32 Pin SOP Package ...

Page 24: ... INT5 P2 1 INT6 P2 2 INT7 P2 3 INT8 P2 4 INT9 CIN0 P3 0 T0PWM T0CAP SDAT P3 1 REM SCLK V DD V SS X OUT X IN TEST P2 5 INT9 CIN1 P2 6 INT9 CIN2 P1 3 P1 2 P1 1 P4 7 P3 3 T1CAP T2CAP P3 2 T0CK P1 0 P2 7 INT9 CIN3 P3 5 P3 4 nRESET P0 3 INT3 P0 2 INT2 P0 1 INT1 P0 0 INT0 P4 4 P4 5 P4 6 P1 7 P1 6 P1 5 P1 4 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 Figure 1 4 Pin Assignment Diagram 44 Pin ...

Page 25: ...or STOP releasing Also P2 4 P2 7 can be assigned individually as analog input pins for Comparator 1 25 28 29 5 6 8 Ext INT INT5 INT8 INT9 CIN0 CIN3 P3 0 I O I O port with bit programmable pin Configurable to input mode push pull output mode or n channel open drain output mode Input mode with a pull up resistor can be assigned by software This port 3 pin has high current drive capability Also P3 0 ...

Page 26: ...output mode Pull up resistors can be assigned by software Pins can be assigned individually as external interrupt inputs with noise filters interrupt enable disable and interrupt pending control SED R note circuit built in P2 4 P2 7 for STOP releasing Also P2 4 P2 7 can be assigned individually as analog input pins for Comparator 1 42 44 1 2 10 11 15 Ext INT INT5 INT8 INT9 CIN0 CIN3 P3 0 I O I O p...

Page 27: ... SCLK 4 4 REM SCLK P3 2 P3 3 I C MOS Input port with a pull up resistor 5 17 18 T0CK T1CAP T2CAP P3 4 P3 5 I O I O port with bit programmable pins Configurable to input mode or output mode Pin circuits are either push pull or n channel open drain type Pull up resistors can be assigned by software 2 13 14 P4 0 P4 7 I O I O port with bit programmable pins Configurable to input mode or output mode Pi...

Page 28: ...l up Enable VDD INPUT OUTPUT Pull Up Resistor 55kΩ typ Data VSS External Interrupt Output Disable Noise Filter MUX P2CONx x CMPSEL 0 3 P2 4 P2 7 Only REF External REF P2 7 only Comparator Stop Stop Release Figure 1 5 Pin Circuit Type 1 Port 0 and Port2 ...

Page 29: ... OVERVIEW 1 11 PIN CIRCUITS Continued VDD Pull up Resistor 55kΩ Typ VDD VSS Noise Filter INPUT OUTPUT Pull up Enable Data Output Disable Normal Input Open Drain Figure 1 6 Pin Circuit Type 2 Port 1 Port4 P3 4 and P3 5 ...

Page 30: ...inued VDD Pull up Enable P3 0 T0PWM T0CAP T1CAP T2CAP Pull up Resistor 55kΩ Typ Open Drain Port 3 0 Data VSS P3 0 Input M U X P3CON 2 Data Output Disable T0CAP T1CAP T2CAP T0_PWM Noise filter M U X P3CON 2 6 7 VDD Figure 1 7 Pin Circuit Type 3 P3 0 ...

Page 31: ...kΩ Typ Open Drain Port 3 1 Data VSS P3 1 Input M U X P3CON 5 Data Output Disable T0CK Carrier On Off P3 7 CACON 2 Noise filter M U X P3CON 5 6 7 Figure 1 8 Pin Circuit Type 4 P3 1 VDD Pull up Resistor 55kΩ Typ Input T0CK P3 2 T1CAP T2CAP P3 3 M U X P3CON 2 6 7 INPUT Figure 1 9 Pin Circuit Type 5 P3 2 and P3 3 ...

Page 32: ...PRODUCT OVERVIEW S3F80JB 1 14 PIN CIRCUITS Continued VDD Pull up Resistor 500kΩ Typ nRESET Figure 1 10 Pin Circuit Type 6 nRESET ...

Page 33: ... has a programmable internal 64 Kbytes Flash ROM An external memory interface is not implemented There are 333 mapped registers in the internal register file Of these 272 are for general purpose use This number includes a 16 byte working register common area that is used as a scratch area for data operations a 192 byte prime register area and a 64 byte area Set 2 that is also used for stack operat...

Page 34: ...ed in these locations The program memory address at which program execution starts after reset is 0100H default If you use ISPTM sectors as the ISPTM software storage the reset vector address can be changed by setting the Smart Option Refer to Figure 2 2 Internal Program Memory Flash 384 256 128 byte Internal RAM Interrupt Vector Area ISP Sector Smart Option Rom Cell 65 536 Decimal 255 0 00H 0FFH ...

Page 35: ...ss 003FH IPOR LVD Control Bit 0 IPOR enable LVD disable in the stop mode 5 1 IPOR disable LVD enable in the stop mode 6 Not used Frequency Selection Bits 7 Operating Frequency Range 111110 1MHz 4MHz 11111 1MHz 8MHz ISP Reset Vector Address Selection Bits 2 00 200H ISP Area size 256 bytes 01 300H ISP Area size 512 bytes 10 500H ISP Area size 1024 bytes 11 900H ISP Area size 2048 bytes ROM Address 0...

Page 36: ...n size by 3EH 1 and 3EH 0 If ISP Protection Enable Disable Bit 3EH 2 is 1 3EH 1 and 3EH 0 are meaningless 5 If IPOR LVD Control Bit 3FH 7 is 0 IPOR is enabled regardless of operating mode and LVD block is disabled in the STOP mode So the current consumption in the stop mode can be decreased by setting IPOR LVD Control Bit 3FH 7 to 0 Although LVD block is disabled IPOR can make power on reset on th...

Page 37: ...d as shared working registers and 272 registers are for general purpose use The extension of register space into separately addressable areas sets banks is supported by various addressing mode restrictions the select bank instructions SB0 and SB1 Specific register types and the area occupied in the S3F80JB internal register space are summarized in Table 2 1 Table 2 1 The Summary of S3F80JB Registe...

Page 38: ...er Addressing Mode Working Register Working Register Addressing only FFH Set 1 FFH Set 2 C0H Page 0 General Purpose Data Register Indirect Register or Indexed Addressing Modes or Stack Operations 256 Bytes E0H Page 0 Prime Data Register All Addressing Mode BFH 192 Bytes 00H 64 Bytes 32 Bytes 32 Bytes Figure 2 3 Internal Register File Organization ...

Page 39: ...s source value lower nibble and destination value upper nibble are always 0000 automatically Therefore S3F80JB is always selected page 0 as the source and destination page for register addressing These page pointer PP register settings as shown in Figure 2 4 should not be modified during normal operation NOTE A hardware reset operation writes the 4 bit destination and source values shown above to ...

Page 40: ...H You can use the common working register area as a scratch area for data operations being performed in other areas of the register file Registers in set 1 locations are directly accessible at all times using the Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Ch...

Page 41: ...s using any addressing mode In other words there is no addressing mode restriction for these registers as is the case for set 1 and set 2 registers The prime register area on page 0 is immediately addressable following a reset FFH FCH E0H D0H C0H Bank 0 FFH C0H Set 2 00H Prime Register Area Peripheral and IO General purpose CPU and system control Set 1 Bank 1 Page 0 Page 0 BFH Figure 2 5 Set 1 Set...

Page 42: ...e locations of selected working register spaces One working register slice is 8 bytes eight 8 bit working registers R0 R7 or R8 R15 One working register block is 16 bytes sixteen 8 bit working registers R0 R15 All of the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to ...

Page 43: ...ed 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline we recommend that RP0 point to the lower slice and RP1 point to the upper slice see Figure 2 6 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 7 RP0 points to the upper slice and RP1 to the lower ...

Page 44: ...0 R1 ADC R0 R2 R0 R0 R2 C ADC R0 R3 R0 R0 R3 C ADC R0 R4 R0 R0 R4 C ADC R0 R5 R0 R0 R5 C The sum of these six registers 6FH is located in the register R0 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be...

Page 45: ... 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register the least significant byte ...

Page 46: ... Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RP0 points to locations C0H C7H and RP1 to locations C8H CFH that is to the common working register area Control Registers System Registers Bank 1 Prime Registers NOTE In the S3F80JB microcontroller only page0 is implemented Page0 containsall of the addressable regis...

Page 47: ...on area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations 0 Following a hareware reset register pointers RP0 and RP1 point to the common working register area locations C0H CFH FFH F0H C0H Set 1 FFH BFH Set 2 00H Prime Area RP0 RP1 ...

Page 48: ...the address bits are concatenated in the following way to form a complete 8 bit address The high order bit of the 4 bit address selects one of the register pointers 0 selects RP0 1 selects RP1 The five high order bits in the register pointer select an 8 byte slice of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2...

Page 49: ...s Address OPCODE Selects RP0 or RP1 RP1 RP0 4 bit address procides three low order bits Figure 2 12 4 Bit Working Register Addressing Register address 76H RP0 R6 Selects RP0 Instruction INC R6 OPCODE RP1 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 0 1 1 1 0 0 0 1 0 1 1 0 1 1 1 0 Figure 2 13 4 Bit Working Register Addressing Example ...

Page 50: ... address are provided by the original instruction Figure 2 14 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 4 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 011 are provided...

Page 51: ...ies working register addressing RP0 Selects RP1 RP1 0 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 Register address 0ABH 0 1 1 0 1 1 1 0 8 bit address from instruction LD R11 R2 R11 Figure 2 15 8 Bit Working Register Addressing Example ...

Page 52: ...tack address value is always decreased by one before a push operation and increased by one after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 15 Stack contents after a call instruction Stack contents after an interrupt Top of stack Flags PCH PCL PCL PCH Top of stack Low Address High Address Figure 2 16 Stack Operations Us...

Page 53: ...register file using PUSH and POP instructions LD SPL 0FFH SPL FFH Normally the SPL is set to 0FFH by the initialization routine PUSH PP Stack address 0FEH PP PUSH RP0 Stack address 0FDH RP0 PUSH RP1 Stack address 0FCH RP1 PUSH R3 Stack address 0FBH R3 POP R3 R3 Stack address 0FBH POP RP1 RP1 Stack address 0FCH POP RP0 RP0 Stack address 0FDH POP PP PP Stack address 0FEH ...

Page 54: ...e method used to determine the location of the data operand The operands specified in instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 S3F8 series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction Register R Indirect Register IR Indexed X Direct Ad...

Page 55: ...ERAND 8 bit register file address Points to one register in register file One Operand Instruction Example Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Program Memory Register File Figure 3 1 Register Addressing dst OPCODE 4 bit Working Register Points to the woking register 1 of 8 Two Operand Instruction Example Sample Instruction ADD R1 R2 Where R1 and R2 are r...

Page 56: ...register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Remember however that locations C0H FFH in set 1 cannot be accessed using Indirect Register addressing mode dst Address of operand used by instruction OPCODE ADDRESS 8 bit register file address Points to one register in register file One Operand Instruction Example Sam...

Page 57: ...s to Register Pair Example Instruction References Program Memory Sample Instructions CALL RR2 JP RR2 Program Memory Register File Value used in instruction OPERAND Register Pair Program Memory 16 Bit Address Points to Program Memory Figure 3 4 Indirect Register Addressing to Program Memory ...

Page 58: ...Register Address Point to the Woking Register 1 of 8 Sample Instruction OR R3 R6 Program Memory Register File src 3 LSBs Value used in instruction OPERAND Selected RP points to start of woking register block RP0 or RP1 MSB Points to RP0 or RP1 Figure 3 5 Indirect Working Register Addressing to Register File ...

Page 59: ...tion OPERAND Example Instruction References either Program Memory or Data Memory Program Memory or Data Memory Next 2 bit Point to Working Register Pair 1 of 4 LSB Selects 16 Bit address points to program memory or data memory RP0 or RP1 MSB Points to RP0 or RP1 Selected RP points to start of working register block NOTE LDE command is not available because an external interface is not implemented ...

Page 60: ... offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to the base address see Figure 3 9 The only instruction that supports indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instruction...

Page 61: ...ctions LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external data memory is accessed NEXT 2 BITS Register Pair Value used in Instruction 8 Bit 16 Bit 16 Bit dst src OPCODE Program Memory x OFFSET 4 bit Working Register Address NOTE LDE command is not available because an external interface is not ...

Page 62: ...ions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external data memory is accessed NEXT 2 BITS Register Pair Value used in Instruction 16 Bit 16 Bit 16 Bit dst src OPCODE Program Memory x OFFSET 4 bit Working Register Address OFFSET NOTE LDE command is not available because an external inter...

Page 63: ...r Load operations to program memory LDC or to external data memory LDE if implemented Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H Identical operation to LDC example except that external data memory is accessed dst src OPCODE Program Memory 0 or 1 Lower Address Byte LSB Selects Program Memory or Data Memory 0 Program Memory 1 Dat...

Page 64: ...m Memory Lower Address Byte Program Memory Address Used Upper Address Byte Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Next OPCODE Figure 3 11 Direct Addressing for Call and Jump Instructions ...

Page 65: ...ode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Current Instruction Program Memory Locations 0 255 Program Memory OPCODE dst Lower Address Byte Upper Address Byte Next Instruction LSB Must be Zero Sample Inst...

Page 66: ...s the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR OPCODE Program Memory Displacement Program Memory Address Used Sample Instructions JR ULT OFFSET Where OFFSET is a value in ...

Page 67: ...plied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers The operand value is in the instruction OPCODE Sample Instruction LD R0 0AAH Program Memory OPERAND Figure 3 14 Immediate Addressing ...

Page 68: ...egister description format Control register descriptions are arranged in alphabetical order A Z according to the register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual Data and counter registers are not described in detail in this reference section More information about all of the r...

Page 69: ...age Pointer PP 223 DFH R W Port 0 Data Register P0 224 E0H R W Port 1 Data Register P1 225 E1H R W Port 2 Data Register P2 226 E2H R W Port 3 Data Register P3 227 E3H R W Port 4 Data Register P4 228 E4H R W Port 2 Interrupt Enable Register P2INT 229 E5H R W Port 2 Interrupt Pending Register P2PND 230 E6H R W Port 0 Pull up Resistor Enable Register P0PUR 231 E7H R W Port 0 Control Register High Byt...

Page 70: ...2 Mapped Registers Bank1 Set1 Register Name Mnemonic Decimal Hex R W LVD Control Register LVDCON 224 E0 R W Port 3 4 5 Control Register P345CON 225 E1 R W Port 4 Control Register High Byte P4CONH 226 E2 R W Port 4 Control Register Low Byte P4CONL 227 E3 R W Timer 2 Counter Register High Byte T2CNTH 228 E4 R NOTE Timer 2 Counter Register Low Byte T2CNTL 229 E5 R NOTE Timer 2 Data Register High Byte...

Page 71: ...ame for bit addressing D5H Register address Hexadecimal Full register name Register mnemonic Name of individual bit or bit function 7 6 5 4 2 3 1 0 x R W x R W x R W x R W 0 R W x R W 0 R W x R W Zero Flag Bit Z 0 Operation result is a non zero value 1 Operation result is zero Sign Flag Bit S 0 Operation generates positive number MSB 0 1 Operation generates negative number MSB 1 7 Carry Flag Bit C...

Page 72: ...s 0 0 fOSC 4096 0 1 fOSC 1024 1 0 fOSC 128 1 1 Not used for S3F80JB 1 Basic Timer Counter Clear Bit 1 0 No effect 1 Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer and Timer 0 2 0 No effect 1 Clear both block frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to 00H Immediately following the write operation the ...

Page 73: ...fOSC 8 5 and 4 Counter A Interrupt Timing Selection Bits 0 0 Elapsed time for Low data value 0 1 Elapsed time for High data value 1 0 Elapsed time for combined Low and High data values 1 1 Not used for S3F80JB 3 Counter A Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt 2 Counter A Start Bit 0 Stop counter A 1 Start counter A 1 Counter A Mode Selection Bit 0 One shot mode 1 Repeating mo...

Page 74: ...SC 8 1 0 fOSC 2 1 1 fOSC non divided 2 0 Subsystem Clock Selection Bits 2 1 0 1 Not used for S3F80JB Other value Select main system clock MCLK NOTES 1 After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 2 These selection bits CLKCON 0 1 2 are required only for systems that have a main clock...

Page 75: ...ator operation disable 1 Comparator operation enable 6 Conversion Timer Control Bit 0 8 27 fOSC 256 at 8 MHz 1 8 24 fOSC 32 at 8 MHz 5 External Reference Selection Bit 0 Internal reference CIN0 3 Analog input 1 External reference CIN0 2 Analog input CIN3 Reference input 4 Not used for S3F80JB 3 0 Reference Voltage Selection Bits Selected VREF VDD N 0 5 16 N 0 to 15 NOTE You can select the number o...

Page 76: ...t 0 Normal I O selection 1 Alternative function enable CIN3 2 P2 6 Function Selection Bit 0 Normal I O selection 1 Alternative function enable CIN2 1 P2 5 Function Selection Bit 0 Normal I O selection 1 Alternative function enable CIN1 0 P2 4 Function Selection Bit 0 Normal I O selection 1 Alternative function enable CIN0 NOTE If a bit of CMPSEL is set to 1 Comparator input is selected the port pi...

Page 77: ... 5 and 4 Program Memory Automatic Wait Control Bits 0 0 No wait 0 1 Wait one cycle 1 0 Wait two cycles 1 1 Wait three cycles 3 and 2 Data Memory Automatic Wait Control Bits 0 0 No wait 0 1 Wait one cycle 1 0 Wait two cycles 1 1 Wait three cycles 1 Stack Area Selection Bit 0 Select internal register file area 1 Select external data memory area 0 Not used for S3F80JB NOTE The EMT register is not use...

Page 78: ...0 Operation generates a positive number MSB 0 1 Operation generates a negative number MSB 1 4 Overflow Flag Bit V 0 Operation result is 127 or 128 1 Operation result is 127 or 128 3 Decimal Adjust Flag Bit D 0 Add operation completed 1 Subtraction operation completed 2 Half Carry Flag Bit H 0 No carry out of bit 3 or no borrow into bit 3 by addition or subtraction 1 Addition generated carry out of...

Page 79: ... Register addressing mode only 7 4 Flash Memory Mode Selection Bits 0101 Programming mode 1010 Erase mode 0110 Hard Lock mode NOTE Others Not used for S3F80JB 3 1 Not used for S3F80JB 0 Flash Operation Start Bit available for Erase and Hard Lock mode only 0 Operation stop 1 Operation start auto clear bit NOTE Hard Lock mode is one of the flash protection modes Refer to page 15 18 ...

Page 80: ...rite R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory Sector Address Low Byte Note The low byte flash memory sector address pointer value is the lower eight bits of the 16 bit pointer address FMUSR Flash Memory User Programming Enable Register EEH Set1 Bank1 Bit Identifier 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R...

Page 81: ...able mask 1 Enable un mask 5 Interrupt Level 5 IRQ5 Enable Bit External Interrupts P2 7 P2 4 0 Disable mask 1 Enable un mask 4 Interrupt Level 4 IRQ4 Enable Bit External Interrupts P2 3 P2 0 0 Disable mask 1 Enable un mask 3 Interrupt Level 3 IRQ3 Enable Bit Timer 2 Match or Overflow 0 Disable mask 1 Enable un mask 2 Interrupt Level 2 IRQ2 Enable Bit Counter A Interrupt 0 Disable mask 1 Enable un ...

Page 82: ...of the 16 bit instruction pointer address IP15 IP8 The lower byte of the IP address is located in the IPL register DBH IPL Instruction Pointer Low Byte DBH Set1 Bank0 Bit Identifier 7 6 5 4 3 2 1 0 Reset Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is th...

Page 83: ... C A 0 1 0 A B C 0 1 1 B A C 1 0 0 C A B 1 0 1 C B A 1 1 0 A C B 1 1 1 Group priority undefined 6 Interrupt Subgroup C Priority Control Bit 0 IRQ6 IRQ7 1 IRQ7 IRQ6 5 Interrupt Group C Priority Control Bit 0 IRQ5 IRQ6 IRQ7 1 IRQ6 IRQ7 IRQ5 3 Interrupt Subgroup B Priority Control Bit See Note 0 IRQ3 IRQ4 1 IRQ4 IRQ3 2 Interrupt Group B Priority Control Bit See Note 0 IRQ2 IRQ3 IRQ4 1 IRQ3 IRQ4 IRQ2 ...

Page 84: ... 0 0 Not pending 1 Pending 5 Level 5 IRQ5 Request Pending Bit External Interrupts P2 7 P2 4 0 Not pending 1 Pending 4 Level 4 IRQ4 Request Pending Bit External Interrupts P2 3 P2 0 0 Not pending 1 Pending 3 Level 3 IRQ3 Request Pending Bit Timer 2 Match Capture or Overflow 0 Not pending 1 Pending 2 Level 2 IRQ2 Request Pending Bit Counter A Interrupt 0 Not pending 1 Pending 1 Level 1 IRQ1 Request ...

Page 85: ... 0 Read Write R W Addressing Mode Register addressing mode only 7 1 Not used for S3F80JB 0 LVD Flag 2 3V Indicator Bit 0 VDD LVD_FLAG Level 2 3V 1 VDD LVD_FLAG Level 2 3V NOTE When LVD detects LVD_FLAG level 2 3V LVDCON 0 flag bit is set automatically When VDD is upper 2 3V LVDCON 0 flag bit is cleared automatically ...

Page 86: ... falling edges 1 0 Push pull output mode 1 1 C MOS input mode interrupt on rising edges 3 and 2 P0 5 INT4 Mode Selection Bits 0 0 C MOS input mode interrupt on falling edges 0 1 C MOS input mode interrupt on rising and falling edges 1 0 Push pull output mode 1 1 C MOS input mode interrupt on rising edges 1 and 0 P0 4 INT4 Mode Selection Bits 0 0 C MOS input mode interrupt on falling edges 0 1 C MO...

Page 87: ...d falling edges 1 0 Push pull output mode 1 1 C MOS input mode interrupt on rising edges 3 and 2 P0 1 INT1 Mode Selection Bits 0 0 C MOS input mode interrupt on falling edges 0 1 C MOS input mode interrupt on rising and falling edges 1 0 Push pull output mode 1 1 C MOS input mode interrupt on rising edges 1 and 0 P0 0 INT0 Mode Selection Bits 0 0 C MOS input mode interrupt on falling edges 0 1 C M...

Page 88: ...rupt INT4 Enable Bit 0 Disable interrupt 1 Enable interrupt 5 P0 5 External Interrupt INT4 Enable Bit 0 Disable interrupt 1 Enable interrupt 4 P0 4 External Interrupt INT4 Enable Bit 0 Disable interrupt 1 Enable interrupt 3 P0 3 External Interrupt INT3 Enable Bit 0 Disable interrupt 1 Enable interrupt 2 P0 2 External Interrupt INT2 Enable Bit 0 Disable interrupt 1 Enable interrupt 1 P0 1 External ...

Page 89: ...n read 4 P0 4 External Interrupt INT4 Pending Flag Bit 0 No P0 4 external interrupt pending when read 1 P0 4 external interrupt is pending when read 3 P0 3 External Interrupt INT3 Pending Flag Bit 0 No P0 3 external interrupt pending when read 1 P0 3 external interrupt is pending when read 2 P0 2 External Interrupt INT2 Pending Flag Bit 0 No P0 2 external interrupt pending when read 1 P0 2 externa...

Page 90: ...e pull up resistor 1 Enable pull up resistor 5 P0 5 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 4 P0 4 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 3 P0 3 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 2 P0 2 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 1 P...

Page 91: ...drain output mode 1 0 Push pull output mode 1 1 C MOS input with pull up mode 5 and 4 P1 6 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 C MOS input with pull up mode 3 and 2 P1 5 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 C MOS input with pull up mode 1 and 0 P1 4 Mode Selection Bits 0 0 C M...

Page 92: ...rain output mode 1 0 Push pull output mode 1 1 C MOS input with pull up mode 5 and 4 P1 2 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 C MOS input with pull up mode 3 and 2 P1 1 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 C MOS input with pull up mode 1 and 0 P1 0 Mode Selection Bits 0 0 C MO...

Page 93: ...tion Bits 0 0 C MOS input mode interrupt on falling edges 0 1 C MOS input mode interrupt on rising and falling edges 1 0 Push pull output mode 1 1 C MOS input mode interrupt on rising edges 1 and 0 P2 4 INT9 Mode Selection Bits 0 0 C MOS input mode interrupt on falling edges 0 1 C MOS input mode interrupt on rising and falling edges 1 0 Push pull output mode 1 1 C MOS input mode interrupt on risin...

Page 94: ...es 0 1 C MOS input mode interrupt on rising edges and falling edges 1 0 Push pull output mode 1 1 C MOS input mode interrupt on rising edges 3 and 2 P2 1 INT6 Mode Selection Bits 0 0 C MOS input mode interrupt on falling edges 0 1 C MOS input mode interrupt on rising edges and falling edges 1 0 Push pull output mode 1 1 C MOS input mode interrupt on rising edges 1 and 0 P2 0 INT5 Mode Selection Bi...

Page 95: ...rupt INT9 Enable Bit 0 Disable interrupt 1 Enable interrupt 5 P2 5 External Interrupt INT9 Enable Bit 0 Disable interrupt 1 Enable interrupt 4 P2 4 External Interrupt INT9 Enable Bit 0 Disable interrupt 1 Enable interrupt 3 P2 3 External Interrupt INT8 Enable Bit 0 Disable interrupt 1 Enable interrupt 2 P2 2 External Interrupt INT7 Enable Bit 0 Disable interrupt 1 Enable interrupt 1 P2 1 External ...

Page 96: ...n read 4 P2 4 External Interrupt INT9 Pending Flag Bit 0 No P2 4 external interrupt pending when read 1 P2 4 external interrupt is pending when read 3 P2 3 External Interrupt INT8 Pending Flag Bit 0 No P2 3 external interrupt pending when read 1 P2 3 external interrupt is pending when read 2 P2 2 External Interrupt INT7 Pending Flag Bit 0 No P2 2 external interrupt pending when read 1 P2 2 externa...

Page 97: ...e pull up resistor 1 Enable pull up resistor 5 P2 5 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 4 P2 4 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 3 P2 3 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 2 P2 2 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 1 P...

Page 98: ...0CAP P3 3 T1CAP T2CAP P3 1 REM P3 2 T0CK 5 P3 1 Function Selection Bit 0 Normal I O selection 1 Alternative function enable REM T0CK 4 and 3 P3 1 Mode Selection Bits 0 0 Schmitt trigger input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 Schmitt trigger input with pull up resistor 2 Function Selection Bit for P3 0 P3 3 0 Normal I O selection 1 Alternative function enable P3 0 T0PWM...

Page 99: ... Pin Assignment of P3CON in 42 44 Pin Package P3CON Each Function Description and Assignment to P3 0 P3 3 B5 B4 B3 B2 B1 B0 P3 0 P3 1 P3 2 P3 3 0 x x 0 x x Normal I O Normal I O Normal Input Normal Input 0 x x 1 0 0 T0_CAP Normal I O Normal Input T1CAP Normal Input 0 x x 1 1 1 T0_CAP Normal I O Normal Input T1CAP Normal Input 0 x x 1 0 1 T0PWM Normal I O Normal Input T1CAP Normal Input 0 x x 1 1 0...

Page 100: ...input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 C MOS input with pull up mode 3 and 1 Not used for S3F80JB 0 Port 4 Control Register Selection Bit 0 P4CON Register selection 1 P4CONH P4CONL Register selection NOTE After CPU reset P3 4 and P3 5 will be Open drain output mode by the reset value of P345CON register at E1H Set1 Bank1 P345CON will be initialized as 50h to set P3 4 i...

Page 101: ...Selection Bit 0 Open drain output mode 1 Push pull output mode 5 P4 5 Mode Selection Bit 0 Open drain output mode 1 Push pull output mode 4 P4 4 Mode Selection Bit 0 Open drain output mode 1 Push pull output mode 3 P4 3 Mode Selection Bit 0 Open drain output mode 1 Push pull output mode 2 P4 2 Mode Selection Bit 0 Open drain output mode 1 Push pull output mode 1 P4 1 Mode Selection Bit 0 Open drai...

Page 102: ...input with pull up mode 5 and 4 P4 6 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 C MOS input with pull up mode 3 and 2 P4 5 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 C MOS input with pull up mode 1 and 0 P4 4 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull...

Page 103: ...input with pull up mode 5 and 4 P4 2 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 C MOS input with pull up mode 3 and 2 P4 1 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 C MOS input with pull up mode 1 and 0 P4 0 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull...

Page 104: ...ion Bits 0 0 0 0 Destination page 0 See Note 3 0 Source Register Page Selection Bits 0 0 0 0 Source page 0 See Note NOTE In the S3F80JB microcontroller a paged expansion of the internal register file is not implemented For this reason only page 0 settings are valid Register page pointer values for the source and destination register page are automatically set to 0000B following a hardware reset Th...

Page 105: ... to address C0H in register set 1 bank0 selecting the 8 byte working register slice C0H C7H 2 0 Not used for S3F80JB RP1 Register Pointer 1 D7H Set1 Bank0 Bit Identifier 7 6 5 4 3 2 1 0 Reset Value 1 1 0 0 1 Read Write R W R W R W R W R W Addressing Mode Register addressing mode only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 248 byte working regi...

Page 106: ...top Control Register FBH Set1 Bank0 Bit Identifier 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W Addressing Mode Register addressing mode only 7 0 Stop Control Register Enable Bits 1 0 1 0 0 1 0 1 Enable STOP Mode Other value Disable STOP Mode NOTES 1 To get into STOP mode stop control register must be enabled just before STOP instruction 2 When STOP mode is released stop ...

Page 107: ... Bit 4 0 Disable fast interrupt processing 1 Enable fast interrupt processing 0 Global Interrupt Enable Bit 5 0 Disable global interrupt processing 1 Enable global interrupt processing NOTES 1 Because an external interface is not implemented for the S3F80JB SYM 7 must always be 0 2 Although the SYM register is not used SYM 5 should always be 0 If you accidentally write a 1 to this bit during norma...

Page 108: ... 1 1 PWM mode Match and OVF interrupt can occur 3 Timer 0 Counter Clear Bit 0 No effect when write 1 Clear T0 counter T0CNT when write 2 Timer 0 Overflow Interrupt Enable Bit note 0 Disable T0 overflow interrupt 1 Enable T0 overflow interrupt 1 Timer 0 Match Capture Interrupt Enable Bit 0 Disable T0 match capture interrupt 1 Enable T0 match capture interrupt 0 Timer 0 Match Capture Interrupt Pendi...

Page 109: ... falling edges counter running OVF can occur 3 Timer 1 Counter Clear Bit 0 No effect when write 1 Clear T1 counter T1CNT when write 2 Timer 1 Overflow Interrupt Enable Bit note 0 Disable T1 overflow interrupt 1 Enable T1 overflow interrupt 1 Timer 1 Match Capture Interrupt Enable Bit 0 Disable T1 match capture interrupt 1 Enable T1 match capture interrupt 0 Timer 1 Match Capture Interrupt Pending ...

Page 110: ... falling edges counter running OVF can occur 3 Timer 2 Counter Clear Bit 0 No effect when write 1 Clear T2 counter T2CNT when write 2 Timer 2 Overflow Interrupt Enable Bit note 0 Disable T2 overflow interrupt 1 Enable T2 overflow interrupt 1 Timer 2 Match Capture Interrupt Enable Bit 0 Disable T2 match capture interrupt 1 Enable T2 match capture interrupt 0 Timer 2 Match Capture Interrupt Pending ...

Page 111: ... interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR register settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no ...

Page 112: ... 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level See Figure 5 1 Type 1 One level IRQn one vector V1 one source S1 Type 2 One level IRQn one vector V1 multiple sources S1 Sn Type 3 One level IRQn multiple vectors V1 Vn multiple sources S1 Sn Sn 1 Sn m In the S3F80JBmicrocontroller all three interrupt types are implemented Vectors Sources Levels S1 V1 S...

Page 113: ...es the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the pr...

Page 114: ...3 D2H D0H 2 1 0 P2 1 external interrupt P2 0 external interrupt E6H P0 3 external interrupt IRQ6 E4H P0 2 external interrupt 3 E2H E0H 2 1 0 P0 1 external interrupt P0 0 external interrupt IRQ5 D8H P2 7 external interrupt P2 6 external interrupt P2 5 external interrupt P2 4 external interrupt S W S W S W S W S W S W S W S W S W S W S W S W IRQ7 E8H P0 7 external interrupt P0 6 external interrupt P...

Page 115: ...s normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H Reset address can be changed by smart option Refer to Table 15 3 or Figure 2 2 0 Decimal 65 536 255 Smart Option Rom Cell 0000H 00FFH HEX FFFFH 64 Kbyte Internal Program Memory Flash Memory Interrupt Vector Are...

Page 116: ...2 external interrupt 2 226 E2H P0 1 external interrupt 1 224 E0H P0 0 external interrupt 0 216 D8H P2 7 external interrupt IRQ5 216 D8H P2 6 external interrupt 216 D8H P2 5 external interrupt 216 D8H P2 4 external interrupt 214 D6H P2 3 external interrupt IRQ4 3 212 D4H P2 2 external interrupt 2 210 D2H P2 1 external interrupt 1 208 D0H P2 0 external interrupt 0 NOTES 1 Interrupt priorities are id...

Page 117: ...riority register IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source The system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interru...

Page 118: ...ttings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing the part of your application program that handles the interrupt processing be sure to include the necessary register file address register pointer information Interrupt Request Register Read only IRQ0 IRQ7 Interrupts Interru...

Page 119: ...pt P0 4 external interrupt IRQ7 P0CONH P0INT P0PND E8H F1H F2H Bank0 P0 3 external interrupt P0 2 external interrupt P0 1 external interrupt P0 0 external interrupt IRQ6 P0CONL P0INT P0PND E9H F1H F2H Bank0 P2 7 external interrupt P2 6 external interrupt P2 5 external interrupt P2 4 external interrupt IRQ5 P2CONH P2INT P2PND ECH E5H E6H Bank0 P2 3 external interrupt P2 2 external interrupt P2 1 ex...

Page 120: ...initialization routine which follows a reset operation in order to enable interrupt processing Although you can manipulate SYM 0 directly to enable and disable interrupts during normal operation we recommend using the EI and DI instructions for this purpose System Mode Register SYM DEH Set 1 Bank 0 R W 7 4 3 2 1 0 MSB LSB Fast Interrupt Level Selection Bits 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 ...

Page 121: ...eared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1and Bank0 Bit values can be read and written by instructions using the register addressing mode NOTE Before IMR register is changed to any value all interrupts must be disable Using...

Page 122: ...these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 Group A IRQ0 IRQ1 Group B IRQ2 IRQ3 IRQ4 Group C IRQ5 IRQ6 IRQ7 IPR Group A IRQ1 A2 IRQ0 A1 IRQ5 C1 IRQ7 IPR Group C IRQ6 C21 C2 C22 IRQ2 B1 IRQ4 IPR Group B IRQ3 B21 B2 B22 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relativ...

Page 123: ...IRQ1 Subgroup B see note 0 IRQ3 IRQ4 1 IRQ3 IRQ4 Group C 0 IRQ5 IRQ6 IRQ7 1 IRQ6 IRQ7 IRQ5 Subgroup C 0 IRQ6 IRQ7 1 IRQ7 IRQ6 Group B 0 IRQ2 IRQ3 IRQ4 1 IRQ2 IRQ3 IRQ4 Group Priority 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Undefined B C A A B C B A C C A B C B A A C B Undefined D7 D4 D1 Figure 5 8 Interrupt Priority Register IPR ...

Page 124: ...ime using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however s...

Page 125: ...d and cannot therefore be read or written by application software In the S3F80JB interrupt structure the timer 0 overflow interrupt IRQ0 the timer 1 overflow interrupt IRQ1 the timer 2 overflow interrupt IRQ3 and the counter A interrupt IRQ2 belong to this category of interrupts whose pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type...

Page 126: ... 0 1 The interrupt level must be enabled IMR register unmask The interrupt level must have the highest priority if more than one level is currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register If all of the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The CPU then initiates an interrupt ...

Page 127: ...lue to the stack PUSH IMR 2 Load the IMR register with a new mask value that enables only the higher priority interrupt 3 Execute an EI instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR 5 Execu...

Page 128: ...he SYM register Fast Interrupt Service Routine When an interrupt occurs in the level selected for fast interrupt processing the following events occur 1 The contents of the instruction pointer and the PC are swapped 2 The FLAG register values are written to the FLAGS FLAGS prime register 3 The fast interrupt status bit in the FLAGS register is set 4 The interrupt is serviced 5 Assuming that the fa...

Page 129: ...d shift operations Data Types The SAM8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit Register Addressing To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working regis...

Page 130: ...oad external data memory and increment LDCI dst src Load program memory and increment LDEPD dst src Load external data memory with pre decrement LDCPD dst src Load program memory with pre decrement LDEPI dst src Load external data memory with pre increment LDCPI dst src Load program memory with pre increment LDW dst src Load word POP dst Pop from stack POPUD dst src Pop user stack decrementing POP...

Page 131: ...ry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ...

Page 132: ... Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset B...

Page 133: ...t RRC dst Rotate right through carry SRA dst Shift right arithmetic SWAP dst Swap nibbles CPU Control Instructions CCF Complement carry flag DI Disable interrupts EI Enable interrupts IDLE Enter Idle mode NOP No operation RCF Reset carry flag SB0 Set bank 0 SB1 Set bank 1 SCF Set carry flag SRP src Set register pointers SRP0 src Set register pointer 0 SRP1 src Set register pointer 1 STOP Enter Sto...

Page 134: ...reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then simultaneously two ...

Page 135: ...ns D Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and cannot be used as a test condition H Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtr...

Page 136: ...ogic one Set or cleared according to operation Value is unaffected x Value is undefined Table 6 3 Instruction Set Symbols Symbol Description dst Destination operand src Source operand Indirect register address prefix PC Program counter IP Instruction pointer FLAGS Flags register D5H RP Register pointer Immediate operand or register address prefix H Hexadecimal number suffix D Decimal number suffix...

Page 137: ...n number only Ir Indirect working register only Rn n 0 15 IR Indirect register or indirect working register Rn or reg reg 0 255 n 0 15 Irr Indirect working register pair only RRp p 0 2 14 IRR Indirect register pair or indirect working register pair RRp or reg reg 0 254 even only where p 0 2 14 X Indexed addressing mode reg Rn reg 0 255 n 0 15 XS Indexed short offset addressing mode addr RRp addr r...

Page 138: ...r1 Ir2 TCM R2 R1 TCM IR2 R1 TCM R1 IM BAND r0 Rb I 7 PUSH R2 PUSH IR2 TM r1 r2 TM r1 Ir2 TM R2 R1 TM IR2 R1 TM R1 IM BIT r1 b B 8 DECW RR1 DECW IR1 PUSHUD IR1 R2 PUSHUI IR1 R2 MULT R2 RR1 MULT IR2 RR1 MULT IM RR1 LD r1 x r2 B 9 RL R1 RL IR1 POPUD IR2 R1 POPUI IR2 R1 DIV R2 RR1 DIV IR2 RR1 DIV IM RR1 LD r2 x r1 L A INCW RR1 INCW IR1 CP r1 r2 CP r1 Ir2 CP R2 R1 CP IR2 R1 CP R1 IM LDC r1 Irr2 xL E B ...

Page 139: ...OWER NIBBLE HEX 8 9 A B C D E F U 0 LD r1 R2 LD r2 R1 DJNZ r1 RA JR cc RA LD r1 IM JP cc DA INC r1 NEXT P 1 ENTER P 2 EXIT E 3 WFI R 4 SB0 5 SB1 N 6 IDLE I 7 STOP B 8 DI B 9 EI L A RET E B IRET C RCF H D SCF E E CCF X F LD r1 R2 LD r2 R1 DJNZ r1 RA JR cc RA LD r1 IM JP cc DA INC r1 NOP ...

Page 140: ...10 note NZ Not zero Z 0 1101 PL Plus S 0 0101 MI Minus S 1 0100 OV Overflow V 1 1100 NOV No overflow V 0 0110 note EQ Equal Z 1 1110 note NE Not equal Z 0 1001 GE Greater than or equal S XOR V 0 0001 LT Less than S XOR V 1 1010 GT Greater than Z OR S XOR V 0 0010 LE Less than or equal Z OR S XOR V 1 1111 note UGE Unsigned greater than or equal C 0 0111 note ULT Unsigned less than C 1 1011 UGT Unsi...

Page 141: ...g The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time and addressing...

Page 142: ... both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Examples Given R1 10H R2 03H C ...

Page 143: ... sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if a carry from the low order nibble occurred Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 R R 6 05 R IR opc dst src 3 6 06 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH ADD R1 R2 R1 15H R2 03H ADD R1 R2 R1 1CH R2 ...

Page 144: ...se V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 R R 6 55 R IR opc dst src 3 6 56 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH AND R1 R2 R1 02H R2 03H AND R1 R2 R1 02H R2 03H AND 01H 02H Register 01H 01H register 02H 03H AND 01H 02H Register 01H 00H registe...

Page 145: ...mat Bytes Cycles Opcode Hex Addr Mode dst src opc dst b 0 src 3 6 67 r0 Rb opc src b 1 dst 3 6 67 Rb r0 NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H and register 01H 05H BAND R1 01H 1 R1 06H register 01H 05H BAND 01H 1 R1 Register 01H 05H ...

Page 146: ...cles Opcode Hex Addr Mode dst src opc dst b 0 src 3 6 17 r0 Rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H and register 01H 01H BCP R1 01H 1 R1 07H register 01H 01H If destination working register R1 contains the value 07H 00000111B and the source register ...

Page 147: ...Bytes Cycles Opcode Hex Addr Mode dst opc dst b 0 2 4 57 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITC R1 1 R1 05H If working register R1 contains the value 07H 00000111B the statement BITC R1 1 complements bit one of the destination and leaves the va...

Page 148: ...ormat Bytes Cycles Opcode Hex Addr Mode dst opc dst b 0 2 4 77 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITR R1 1 R1 05H If the value of working register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination register R1 leaving...

Page 149: ...Bytes Cycles Opcode Hex Addr Mode dst opc dst b 1 2 4 77 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITS R1 3 R1 0FH If working register R1 contains the value 07H 00000111B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leavi...

Page 150: ...he 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit Examples Given R1 07H and register 01H 03H BOR R1 01H 1 R1 07H register 01H 03H BOR 01H 2 R1 Register 01H 07H R1 07H In the first example destination working register R1 contains the value 07H 00000111B and source register 01H the value 03H 00000011B The...

Page 151: ...d Format Note 1 Bytes Cycles Opcode Hex Addr Mode dst src opc src b 0 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRF SKIP R1 3 PC jumps to SKIP location If working register R1 contains the value 07H 00000111B the statement BTJRF SKIP R1 3 te...

Page 152: ...ormat Note 1 Bytes Cycles Opcode Hex Addr Mode dst src opc src b 1 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 00000111B the statement BTJRT SKIP R1 1 tests bit one in the source reg...

Page 153: ...src opc dst b 0 src 3 6 27 r0 Rb opc src b 1 dst 3 6 27 Rb r0 NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H 00000111B and register 01H 03H 00000011B BXOR R1 01H 1 R1 06H register 01H 03H BXOR 01H 2 R1 Register 01H 07H R1 07H In the first ex...

Page 154: ...nstruction CALL RR0 SP 0000H 0000H 1AH 0001H 49H CALL 40H SP 0000H 0000H 1AH 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location 0000H The PC is then loaded with the value 3521H the address of the first instru...

Page 155: ...lag is changed to logic zero if C 0 the value of the carry flag is changed to logic one Flags C Complemented No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 EF Example Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register 0D5H changing its value from logic zero to logic one ...

Page 156: ...dst 2 4 B0 R 4 B1 IR Examples Given Register 00H 4FH register 01H 02H and register 02H 5EH CLR 00H Register 00H 00H CLR 01H Register 01H 02H register 02H 00H In Register R addressing mode the statement CLR 00H clears the destination register 00H value to 00H In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to 00H ...

Page 157: ...ormat Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 60 R 4 61 IR Examples Given R1 07H and register 07H 0F1H COM R1 R1 0F8H COM R1 R1 07H register 07H 0EH In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and vice versa leaving the value 0F8H 11111000B In the second...

Page 158: ...c dst 3 6 A4 R R 6 A5 R IR opc dst src 3 6 A6 R IM Examples 1 Given R1 02H and R2 03H CP R1 R2 Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S are 1 2 Given R1 ...

Page 159: ...rmat Bytes Cycles Opcode Hex Addr Mode dst src opc src dst RA 3 12 C2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Example Given R1 02H R2 03H and register 03H 02H CPIJE R1 R2 SKIP R2 04H PC jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H The statement CPIJ...

Page 160: ... Opcode Hex Addr Mode dst src opc src dst RA 3 12 D2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Example Given R1 02H R2 03H and register 03H 04H CPIJNER1 R2 SKIP R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value 03H and general register 03 the value 04H The statement CPIJNE R1...

Page 161: ...re DA Bits 4 7 Value Hex H Flag Before DA Bits 0 3 Value Hex Number Added to Byte Carry After DA 0 0 9 0 0 9 00 0 0 0 8 0 A F 06 0 0 0 9 1 0 3 06 0 ADD 0 A F 0 0 9 60 1 ADC 0 9 F 0 A F 66 1 0 A F 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 SUB 0 0 8 1 6 F FA 06 0 SBC 1 7 F 0 0 9 A0 60 1 1 6 F 1 6 F 9A 66 1 Flags C Set if there was a carry from the most signifi...

Page 162: ...27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic 0 0 0 1 0 1 0 1 15 0 0 1 0 0 1 1 1 27 0 0 1 1 1 1 0 0 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 42 Assuming the same values given above the s...

Page 163: ...leared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 00 R 4 01 IR Examples Given R1 03H and register 03H 10H DEC R1 R1 02H DEC R1 Register 03H 0FH In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements th...

Page 164: ... Opcode Hex Addr Mode dst opc dst 2 8 80 RR 8 81 IR Examples Given R0 12H R1 34H R2 30H register 30H 0FH and register 31H 21H DECW RR0 R0 12H R1 33H DECW R2 Register 30H 0FH register 31H 20H In the first example destination register R0 contains the value 12H and register R1 the value 34H The statement DECW RR0 addresses R0 and the following operand R1 as a 16 bit word and decrements the value of R...

Page 165: ...ive interrupt pending bits but the CPU will not service them while interrupt processing is disabled Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 8F Example Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pending and interrupt so...

Page 166: ...nt 1 cleared otherwise V Set if quotient is 28 or if divisor 0 cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Examples Given R0 10H R1 03H R2 40H register 40H 80H DIV RR0 R2 R0 03H R1 40H DIV RR0 R2 R0...

Page 167: ...ng used as a counter should be set at the one of location 0C0H to 0CFH with SRP SRP0 or SRP1 instruction Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst r opc dst 2 8 jump taken rA RA 8 no jump r 0 to F Example Given R1 02H and LOOP is the label of a relative address SRP 0C0H DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is use...

Page 168: ...nding bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the EI instruction Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 9F Example Given SYM 00H EI If the SYM register contains the value 00H that is if interrupts are currently disabled the statement EI sets the SYM register to 01H enabling all interrupts SYM...

Page 169: ...the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 1F Example The diagram below shows one example of how to use an ENTER statement 0050 IP 0022 SP 22 Data Address Data 0040 PC 40 41 42 43 Enter Address H Address L Address H Address Data 1F 01 10 Memory 0043 IP 0020 SP 20 21 22 IPH IPL D...

Page 170: ...is then loaded into the program counter and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 internal stack 2F 16 internal stack Example The diagram below shows one example of how to use an EXIT statement 0050 IP 0022 SP Address Data 0040 PC Address Data Memory 0052 IP 0022 SP Address Data 0060 PC Address Data Memory Stack Stack Befo...

Page 171: ...ock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc 1 4 6F Example The instruction IDLE stops the CPU clock but not the system clock ...

Page 172: ... dst dst opc 1 4 rE r r 0 to F opc dst 2 4 20 R 4 21 IR Examples Given R0 1BH register 00H 0CH and register 1BH 0FH INC R0 R0 1CH INC 00H Register 00H 0DH INC R0 R0 1BH register 01H 10H In the first example if destination working register R0 contains the value 1BH the statement INC R0 leaves the value 1CH in that same register The next example shows the effect an INC instruction has on register 00...

Page 173: ...ister 02H 0FH and register 03H 0FFH INCW RR0 R0 1AH R1 03H INCW R1 Register 02H 10H register 03H 00H In the first example the working register pair RR0 contains the value 1AH in register R0 and 02H in register R1 The statement INCW RR0 increments the 16 bit destination by one leaving the value 03H in register R1 In the second example the statement INCW R1 uses Indirect Register IR addressing mode ...

Page 174: ...ast Bytes Cycles Opcode Hex opc 1 6 BF Example In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped This causes the PC to jump to address 100H and the IP to keep the return address The last instruction in the service routine normally is a jump to I...

Page 175: ...byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 In the first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Examples Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL_W LABEL_W 1000H PC 1000H JP 00H PC 0120H The first example shows a conditional JP Assuming that the c...

Page 176: ...riginal value of the program counter is taken to be the address of the first instruction byte following the JR statement Flags No flags are affected Format 1 Bytes Cycles Opcode Hex Addr Mode dst cc opc dst 2 6 ccB RA cc 0 to F NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits Example Given The carry flag 1 and LABEL_X 1FF7H JR C LABEL_X...

Page 177: ...tents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src dst opc src 2 4 rC r IM 4 r8 r R src opc dst 2 4 r9 R r r 0 to F opc dst src 2 4 C7 r lr 4 D7 Ir r opc src dst 3 6 E4 R R 6 E5 R IR opc dst src 3 6 E6 R IM 6 D6 IR IM opc src dst 3 6 F5 IR R opc dst src x 3 6 87 r x r opc src dst x 3 6 97 x r r ...

Page 178: ...r 01H 20H LD 01H R0 Register 01H 01H R0 01H LD R1 R0 R1 20H R0 01H LD R0 R1 R0 01H R1 0AH register 01H 0AH LD 00H 01H Register 00H 20H register 01H 20H LD 02H 00H Register 02H 20H register 00H 01H LD 00H 0AH Register 00H 0AH LD 00H 10H Register 00H 01H register 01H 10H LD 00H 02H Register 00H 01H register 01H 02 register 02H 02H LD R0 LOOP R1 R0 0FFH R1 0AH LD LOOP R0 R1 Register 31H 0AH R0 01H R1...

Page 179: ... the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R0 06H and general register 00H 05H LDB R0 00H 2 R0 07H register 00H 05H LDB 00H 0 R0 R0 06H register 00H 04H In the first example destination working register R0 contains the value 06H and the source general register 00H the value 05H The statement LD R0 00...

Page 180: ...E7 r XS rr 4 opc src dst XS 3 12 F7 XS rr r 5 opc dst src XLL XLH 4 14 A7 r XL rr 6 opc src dst XLL XLH 4 14 B7 XL rr r 7 opc dst 0000 DAL DAH 4 14 A7 r DA 8 opc src 0000 DAL DAH 4 14 B7 DA r 9 opc dst 0001 DAL DAH 4 14 A7 r DA 10 opc src 0001 DAL DAH 4 14 B7 DA r NOTES 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 For formats 3 and 4 the destinati...

Page 181: ...ion 0105H 01H RR2 R0 6DH R2 01H R3 04H LDE R0 01H RR2 R0 contents of external data memory location 0105H 01H RR2 R0 7DH R2 01H R3 04H LDC note 01H RR2 R0 11H contents of R0 is loaded into program memory location 0105H 01H 0104H LDE 01H RR2 R0 11H contents of R0 is loaded into external data memory location 0105H 01H 0104H LDC R0 1000H RR2 R0 contents of program memory location 1104H 1000H 0104H R0 ...

Page 182: ...ed LDCD references program memory and LDED references external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 10 E2 r Irr Examples Given R6 10H R7 33H R8 12H program memory location 1033H 0CDH and external data memory location 1033H 0DDH LDCD R8 RR6 0C...

Page 183: ...fected LDCI refers to program memory and LDEI refers to external data memory The assembler makes Irr even for program memory and odd for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 10 E3 r Irr Examples Given R6 10H R7 33H R8 12H program memory locations 1033H 0CDH and 1034H 0C5H external data memory locations 1033H 0DDH and 1034H 0D5H LDCI...

Page 184: ...tion The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes Irr an even number for program memory and an odd number for external data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 2 14 F2 Irr r Examples Given R0 77H R6 30H and R7 00H LDCPD RR6 R0 RR6 RR6 1 77H contents o...

Page 185: ...cation The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 2 14 F3 Irr r Examples Given R0 7FH R6 21H and R7 0FFH LDCPI RR6 R0 RR6 RR6 1 7FH contents of R0 i...

Page 186: ... and register 03H 0FH LDW RR6 RR4 R6 06H R7 1CH R4 06H R5 1CH LDW 00H 02H Register 00H 03H register 01H 0FH register 02H 03H register 03H 0FH LDW RR2 R7 R2 03H R3 0FH LDW 04H 01H Register 04H 03H register 05H 0FH LDW RR6 1234H R6 12H R7 34H LDW 02H 0FEDH Register 02H 0FH register 03H 0EDH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H 03H...

Page 187: ...esult is a 1 cleared otherwise V Cleared D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Examples Given Register 00H 20H register 01H 03H register 02H 09H register 03H 06H MULT 00H 02H Register 00H 01H register 01H 20H register 02H 09H MULT 00H 01H Register 00H 00H register 01H 0C0H MULT 00H 30H Register 00H 06H register 0...

Page 188: ...am counter The instruction pointer is then incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 10 0F Example The following diagram shows one example of how to use the NEXT instruction Data 01 10 Before After 0045 IP Address Data 0130 PC 43 44 45 Address H Address L Address H Address Data Memory 130 Routine 0043 IP Address Data 0120 PC 43 44 45 Address H Address L Ad...

Page 189: ...ction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 FF Example When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ...

Page 190: ...rmat Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 R R 6 45 R IR opc dst src 3 6 46 R IM Examples Given R0 15H R1 2AH R2 01H register 00H 08H register 01H 37H and register 08H 8AH OR R0 R1 R0 3FH R1 2AH OR R0 R2 R0 37H R2 01H register 01H 37H OR 00H 01H Register 00H 3FH register 01H 37H OR 01H 00H Register 00H 08H register 01H 0BFH OR 00H 02H Registe...

Page 191: ...c dst 2 8 50 R 8 51 IR Examples Given Register 00H 01H register 01H 1BH SPH 0D8H 00H SPL 0D9H 0FBH and stack register 0FBH 55H POP 00H Register 00H 55H SP 00FCH POP 00H Register 00H 01H register 01H 55H SP 00FCH In the first example general register 00H contains the value 01H The statement POP 00H loads the contents of location 00FBH 55H into destination register 00H and then increments the stack ...

Page 192: ...cremented Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 8 92 R IR Example Given Register 00H 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00H Register 00H 41H register 02H 6FH register 42H 6FH If general register 00H contains the value 42H and register 42H the value 6FH the statement POPUD 02H 00H loads the contents of...

Page 193: ...nter is then incremented Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 8 93 R IR Example Given Register 00H 01H and register 01H 70H POPUI 02H 00H Register 00H 02H register 01H 70H register 02H 70H If general register 00H contains the value 01H and register 01H the value 70H the statement POPUI 02H 00H loads the value 70H into the destination general re...

Page 194: ...ternal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Examples Given Register 40H 4FH register 4FH 0AAH SPH 00H and SPL 00H PUSH 40H Register 40H 4FH stack register 0FFH 4FH SPH 0FFH SPL 0FFH PUSH 40H Register 40H 4FH register 4FH 0AAH stack register 0FFH 0AAH SPH 0FFH SPL 0FFH In the first example if the stack pointer contains the value 0000H and general register 40H the valu...

Page 195: ...ointer Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 3 8 82 IR R Example Given Register 00H 03H register 01H 05H and register 02H 1AH PUSHUD 00H 01H Register 00H 02H register 01H 05H register 02H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUD 00H 01H decrements the user stack pointer by one leaving the v...

Page 196: ...tack pointer Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 3 8 83 IR R Example Given Register 00H 03H register 01H 05H and register 04H 2AH PUSHUI 00H 01H Register 00H 04H register 01H 05H register 04H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving...

Page 197: ... Operation C 0 The carry flag is cleared to logic zero regardless of its previous value Flags C Cleared to 0 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 CF Example Given C 1 or 0 The instruction RCF clears the carry flag C to logic zero ...

Page 198: ...cuted is the one that is addressed by the new program counter value Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 8 internal stack AF 10 internal stack Example Given SP 00FCH SP 101AH and PC 1234 RET PC 101AH SP 00FEH The statement RET pops the contents of stack pointer location 00FCH 10H into the high byte of the program counter The stack pointer then pops the value in location...

Page 199: ... cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 90 R 4 91 IR Examples Given Register 00H 0AAH register 01H 02H and register 02H 17H RL 00H Register 00H 55H C 1 RL 01H Register 01H 02H register 02H 2EH C 0 In the first example if general re...

Page 200: ...tic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 10 R 4 11 IR Examples Given Register 00H 0AAH register 01H 02H and register 02H 17H C 0 RLC 00H Register 00H 54H C 1 RLC 01H Register 01H 02H register 02H 2EH C 0 In the first example if general register 00H has th...

Page 201: ...urred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 E0 R 4 E1 IR Examples Given Register 00H 31H register 01H 02H and register 02H 17H RR 00H Register 00H 98H C 1 RR 01H Register 01H 02H register 02H 8BH C 1 In the first example if general register 00H contains the value 31H 001100...

Page 202: ...ic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 C0 R 4 C1 IR Examples Given Register 00H 55H register 01H 02H register 02H 17H and C 0 RRC 00H Register 00H 2AH C 1 RRC 01H Register 01H 02H register 02H 0BH C 1 In the first example if general register 00H contains...

Page 203: ... the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 4F Example The statement SB0 clears FLAGS 0 to 0 selecting bank 0 register addressing ...

Page 204: ...gister FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area of the register file Bank 1 is not implemented in some KS88 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 5F Example The statement SB1 sets FLAGS 0 to 1 selecting bank 1 register addressing if implemented ...

Page 205: ...t is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 R R 6 35 R IR opc ds...

Page 206: ...ry Flag SCF Operation C 1 The carry flag C is set to logic one regardless of its previous value Flags C Set to 1 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 DF Example The statement SCF sets the carry flag to logic one ...

Page 207: ...t if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 D0 R 4 D1 IR Examples Given Register 00H 9AH register 02H 03H register 03H 0BCH and C 1 SRA 00H Register 00H 0CD C 0 SRA 02H Register 02H 03H register 03H 0DEH C 0 In the first example if general register 00H contains the value 9AH 10011010B the sta...

Page 208: ...write one or both of the register pointers RP0 and RP1 Bits 3 7 of the selected register pointer are written unless both register pointers are selected RP0 3 is then cleared to logic zero and RP1 3 is set to logic one Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode src opc src 2 4 31 IM Examples The statement SRP 40H sets register pointer 0 RP0 at location 0D6H to 40H and regi...

Page 209: ...peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc 1 4 7F Example The statement STO...

Page 210: ...wise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 R R 6 25 R IR opc dst src 3 6 26 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH SUB R1 R2 R1 0FH R2 03H...

Page 211: ... is set cleared otherwise V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 F0 R 4 F1 IR Examples Given Register 00H 3EH register 02H 03H and register 03H 0A4H SWAP 00H Register 00H 0E3H SWAP 02H Register 02H 03H register 03H 4AH In the first example if general register 00H contains the value 3EH 00111110B the statement SWAP 00H swaps the lower and uppe...

Page 212: ...ed to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 R R 6 65 R IR opc dst src 3 6 66 R IM Examples Given R0 0C7H R1 02H R2 12H register 00H 2BH register 01H 02H and register 02H 23H TCM R0 R1 R0 0C7H R1 02H Z 1 TCM R0 R1 R0 0C7H R1 02H register 02H 23H Z 0 TCM 00H 01H Register 00H 2BH register 01H 02H Z 1 TCM 00H 01...

Page 213: ...Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 R R 6 75 R IR opc dst src 3 6 76 R IM Examples Given R0 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H TM R0 R1 R0 0C7H R1 02H Z 0 TM R0 R1 R0 0C7H R1 02H register 02H 23H Z 0 TM 00H 01H Register 00H 2BH register 01H 02H Z 0 TM 00H 01H Register 00H 2BH register 01H 02H re...

Page 214: ...eased by an internal interrupt including a fast interrupt Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4n 3F n 1 2 3 Example The following sample program structure shows the sequence of operations that follow a WFI statement EI WFI Next instruction Main program Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed Enable global interrupt...

Page 215: ...fected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 B2 r r 6 B3 r lr opc src dst 3 6 B4 R R 6 B5 R IR opc dst src 3 6 B6 R IM Examples Given R0 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H XOR R0 R1 R0 0C5H R1 02H XOR R0 R1 R0 0E4H R1 02H register 02H 23H XOR 00H 01H Register 00H 29H register 01H 02H XOR 00H 01H Register 00H 08H registe...

Page 216: ...nect the external oscillator or clock source to the on chip clock circuit SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal or ceramic resonator oscillation source or an external clock Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fOSC divided by 1 2 8 or 16 Clock circuit control register CLKCON XIN XOUT C1 C2 Figur...

Page 217: ...er is automatically cleared In Idle mode the internal clock signal is gated away from the CPU but continues to be supplied to the interrupt structure timer 0 timer 1 counter A and so on Idle mode is released by a reset or by an interrupt external or internally generated NOTES 1 An external interrupt with an RC delay noise filter for the S3F80JB INT0 9 is fixed to release stop mode and wake up the ...

Page 218: ...are not used in S3F80JB After a reset the main oscillator is activated and the fOSC 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed to fOSC fOSC 2 fOSC 8 or fOSC 16 System Clock Control Register CLKCON D4H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB Not used Divide by selection bits for CPU clock frequency 00 fosc 16 01 fosc 8 10 fosc 2 1...

Page 219: ...verflow occurs Low Voltage Detect LVD When IPOR LVD Control Bit smart option bit 7 03FH is set to 1 and VDD is changed in condition for LVD operation regardless of operation mode reset occurs Although IPOR LVD Control Bit smart option bit 7 03FH is set to 0 if the operation mode is not in STOP mode reset signal is generated by LVD Internal Power ON Reset IPOR When IPOR LVD Control Bit smart option...

Page 220: ...ircuit while rising of VDD passes the level of VLVD 2 When IPOR LVD Control Bit of smart option is set to 0 and mode is in STOP Mode reset is generated by internal power on reset 3 Basic Timer over flow for watchdog timer See the chapter 11 Basic Timer and Timer 0 for more understanding 4 The reset pulse generation by transiting of reset pin nRESET from low level to high level on the condition tha...

Page 221: ...T9 SED R Circuit P0 P2 4 P2 7 STOP STOPCON IPOR LVD Control Bit 1 smart option bit 7 03FH Noise Filter Reset Pulse Generator nRESET Back up Mode Falling Edge Detector Enable Disable Disable Enable STOP STOPCON LVD IPOR Rising Edge Detector fosc BT WDT IPOR LVD Control Bit 1 smart option bit 7 03FH Falling Edgd RESET Figure 8 2 RESET Block Diagram of The S3F80JB ...

Page 222: ...VIH high input level of reset pin the reset pulse is generated on the condition of VDD VLVD WATCH DOG TIMER RESET The watchdog timer that can recover to normal operation from abnormal function is built in S3F80JB Watchdog timer generates a system reset signal if Basic Timer Counter BTCNT isn t cleared within a specific time by program For more understanding of the watchdog timer function please se...

Page 223: ...LVD and IPOR is selected as reset source by IPOR LVD Control Bit setting value of smart option in the stop mode If the setting value is 0 LVD can be disabled by STOP instruction Instead of LVD IPOR is enabled If the setting value is 1 LVD is enabled regardless of executing STOP instruction and IPOR is disabled INTERNAL POWER ON RESET The power on reset circuit is built on the S3F80JB product Durin...

Page 224: ... work of the reset pin LVD circuit and Internal POR The LVD circuit can be disabled and enabled in the stop mode by smart option If 3FH 7 is 1 LVD circuit is always enabled In this case the system reset by LVD circuit occurs in stop mode But if 3FH 7 is 0 the system reset by LVD circuit doesn t occur in stop mode Refer to page 2 3 relating to the smart option The rising time of VDD must be less th...

Page 225: ...led in the S3F80JB Va b NOTE Va is a schmitt trigger input signal of internal power on reset IPOR 0 85VDD Reset Pulse Width a b Figure 8 6 Reset Timing Diagram for The S3F80JB in STOP mode by IPOR EXTERNAL INTERRUPT RESET When IPOR LVD Control Bit smart option bit 7 03FH is set to 0 and chip is in stop mode if external interrupt is occurred by among the enabled external interrupt sources from INT0...

Page 226: ...eset No system reset Standstill VDD VLVD VDD VLVD Transition from Vreset VIL to VIH Vreset Reset pin System reset occurs Table 8 2 Reset Condition in STOP Mode When IPOR LVD Control Bit is 0 Condition Slope of VDD VDD The voltage level of reset pin Vreset Reset Source System Reset VDD VLVD Vreset VIH No system reset VDD VLVD Vreset VIH No system reset Rising up from 0 4 VDD VDD VLVD VDD VLVD Trans...

Page 227: ...control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slowest clock 1 16 because of the hardware reset value for the CLKCON register If all interrupts are masked in the IMR register a reset is the only way you can release Idle mode 2 Activate any enabled interrupt internal or external When you use an interrupt to...

Page 228: ... pin and LVD circuit The system reset of watchdog timer is not occurred in back up mode LVD Rising Edge Detector nRESET Back Up Mode Falling Edge Detector VD D VLVD Noise Filter Vreset VI L Figure 8 7 Block Diagram for Back up Mode Normal Operation Normal Operation Back up Mode Voltage V VLVD VDD Low level detect voltage Falling edge detected oscillation stop VDD VLVD Rising edge detected VDD VLVD...

Page 229: ...l register file is retained STOP mode can be released in one of two ways by a system reset or by an external interrupt After releasing from STOP mode the value of stop control register STOPCON is cleared automatically PROGRAMMING TIP To Enter STOP Mode This example shows how to enter the stop mode ORG 0000H Reset address JP T START ENTER_STOP LD STOPCON 0A5H STOP NOP NOP NOP RET ORG 0100H 3 JP T S...

Page 230: ...ng the program instruction stored in reset address Using LVD to Release STOP Mode When IPOR LVD Control Bit smart option bit 7 03FH is set to 1 and VDD is changed in condition for LVD operation in stop mode stop mode is released and reset occurs Using an External Interrupt to Release STOP Mode External interrupts can be used to release stop mode When IPOR LVD Control Bit smart option bit 7 03FH is...

Page 231: ...ate reset signal On the other hand when IPOR LVD Control Bit smart option bit 7 03FH is set to 1 S3F80JB is only released stop mode Reset doesn t occur When the falling edge of a pin on Port0 and P2 4 P2 7 is entered the chip is released from stop mode even though external interrupt is disabled Keeping the chip from entering abnormal stop mode This circuit detects the abnormal status by checking t...

Page 232: ...are disabled The watch dog function Basic Timer is enabled Port 0 2 and 3 are set to input mode and all pull up resistors are disabled for the I O port pin circuits Peripheral control and data register settings are disabled and reset to their default hardware values See Table 8 3 The program counter PC is loaded with the program reset address in the ROM 0100H When the programmed oscillation stabil...

Page 233: ... Flags Register FLAGS 213 D5H x x x x x x 0 0 Register Pointer 0 RP0 214 D6H 1 1 0 0 0 Register Pointer 1 RP1 215 D7H 1 1 0 0 1 Location D8H SPH is not mapped Stack Pointer Low Byte SPL 217 D9H x x x x x x x x Instruction Pointer High Byte IPH 218 DAH x x x x x x x x Instruction Pointer Low Byte IPL 219 DBH x x x x x x x x Interrupt Request Register Read Only IRQ 220 DCH 0 0 0 0 0 0 0 0 Interrupt ...

Page 234: ...er A Data Register Low Byte CADATAL 245 F5H 1 1 1 1 1 1 1 1 Timer 1 Counter Register High Byte T1CNTH 246 F6H 0 0 0 0 0 0 0 0 Timer 1 Counter Register Low Byte T1CNTL 247 F7H 0 0 0 0 0 0 0 0 Timer 1 Data Register High Byte T1DATAH 248 F8H 1 1 1 1 1 1 1 1 Timer 1 Data Register Low Byte T1DATAL 249 F9H 1 1 1 1 1 1 1 1 Timer 1 Control Register T1CON 250 FAH 0 0 0 0 0 0 0 0 STOP Control Register STOPC...

Page 235: ...de Register CMOD 233 E9H 0 0 0 0 0 0 0 0 Comparison Result Register CMPREG 234 EAH 0 0 0 0 0 0 0 0 Comparator Input Selection Register CMPSEL 235 EBH 0 0 0 0 Flash Memory Sector Address Register High Byte FMSECH 236 ECH 0 0 0 0 0 0 0 0 Flash Memory Sector Address Register Low byte FMSECL 237 EDH 0 0 0 0 0 0 0 0 Flash Memory User Programming Enable Register FMUSR 238 EEH 0 0 0 0 0 0 0 0 Flash Memor...

Page 236: ...P0 P2 4 2 7 X STOP Release and Continue O STOP Release and Reset Stop Mode SED R P2 0 2 3 X STOP X STOP NOTES 1 X means that a corresponding reset source don t generate reset signal O means that a corresponding reset source generates reset signal 2 Reset means that reset signal is generated and chip reset occurs 3 Continue means that it executes the next instruction continuously without ISR execut...

Page 237: ...gister to 00H Disable Pull up Resister No Connection for Pins P1CONH 55H P1CONL 55H P1 00H Port 2 Set Push pull Output mode Set P2 Data Register to 00H Disable Pull up resister No Connection for Pins P2CONH 0AAH P2CONL 0AAH P2 00H P2PUR 00H P3 0 3 1 Set Push pull Output mode Set P3 Data Register to 00H No Connection for Pins P3CON 11010010B P3 00H P3 2 P3 3 No connection P3 4 P3 5 Set Push pull Ou...

Page 238: ...All port becomes input mode but is blocked Disable all pull up resister except for P3 2 and P3 3 All I O port is floating status except P3 2 and P3 3 Disable all pull up resister except P3 2 and P3 3 All port is keep the previous status Output port data is not changed Control Register All control register and system register are initialized as list of Table 8 3 All control register and system regi...

Page 239: ...it programmable I O ports P0 P3 Three ports P0 P2 are 8 bit ports and P3 is a 2 bit port This gives a total of 26 I O pins Each port is bit programmable and can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special I O instructions are required For IR applications port0 port1 and port2 are usually configured t...

Page 240: ...using P2PUR register settings Also P2 4 P2 7 can be assigned individually as analog input pin for comparator P3 0 P3 1 P3 0 is configured input functions Input mode with or without pull up for normal input or T0CAP or output functions push pull or open drain output mode for normal output or T0PWM P3 1 is configured input functions Input mode with or without pull up for normal input or output funct...

Page 241: ...t in IR controller application Port 2 8 bit general purpose I O port Input or push pull output The P2 pins P2 0 P2 7 can be used as external interrupt inputs and have noise filters The P2INT register is used to enable disable interrupts and P2PND bits can be polled by software for interrupt pending control Pull up resistors can be assigned to individual P2 pins using P2PUR register settings Also P...

Page 242: ... R W Port 2 data register P2 226 E2H Set 1 Bank 0 R W Port 3 data register P3 227 E3H Set 1 Bank 0 R W Port 4 data register P4 228 E4H Set 1 Bank 0 R W Because port 3 is a 6 bit I O port the port 3 data register only contains values for P3 0 P3 5 The P3 register also contains a special carrier on off bit P3 7 See the port3 description for details All other I O ports are 8 bit Pn 4 Pn 3 7 6 5 4 3 2...

Page 243: ...g in the P3CON and P345CON registers P3 2 P3 3 are configured only input pins with pull up resistor Pn 4 Pn 3 Pull up Register Enable Registers PnPUR where n 0 2 Set 1 E7H EEH Bank0 R W 7 6 5 4 3 2 1 0 MSB LSB Pn 1 Pn 2 Pn 5 Pn 6 Pn 7 Pn 0 NOTES 1 Pull up resistors can be assigned to the port 3 pins P3 0 and P3 1 by making the appropriate setting the port 3 control register P3CON 2 Pull up resisto...

Page 244: ...t basic timer counter BTCNT FDH Set 1 Bank0 Read only Basic timer control register BTCON D3H Set 1 Bank0 R W TIMER 0 Timer 0 has three operating modes one of which you select using the appropriate T0CON setting Interval timer mode Capture input mode with a rising or falling edge trigger at the P3 0 pin PWM mode Timer 0 has the following functional components Clock frequency divider fOSC divided by...

Page 245: ...able the watch dog function you must write the signature code 1010B to the basic timer register control bits BTCON 7 BTCON 4 For improved reliability using the watch dog timer function is recommended in remote controllers and hand held product applications Basic Timer Control Register BTCON D3H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB Divider Clear Bit for BT and T0 0 No effect 1 Clear both divide...

Page 246: ...BTCNT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop mode has been released by an external interrupt In Stop mode whenever a reset or an external interrupt occurs the oscillator starts The BTCNT ...

Page 247: ...input clock frequency of fOSC 4096 and disables all timer 0 interrupts You can clear the timer 0 counter at any time during normal operation by writing a 1 to T0CON 3 The timer 0 overflow interrupt T0OVF is interrupt level IRQ0 and has the vector address FAH When a timer0 overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware To enable the t...

Page 248: ...OSC 4096 01 fOSC 256 10 fOSC 8 11 External clock NOTE Timer 0 Counter Clear Bit 0 No effect 1 Clear the timer 0 counter when write Timer 0 Operating Mode Selection Bits 00 Interval mode 01 Capture mode capture on rising edge counter running OVF can occur 10 Capture mode capture on falling edge counter running OVF can occur 11 PWM mode OVF interrupt can occur NOTE The external clock source of timer...

Page 249: ...rval Timer Mode In interval timer mode a match signal is generated when the counter value is identical to the value written to the T0 reference data register T0DATA The match signal generates a timer 0 match interrupt T0INT vector FCH and clears the counter If for example you write the value 10H to T0DATA 0BH to T0CON the counter will increment until it reaches 10H At this point the T0 interrupt r...

Page 250: ... interrupts are not typically used in PWM type applications Instead the pulse at the T0PWM pin is held to low level as long as the reference data value is less than or equal to the counter value and then the pulse is held to high level for as long as the data value is greater than the counter value One pulse width is equal to tCLK 256 See Figure 10 5 Match CTL T0CON 5 T0CON 4 P3 0 T0PWM IRQ0 T0OVF...

Page 251: ... 0 normal I O port P3 0 is selected Both kinds of timer 0 interrupts can be used in capture mode the timer 0 overflow interrupt is generated whenever a counter overflow occurs the timer 0 match capture interrupt is generated whenever the counter value is loaded into the T0 data register By reading the captured data value in T0DATA and assuming a specific value for the timer 0 clock frequency you c...

Page 252: ...operation the CPU is idle during the required oscillation stabilization interval until bit 4 of the basic timer counter overflows 2 It is available only in using internal mode 3 The external clock source is P3 1 T0CK in 32 pin package or P3 2 T0CK in 42 44 pin package Bits 7 6 Bits 3 2 Bit 1 RESET or STOP Timer 0 Overflow Bit 2 Timer 0 Match T0PWM Basic Timer Control Register Timer 0 Control Regis...

Page 253: ...T DI Disable all interrupts LD BTCON 0AAH Disable the watchdog timer LD CLKCON 18H Non divided clock CLR SYM Disable global and fast interrupts CLR SPL Stack pointer low byte 0 Stack area starts at 0FFH SRP 0C0H Set register pointer 0C0H EI Enable interrupts MAIN LD BTCON 52H Enable the watchdog timer Basic timer clock fOSC 4096 Clear basic timer counter NOP NOP JP T MAIN ...

Page 254: ...w interrupt VECTOR 00FCH T0INT Timer 0 match capture interrupt ORG 0100H RESET DI Disable all interrupts LD BTCON 0AAH Disable the watchdog timer LD CLKCON 18H Select non divided clock CLR SYM Disable global and fast interrupts CLR SPL Stack pointer low byte 0 Stack area starts at 0FFH LD T0CON 4BH Write 00100101B Input clock is fOSC 256 Interval timer mode Enable the timer 0 interrupt Disable the...

Page 255: ...AMMING TIP Programming Timer 0 Continued CP R0 32H 50 4 200 ms JR ULT NO_200MS_SET BITS R1 2 Bit setting 61 2H NO_200MS_SET LD T0CON 42H Clear pending bit POP RP0 Restore register pointer 0 value T0OVER IRET Return from interrupt service routine ...

Page 256: ...OSC divided by 4 8 or 16 Internal clock input from the counter A module counter A flip flop output You can use Timer 1 in three ways As a normal free run counter generating a Timer 1 overflow interrupt IRQ1 vector F4H at programmed time intervals To generate a Timer 1 match interrupt IRQ1 vector F6H when the 16 bit Timer 1 count value matches the 16 bit value written to the reference data register...

Page 257: ...32 pin package and P3 3 pin for 44 pin package The T1CON 5 and T1CON 4 bit pair setting is used to select the trigger condition for capture mode operation rising edges falling edges or both signal edges In capture mode program software can poll the Timer 1 match capture interrupt pending bit T1CON 0 to detect when a Timer 1 capture interrupt pending condition exists T1CON 0 1 When the interrupt re...

Page 258: ...l the Timer 1 match capture interrupt pending bit T1CON 0 to detect when a Timer 1 match interrupt pending condition exists T1CON 0 1 When the interrupt request is acknowledged by the CPU and the service routine starts the interrupt service routine for vector F6H must clear the interrupt pending condition by writing a 0 to T1CON 0 Match CTL T1CON 5 T1CON 4 P3 0 or P3 3 R Clear Pending T1CON 0 Inte...

Page 259: ...Buffer Register MUX IRQ1 Clear IRQ1 Match note NOTE Match signal is occurrd only in interval mode T1CON 7 6 T1CON 2 T1CON 3 Match Signal T1OVF Data Bus Timer 1 Data High Low Register CAOF T F F fOSC 16 fOSC 8 fOSC 4 R OVF T1CON 3 T1CON 5 4 T1CON 1 T1CON 0 Figure 11 3 Timer 1 Block Diagram ...

Page 260: ...1 Control Register T1CON FAH Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB Timer 1 Interrupt Pending Bit 0 No interrupt pending 0 Clear pending bit when write 1 Interrupt is pending Timer 1 Interrupt Match capture Enable Bit 0 Disable interrupt 1 Enable interrupt Timer 1 Overflow Interrupt Enable Bit 0 Disable overflow interrupt 1 Enable overflow interrupt Timer 1 Input Clock Selection Bits 00 fOSC 4 0...

Page 261: ... byte Register T1CNTL F7H Set 1 Bank 0 R 7 6 5 4 3 2 1 0 MSB LSB Reset Value 00H Timer 1 Data High byte Register T1DATAH F8H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB Reset Value FFH Timer 1 Data Low byte Register T1DATAL F9H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB Reset Value FFH Figure 11 5 Timer 1 Registers T1CNTH T1CNTL T1DATAH T1DATAL ...

Page 262: ... A control register CACON 8 bit down counter with auto reload function Two 8 bit reference data registers CADATAH and CADATAL Counter A has two functions As a normal interval timer generating a counter A interrupt IRQ2 vector ECH at programmed time intervals To supply a clock source to the 16 bit timer counter module Timer 1 for generating the Timer 1 overflow interrupt NOTE The CPU clock should b...

Page 263: ...f a borrow occurs the value of the CADATAH register is loaded into the 8 bit counter However if the next borrow occurs the value of the CADATAL register is loaded into the 8 bit counter Data Bus Counter A Data High Byte Register CACON 0 CAOF Repeat Control CLK DIV 1 DIV 2 DIV 4 DIV 8 CACON 2 fOSC Interrupt Control CACON 4 5 INT GEN To Other Block P3 1 REM CACON 3 CACON 6 7 Figure 12 1 Counter A Bl...

Page 264: ...1 T F F is high Counter A Mode Selection Bit 0 One shot mode 1 Repeating mode Counter A Start Stop Bit 0 Stop counter A 1 Start counter A Counter A Input Clock Selection Bits 00 fOSC 01 fOSC 2 10 fOSC 4 11 fOSC 8 Counter A Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt Counter A Interrupt Time Selection Bits 00 Elapsed time for low data value 01 Elapsed time for high data value 10 Ela...

Page 265: ...100H where Fx the selected clock When CAOF 1 tLOW CADATAH 2 1 Fx 0H CADATAH 100H where Fx the selected clock tHIGH CADATAL 2 1 Fx 0H CADATAL 100H where Fx the selected clock To make tLOW 24 us and tHIGH 15 us fOSC 4 MHz FX 4 MHz 4 1 MHz Method 1 When CAOF 0 tLOW 24 us CADATAL 2 FX CADATAL 2 x 1us CADATAL 22 tHIGH 15 us CADATAH 2 FX CADATAH 2 x 1us CADATAH 13 Method 2 When CAOF 1 tHIGH 15 us CADATA...

Page 266: ...F 0 CADATAL 00H CADATAH 00H CAOF 1 CADATAL 00H CADATAH 00H Low Low Counter A Clock 0H CAOF 1 CADATAL DEH CADATAH 1EH CAOF 0 CADATAL DEH CADATAH 1EH CAOF 1 CADATAL 7EH CADATAH 7EH CAOF 0 CADATAL 7EH CADATAH 7EH 100H 200H 20H E0H E0H 20H 80H 80H 80H 80H 100H 200H Figure 12 4 Counter A Output Flip Flop Waveforms in Repeat Mode ...

Page 267: ...ncy is 4 MHz 0 25 µs CADATAH 8 795 µs 0 25 µs 35 18 CADATAL 17 59 µs 0 25 µs 70 36 Set P3 1 C MOS push pull output and CAOF mode 44 pin package ORG 0100H Reset address START DI LD CADATAL 70 2 Set 17 5 ms LD CADATAH 35 2 Set 8 75 ms LD P3CON 11110010B Set P3 to C MOS push pull output Set P3 1 to REM output LD CACON 00000110B Clock Source Fosc Disable Counter A interrupt Select repeat mode for Coun...

Page 268: ... push pull output and CAOF mode 44 pin package ORG 0100H Reset address START DI LD CADATAH 160 2 Set 40 ms LD CADATAL 1 Set any value except 00H LD P3CON 11110010B Set P3 to C MOS push pull output Set P3 1 to REM output LD CACON 00000001B Clock Source Fosc Disable Counter A interrupt Select one shot mode for Counter A Stop Counter A operation Set Counter A Output Flip Flop CAOF high LD P3 80H Set ...

Page 269: ...OSC divided by 4 8 or 16 Internal clock input from the counter A module counter A flip flop output You can use Timer 2 in three ways As a normal free run counter generating a timer 2 overflow interrupt IRQ3 vector F0H at programmed time intervals To generate a timer 2 match interrupt IRQ3 vector F2H when the 16 bit timer 2 count value matches the 16 bit value written to the reference data register...

Page 270: ... pin package and P3 3 pin for 44 pin package The T2CON 5 and T2CON 4 bit pair setting is used to select the trigger condition for capture mode operation rising edges falling edges or both signal edges In capture mode program software can poll the timer 2 match capture interrupt pending bit T2CON 0 to detect when a timer 2 capture interrupt pending condition exists T2CON 0 1 When the interrupt requ...

Page 271: ...l the timer 2 match capture interrupt pending bit T2CON 0 to detect when a timer 2 match interrupt pending condition exists T2CON 0 1 When the interrupt request is acknowledged by the CPU and the service routine starts the interrupt service routine for vector F2H must clear the interrupt pending condition by writing a 0 to T2CON 0 Match CTL T2CON 5 T2CON 4 P3 0 or P3 3 R Clear Pending T2CON 0 Inte...

Page 272: ...Buffer Register MUX IRQ3 Clear IRQ3 Match note NOTE Match signal is occurrd only in interval mode T2CON 7 6 T2CON 2 T1CON 3 Match Signal T2OVF Data Bus Timer 2 Data High Low Register CAOF T F F fOSC 16 fOSC 8 fOSC 4 R OVF T2CON 3 T2CON 5 4 T2CON 1 T1CON 0 Figure 13 3 Timer 2 Block Diagram ...

Page 273: ...mer 2 Control Register T2CON E8H Set 1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB Timer 2 Interrupt Pending Bit 0 No interrupt pending 0 Clear pending bit when write 1 Interrupt is pending Timer 2 Interrupt Match capture Enable Bit 0 Disable interrupt 1 Enable interrupt Timer 2 Overflow Interrupt Enable Bit 0 Disable overflow interrupt 1 Enable overflow interrupt Timer 2 Input Clock Selection Bits 00 fOSC...

Page 274: ... Byte Register T2CNTL E5H Set 1 Bank 1 Read only 7 6 5 4 3 2 1 0 MSB LSB Reset Value 00H Timer 2 Data High Byte Register T2DATAH E6H Set 1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB Reset Value FFH Timer 2 Data Low Byte Register T2DATAL E7H Set 1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB Reset Value FFH Figure 13 5 Timer 2 Registers T2CNTH T2CNTL T2DATAH T2DATAL ...

Page 275: ...n external reference voltage is input at P2 7 the other P2 4 P2 5 and 2 6 pins are used for analog inputs When a conversion is completed the result is saved in the comparison result register CMPREG EAH Set1 Bank1 Read only The initial values of the CMPREG are undefined and the comparator operation is disabled by a reset The comparator module has the following components Comparator Internal referen...

Page 276: ... for digital input selecting If an analog input any INT doesn t occur 2 The comparison results of CIN0 CIN1 CIN2 and CIN3 are respectively stored in CMPREG0 CMPREG1 CMPREG2 and CMPREG3 CMOD 7 CMOD 5 Not used CMOD 3 CMOD 2 CMOD 1 CMOD 0 CMOD 6 CMPSEL_0 CMPSEL_1 CMPSEL_2 P2 4 CIN0 P2 5 CIN1 P2 6 CIN2 P2 7 CIN3 8 4 1 2R Figure 14 1 Comparator Block Diagram for The S3F80JB ...

Page 277: ...nal reference is calculated as follows If 1 Analog input voltage VREF 150 mV If 0 Analog input voltage VREF 150 mV To obtain a comparison result the data must be read out from the CMPREG register after VREF is updated by changing the CMOD value after a conversion time has elapsed Comparision Time CMPCLK x8 Comparision Start Comparision End Unknown 1 1 Unknown 0 Analog Input Voltage CIN0 3 Referenc...

Page 278: ... Control Bit 0 8x27 fosc 256us at 8MHz 1 8x24 fosc 32us at 8MHz 7 6 5 4 3 2 1 0 Figure 14 3 Comparator Mode Register CMOD 7 6 5 4 3 2 1 0 LSB MSB Comparator Input Selection Register CMPSEL EBH Set1 Bank 1 R W P2 7 Function Selection Bit 0 Normal I O selection 1 Alternative function enable CIN3 Not used for S3F80JB P2 6 Function Selection Bit 0 Normal I O selection 1 Alternative function enable CIN...

Page 279: ...S3F80JB COMPARATOR 14 5 Comparator Result Register CMPREG EBH Set1 Bank 1 R 7 6 5 4 3 2 1 0 MSB LSB Comparator Result Data Not used for S3F80JB Figure 14 5 Comparator Result Register CMPREG ...

Page 280: ...gram Mode Flash ROM Configuration The S3F80JB flash memory consists of 512sectors Each sector consists of 128bytes So the total size of flash memory is 512x128 bytes 64KB User can erase the flash memory by a sector unit at a time and write the data into the flash memory by a byte unit at a time 64Kbyte Internal flash memory Sector size 128 Bytes 10years data retention Fast programming Time Sector ...

Page 281: ...tection modes Hard lock protection Read protection The read protection mode is available only in tool program mode So in order to make a chip into read protection you need to select a read protection option when you write a program code to a chip in tool program mode by using a programming tool After read protect all data of flash memory read 00 This protection is released by chip erase execution ...

Page 282: ...or this area can be used as a normal program memory can be erased or programmed by LDC instruction by setting ISP disable bit 1 at the Smart Option Even if ISP sector is selected ISP sector can be erased or programmed in the tool program mode by serial programming tools The size of ISP sector can be varied by settings of smart option Refer to Figure 2 2 and Table 15 2 You can choose appropriate IS...

Page 283: ... select 7 6 5 4 3 2 1 0 MSB LSB ROM Address 003FH IPOR LVD Control Bit 0 IPOR enable LVD disable in the stop mode 1 IPOR disable LVD enable in the stop mode Not used Reserved ISP Reset Vector Address Selection Bits Note2 00 200H ISP Area size 256 bytes 01 300H ISP Area size 512 bytes 10 500H ISP Area size 1024 bytes 11 900H ISP Area size 2048 bytes ROM Address 003EH ISP Protection Size Selection B...

Page 284: ...t Option 003EH ISP Size Selection Bit Bit 2 Bit 1 Bit 0 Area of ISP Sector ISP Sector Size 1 x x 0 0 0 0 0 100H 1FFH 256 Bytes 256 Bytes 0 0 1 100H 2FFH 512 Bytes 512 Bytes 0 1 0 100H 4FFH 1024 Bytes 1024 Bytes 0 1 1 100H 8FFH 2048 Bytes 2048 Bytes NOTE The area of the ISP sector selected by smart option bit 3EH 2 3EH 0 can t be erased and programmed by LDC instruction in user program mode ISP RES...

Page 285: ...is activated when you set FMCON 0 to 1 If you write FMCON 0 to 1 for erasing CPU is stopped automatically for erasing time min 10ms After erasing time CPU is restarted automatically When you read or program a byte data from or into flash memory this bit is not needed to manipulate FLASH MEMORY USER PROGRAMMING ENABLE REGISTER FMUSR The FMUSR register is used for a safe operation of the flash memor...

Page 286: ...ddress which is located in the destination address to write data into FMSECH and FMSECL register If the next operation is also to write one byte data user should check whether next destination address is located in the same sector or not In case of other sectors user should load sector address to FMSECH and FMSECL Register according to the sector Refer to page 15 16 PROGRAMMING TIP Programming Fla...

Page 287: ...he sector to be located destination address should be erased first to program a new data one byte into flash memory Minimum 10ms delay time for the erase is required after setting sector address and triggering erase start bit FMCON 0 Sector erase is not supported in tool program modes MDS mode tool or programming tool Sector 0 9 128 byte x 10 Sector 511 128 byte Sector 510 128 byte Sector 127 128 ...

Page 288: ...emory Sector Address Register FMSECH and FMSECL FMUSR should be enabled just before starting sector erase operation And to erase a sector Flash Operation Start Bit of FMCON register is written from operation stop 0 to operation start 1 That bit will be cleared automatically just after the corresponding operation completed In other words when S3F80JB is in the condition that flash memory user progr...

Page 289: ...OP LD FMUSR 00H User program mode disable SB0 Case2 Erase flash memory space from Sector n to Sector n m Pre define the number of sector to erase LD SecNumH 00H Set sector number LD SecNumL 128 Selection the sector128 base address 4000H LD R6 01H Set the sector range m to erase LD R7 7DH into High byte R6 and Low byte R7 LD R2 SecNumH LD R3 SecNumL ERASE_LOOP CALL SECTOR_ERASE XOR P4 11111111B Dis...

Page 290: ...tor MULT RR14 80H The size of one sector is 128 bytes ADD R13 R14 BTJRF FLAGS 7 NOCARRY INC R12 NOCARRY LD R10 R13 LD R11 R15 ERASE_START SB1 LD FMUSR 0A5H User program mode enable LD FMSECH R10 Set sector address LD FMSECL R11 LD FMCON 10100001B Select erase mode enable Start sector erase ERASE_STOP LD FMUSR 00H User program mode disable SB0 RET ...

Page 291: ...1000XB 4 Set Flash Memory Sector Address Register FMSECH and FMSECL to the sector base address of destination address to write data 5 Load a transmission data into a working register 6 Load a flash memory upper address into upper register of pair working register 7 Load a flash memory lower address into lower register of pair working register 8 Load transmission data to flash memory location area ...

Page 292: ... User Program Mode Disable FMSECH High Address of Sector FMSECL Low Address of Sector R n High Address to Write R n 1 Low Address to Write R data 8 bit Data LDC RR n R data FMUSR 00H SB0 Mode Select FMCON 01010000B FMUSR 0A5H Select Bank0 Set Address and Data Finish 1 BYTE Writing Figure 15 9 Byte Program Flowchart in a User Program Mode ...

Page 293: ...ess to Write R n 1 Low Address to Write R data 8 bit Data LDC RR n R data Mode Select FMCON 01010000B FMUSR 0A5H Select Bank0 Set Address and Data INC R n 1 Same Sector R data New 8 bit Data FMUSR 00H SB0 Finish Writing NO YES NO YES NO YES NO YES User Program Mode Disable Update Data to Write Check Sector Check Address Increse Address Different Data Continuous address Write again Figure 15 10 Pro...

Page 294: ...B0 Case2 Programming in the same sector WR_INSECTOR RR10 Address copy R10 high address R11 low address LD R0 40H SB1 LD FMUSR 0A5H User program mode enable LD FMCON 01010000B Selection programming mode and Start programming LD FMSECH 40H Set the base address of sector located in target address to write data LD FMSECL 00H The sector 128 s base address is 4000H LD R9 33H Load data 33H to write LD R1...

Page 295: ...in target address to write data LD FMSECL 00H The sector 50 s base address is 1900H LD R9 55H Load data 55H to write LD R10 19H Load flash memory upper address into upper register of pair working register LD R11 40H Load flash memory lower address into lower register of pair working register CALL WR_BYTE WR_INSECTOR128 LD FMSECH 40H Set the base address of sector located in target address to write...

Page 296: ...ddress into lower register of pair working register 3 Load receive data from flash memory location area on LDC instruction by indirectly addressing mode PROGRAMMING TIP Reading LD R2 03H Load flash memory s upper address to upper register of pair working register LD R3 00H Load flash memory s lower address to lower register of pair working register LOOP LDC R0 RR2 Read data from flash memory locat...

Page 297: ...d Lock Protection is following that In tool mode the manufacturer of serial tool writer could support Hardware Protection Please refer to the manual of serial program writer tool provided by the manufacturer The program procedure in user program mode 1 Set Flash Memory User Programming Enable Register FMUSR to 10100101B 2 Set Flash Memory Control Register FMCON to 01100001B 3 Set Flash Memory User...

Page 298: ...D_FLAG detection LVD LVD circuit supplies two operating modes by one comparator back up mode input and system reset input The S3F80JB can enter the back up mode and generate the reset signal by the LVD level note1 detection using LVD circuit When LVD circuit detects the LVD level note1 in falling power S3F80JB enters the Back up mode Back up mode input automatically creates a chip stop state When ...

Page 299: ...selected 4MHz and LVD_FLAG voltage level is 1 9V 3 A term of LVD is a symbol of parameter that means Low Level Detect Voltage for Back Up Mode 4 A term of LVD_FLAG is a symbol of parameter that means Low Level Detect Voltage for Flag Indicator 5 In case of 8MHz operating frequency the voltage gap between LVD and LVD_FLAG is 150mV In case of 4MHz operating frequency the voltage gap between LVD and ...

Page 300: ...cts LVD_FLAG LVDCON 0 flag bit is set automatically The reset value of LVDCON is 00H Low Voltage Detect Control Register LVDCON E0H Set1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB LVD Indicator Flag Bit 0 VDD LVD_Flag Voltage 1 VDD LVD_Flag Voltage Not used for S3F80J9 S3F80J5 NOTE LVD_Flag Voltage is 2 3V at 8MHz and 2 15V at 4MHz Figure 16 2 Low Voltage Detect Control Register LVDCON ...

Page 301: ... Voltage Detect Circuit Data Retention Supply Voltage in Stop Mode Stop Mode Release Timing When Initiated by an External Interrupt Stop Mode Release Timing When Initiated by a Reset Stop Mode Release Timing When Initiated by a LVD Input Output Capacitance A C Electrical Characteristics Input Timing for External Interrupts Input Timing for Reset Oscillation Characteristics Oscillation Stabilizatio...

Page 302: ...TG 65 to 150 C HBM 2000 Electrostatic Discharge VESD MM 200 V Table 17 2 D C Electrical Characteristics TA 25 C to 85 C VDD 1 7 V to 3 6 V Parameter Symbol Conditions Min Typ Max Unit Operating Voltage VDD FOSC 4 MHz 1 7 3 6 V Input High Voltage VIH1 All input pins except VIH2 and VIH3 0 8 VDD VDD V VIH2 nRESET 0 85 VDD VDD VIH3 XIN VDD 0 3 VDD Input Low Voltage VIL1 All input pins except VIL2 and...

Page 303: ...d Port4 0 4 1 0 Input High Leakage Current ILIH1 VIN VDD All input pins except ILIH2 and XOUT 1 µA ILIH2 VIN VDD XIN 20 Input Low Leakage Current ILIL1 VIN 0 V All input pins except ILIL2 and XOUT 1 µA ILIL2 VIN 0 V XIN 20 Output High Leakage Current ILOH VOUT VDD All output pins 1 µA Output Low Leakage Current ILOL VOUT 0 V All output pins 1 µA RL1 VIN 0 V VDD 2 1 V TA 25 C Ports 0 4 40 90 150 kΩ...

Page 304: ...l up resistors or external output current loads Table 17 3 Characteristics of Low Voltage Detect Circuit TA 25 C to 85 C Parameter Symbol Conditions Min Typ Max Unit Hysteresys voltage of LVD Slew Rate of LVD V 100 300 mV Low level detect voltage for back up mode LVD 1 7 1 9 2 1 V Low level detect voltage for flag indicator LVD_FLAG 1 95 2 15 2 35 V NOTE The voltage gap between LVD and LVD FLAG is...

Page 305: ...5 C 85 C 25 C 25 C Figure 17 1 Typical Low Side Driver Sink Characteristics P3 1 only TYPICAL VOL vs IOL VDD 3 3V 0 00 0 20 0 40 0 60 0 80 1 00 0 10 20 30 40 IOL mA VOL V TYPICAL VOL VS VDD IOL 5mA 0 50 100 150 200 250 1 800V 2 400V 3 000V 3 600V VDD V VOL mV 85 C 25 C 25 C 85 C 25 C 25 C Figure 17 2 Typical Low Side Driver Sink Characteristics P3 0 and P2 0 2 3 NOTE Figure 17 1 and 17 2 are chara...

Page 306: ... 3 Typical Low Side Driver Sink Characteristics Port0 Port1 P2 4 2 7 P3 4 P3 5 and Port4 TYPICAL VDD VOH VDD 3 3V 0 00 0 20 0 40 0 60 0 80 1 00 1 20 0 5 10 15 20 25 IOH mA VDD VOH V TYPICAL VDD VOH VS VDD IOH 6mA 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 8V 2 3 2 8 3 3 3 8V VDD V VDD VOH V 85 C 25 C 25 C 85 C 25 C 25 C Figure 17 4 Typical High Side Driver Source Characteristics P3 1 only NOTE Figure 17 3 an...

Page 307: ...ical High Side Driver Source Characteristics P3 0 and P2 0 2 3 TYPICAL VDD VOH VDD 3 3V 0 00 0 20 0 40 0 60 0 80 1 00 1 20 0 1 2 3 4 5 6 IOH mA VDD VOH V TYPICAL VDD VOH VS VDD IOH 1mA 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 0 4 0 45 1 8V 2 3 2 8 3 3 3 8 VDD V VDD VOH V 85 C 25 C 25 C 85 C 25 C 25 C Figure 17 6 Typical High Side Driver Source Characteristics Port0 Port1 P2 4 2 7 P3 4 P3 5 and Port4 NOTE...

Page 308: ...al Operating Mode 0 2VDD 0 8VDD Figure 17 7 Stop Mode Release Timing When Initiated by an External Interrupt VDD Normal Operating Mode Stop Mode Oscillation Stabilization Time tWAIT Reset Occur Execution of STOP Instrction NOTE tWAIT is the same as 4096 x 16 x 1 fOSC nRESET 0 2VDD 0 85VDD Figure 17 8 Stop Mode Release Timing When Initiated by a Reset ...

Page 309: ...n Initiated by a LVD Table 17 5 Input Output Capacitance TA 25 C to 85 C Parameter Symbol Conditions Min Typ Max Unit Input Capacitance CIN 10 pF Output Capacitance COUT I O Capacitance CIO f 1 MHz VDD 0 V unmeasured pins are connected to VSS Table 17 6 A C Electrical Characteristics TA 25 C to 85 C Parameter Symbol Conditions Min Typ Max Unit Interrupt Input High Low Width tINTH tINTL P0 0 P0 7 P...

Page 310: ...ne CPU clock period Figure 17 10 Input Timing for External Interrupts Port 0 and Port 2 Normal Operating Mode Oscillation Stabilization Time Reset Occur VDD NOTE tWAIT is the same as 4096 x 16 x 1 fOSC tWAIT Normal Operating Mode Back up Mode Stop Mode nRESET Figure 17 11 Input Timing for Reset nRESET Pin ...

Page 311: ...cs TA 25 C to 85 C Oscillator Clock Circuit Conditions Min Typ Max Unit Crystal XIN C1 C2 XOUT CPU clock oscillation frequency 1 4 MHz Ceramic XIN C1 C2 XOUT CPU clock oscillation frequency 1 4 MHz External Clock XIN XOUT External Clock Open Pin XIN input frequency 1 4 MHz ...

Page 312: ... the minimum oscillator voltage range 10 ms External clock main system XIN input High and Low width tXH tXL 25 500 ns Oscillator stabilization wait time tWAIT when released by a reset 1 216 fOSC ms tWAIT when released by an interrupt 2 ms NOTES 1 fOSC is the oscillator frequency 2 The duration of the oscillation stabilization time tWAIT when it is released by an interrupt is determined by the sett...

Page 313: ... C to 85 C Parameter Symbol Conditions Min Typ Max Unit Flash Write Erase Voltage Fwe 1 95 3 6 V Flash Read Voltage Frv 1 7 3 6 V Programming Time 1 Ftp 32 60 µS Sector Erasing Time 2 Ftp1 10 20 mS Chip Erasing Time 3 Ftp2 50 100 mS Data Access Time FtRS VDD 2 0 V 250 nS Number of Writing Erasing FNwe 10 000 Times Data Retention Ftdr 10 Years NOTES 1 The programming time is the time during which o...

Page 314: ... Typical Low Side Driver Sink Characteristics Typical High Side Driver Source Characteristics Stop Mode Release Timing When Initiated by an External Interrupt Stop Mode Release Timing When Initiated by a Reset Stop Mode Release Timing When Initiated by a LVD Input Output Capacitance A C Electrical Characteristics Input Timing for External Interrupts Input Timing for Reset Comparator Electrical Cha...

Page 315: ... 65 to 150 C HBM 2000 Electrostatic discharge VESD MM 200 V Table 18 2 D C Electrical Characteristics TA 25 C to 85 C VDD 1 95 V to 3 6 V Parameter Symbol Conditions Min Typ Max Unit Operating Voltage VDD FOSC 8 MHz 1 95 3 6 V Input High Voltage VIH1 All input pins except VIH2 and VIH3 0 8 VDD VDD V VIH2 nRESET 0 85 VDD VDD VIH3 XIN VDD 0 3 VDD Input Low Voltage VIL1 All input pins except VIL2 and...

Page 316: ...nd Port4 0 4 1 0 Input High Leakage Current ILIH1 VIN VDD All input pins except ILIH2 and XOUT 1 µA ILIH2 VIN VDD XIN 20 Input Low Leakage Current ILIL1 VIN 0 V All input pins except ILIL2 and XOUT 1 µA ILIL2 VIN 0 V XIN 20 Output High Leakage Current ILOH VOUT VDD All output pins 1 µA Output Low Leakage Current ILOL VOUT 0 V All output pins 1 µA RL1 VIN 0 V VDD 2 35 V TA 25 C Ports 0 4 44 70 95 k...

Page 317: ...l up resistors or external output current loads Table 18 3 Characteristics of Low Voltage Detect Circuit TA 25 C to 85 C Parameter Symbol Conditions Min Typ Max Unit Hysteresis Voltage of LVD Slew Rate of LVD V 100 300 mV Low Level Detect Voltage For Back Up Mode LVD 1 95 2 15 2 35 V Low Level Detect Voltage For Flag Indicator LVD_FLAG 2 1 2 3 2 5 V NOTE The voltage gap between LVD and LVD FLAG is...

Page 318: ...5 C 85 C 25 C 25 C Figure 18 1 Typical Low Side Driver Sink Characteristics P3 1 only TYPICAL VOL vs IOL VDD 3 3V 0 00 0 20 0 40 0 60 0 80 1 00 0 10 20 30 40 IOL mA VOL V TYPICAL VOL VS VDD IOL 5mA 0 50 100 150 200 250 1 800V 2 400V 3 000V 3 600V VDD V VOL mV 85 C 25 C 25 C 85 C 25 C 25 C Figure 18 2 Typical Low Side Driver Sink Characteristics P3 0 and P2 0 2 3 NOTE Figure 18 1 and 18 2 are chara...

Page 319: ...ure 18 3 Typical Low Side Driver Sink Characteristics Port0 Port1 P2 4 2 7 P3 4 P3 5 and Port4 TYPICAL VDD VOH VDD 3 3V 0 00 0 20 0 40 0 60 0 80 1 00 1 20 0 5 10 15 20 25 IOH mA VDD VOH V TYPICAL VDD VOH VS VDD IOH 6mA 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 8V 2 3 2 8 3 3 3 8V VDD V VDD VOH V 85 C 25 C 25 C 85 C 25 C 25 C Figure 18 4 Typical High Side Driver Source Characteristics P3 1 only NOTE Figure 1...

Page 320: ...5 Typical High Side Driver Source Characteristics P3 0 and P2 0 2 3 TYPICAL VDD VOH VDD 3 3V 0 00 0 20 0 40 0 60 0 80 1 00 1 20 0 1 2 3 4 5 6 IOH mA VDD VOH V TYPICAL VDD VOH VS VDD IOH 1mA 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 0 4 0 45 1 8V 2 3 2 8 3 3 3 8 VDD V VDD VOH V 85 C 25 C 25 C 85 C 25 C 25 C Figure 18 6 Typical High Side Driver Source Characteristics Port0 Port1 P2 4 2 7 P3 4 P3 5 and Port4...

Page 321: ...al Operating Mode 0 2VDD 0 8VDD Figure 18 7 Stop Mode Release Timing When Initiated by an External Interrupt VDD Normal Operating Mode Stop Mode Oscillation Stabilization Time tWAIT Reset Occur Execution of STOP Instrction NOTE tWAIT is the same as 4096 x 16 x 1 fOSC nRESET 0 2VDD 0 85VDD Figure 18 8 Stop Mode Release Timing When Initiated by a Reset ...

Page 322: ...n Initiated by a LVD Table 18 5 Input Output Capacitance TA 25 C to 85 C Parameter Symbol Conditions Min Typ Max Unit Input Capacitance CIN 10 pF Output Capacitance COUT I O Capacitance CIO f 1 MHz VDD 0 V unmeasured pins are connected to VSS Table 18 6 A C Electrical Characteristics TA 25 C to 85 C Parameter Symbol Conditions Min Typ Max Unit Interrupt Input High Low Width tINTH tINTL P0 0 P0 7 P...

Page 323: ...ne CPU clock period Figure 18 10 Input Timing for External Interrupts Port 0 and Port 2 Normal Operating Mode Oscillation Stabilization Time Reset Occur VDD NOTE tWAIT is the same as 4096 x 16 x 1 fOSC tWAIT Normal Operating Mode Back up Mode Stop Mode nRESET Figure 18 11 Input Timing for Reset nRESET Pin ...

Page 324: ...REF 0 VDD V Input voltage Internal VCIN1 150 mV Accuracy External VCIN2 150 mV Input leakage current ICIN IREF 3 3 µA Table 18 8 Oscillation Characteristics TA 25 C to 85 C Oscillator Clock Circuit Conditions Min Typ Max Unit Crystal XIN C1 C2 XOUT CPU clock oscillation frequency 1 8 MHz Ceramic XIN C1 C2 XOUT CPU clock oscillation frequency 1 8 MHz External Clock XIN XOUT External Clock Open Pin ...

Page 325: ... the minimum oscillator voltage range 10 ms External clock main system XIN input High and Low width tXH tXL 25 500 ns Oscillator stabilization wait time tWAIT when released by a reset 1 216 fOSC ms tWAIT when released by an interrupt 2 ms NOTES 1 fOSC is the oscillator frequency 2 The duration of the oscillation stabilization time tWAIT when it is released by an interrupt is determined by the sett...

Page 326: ...ash ROM TA 25 C to 85 C Parameter Symbol Conditions Min Typ Max Unit Flash Erase Write Read Voltage Fewrv VDD 1 95 3 3 3 6 V Programming Time 1 Ftp 32 60 µS Sector Erasing Time 2 Ftp1 10 20 mS Chip Erasing Time 3 Ftp2 50 100 mS Data Access Time FtRS VDD 2 0 V 250 nS Number of Writing Erasing FNwe 10 000 Times Data Retention Ftdr 10 Years 1 The programming time is the time during which one byte 8 b...

Page 327: ...ELECTRICAL DATA 8MHz S3F80JB 18 14 NOTES ...

Page 328: ...urrently available in a 32 pin SOP and 44 pin QFP package 32 SOP 450A 20 30 MAX 19 90 0 20 17 16 0 8 0 25 0 10 0 05 11 43 8 34 0 20 0 90 0 20 0 05 MIN 2 00 0 10 2 20 MAX 0 10 MAX 1 27 NOTE Dimensions are in millimeters 12 00 0 30 32 1 0 43 0 40 0 10 Figure 19 1 32 Pin SOP Package Dimension ...

Page 329: ...QFP 1010B 44 NOTE Dimensions are in millimeters 10 00 0 20 13 20 0 30 10 00 0 20 13 20 0 30 1 0 35 0 10 0 05 0 80 0 10 MAX 0 80 0 20 0 05 MIN 2 05 0 10 2 30 MAX 0 15 0 10 0 05 0 8 0 15 MAX 1 00 Figure 19 2 44 Pin QFP Package Dimension ...

Page 330: ...9 and S3C8 microcontroller families Samsung also offers supporting software that includes debugger an assembler and a program for setting options TARGET BOARDS Target boards are available for all the S3C8 S3F8 series microcontrollers All the required target system cables and adapters are included on the device specific target board TB80JB is a specific target board for the S3F80JB development PROG...

Page 331: ...r 50 1 26 MAIN_MODE EVA_MODE JP1 J3 SCLK nRESET SDAT VDD VSS 1 1 JP10 U1 JP3 S1 JP6 JP8 JP11 JP5 VDDMCU VDD_3 3 VDD_REG Y1 TA SAM 8 JP1 5V 3V CABLEs For CONNECTION To Open ice500 CABLE To Connect Between Target Board And Open ice Connect Board VCC GND 4 Figure 20 1 TB80JB Target Board Configuration NOTE 1 S3E80JB should be supplied 3 3V So jumpers and switches in both OPENice i500 connect board an...

Page 332: ...ocon application board RESET Block RESET Push Switch Generation low active reset signal of 80JB EVA chip POWER Block VCC GND S nRESET LED Generation 3 3V with 5V power inserted from external power source or open ice recommend STOP IDLE Display IDLE STOP LED Indicate the status of STOP or IDLE FLASH Serial Writing J3 Signal for writing flash ROM in tool mode Don t use these in user mode MODE Select...

Page 333: ...g the regulator When debugging with Openice i500 JP11 don t need to be connect SW2 Smart option at address 3EH Dip switch for smart option These 1byte are mapped address 3EH for special function Refer to the page 2 3 SW3 Smart option at address 3FH Dip switch for smart option These 1byte are mapped address 3FH for special function Refer to the page 2 3 Y1 External clock source Connecting point for...

Page 334: ...NT4 P0 4 INT4 P0 3 INT3 P0 2 INT2 P0 1 INT1 P0 0 INT0 P4 4 P4 5 P4 6 P1 7 P1 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P1 4 N C N C N C 21 24 P4 7 P1 1 22 23 P2 6 INT9 CIN2 RESET 50 Pin DIP Connector VDD VSS XOUT XIN Figure 20 2 50 Pin Connector Pin Assignment for TB80JB Target Board 50 Pin DIP Connector Target System 50 Pin DI...

Page 335: ...e system with an OTP MTP programmer Series In Circuit Emulator OPENice i500 SMART Kit OTP MTP Programmer SPW 2 BlueChips Combi GW PRO2 Development Tools Suppliers Please contact our local sales offices on how to get MDS tools Or contact the 3rd party tool suppliers directly as shown below 8 bit In Circuit Emulator AIJI System OPENice i500 TEL 82 31 223 6611 FAX 82 331 223 6613 E mail openice aijis...

Page 336: ...rted just by adding device files or upgrading the software It is connected to host PC s serial port and controlled by the software AIJI System TEL 82 31 223 6611 FAX 82 31 223 6613 E mail openice aijisystem com URL http www aijisystem com GW PRO2 Gang Programmer for One time PROM device 8 devices programming at one time Fast programming speed 1 2Kbyte sec PC based control operation mode Full Funct...

Page 337: ...ode Not applicable See ROM Selection Form Customer sample Risk order See Risk Order Sheet Please answer the following questions For what kind of product will you be using this order New product Upgrade of an existing product Replacement of an existing product Other If you are replacing an existing product please indicate the former product name What are the main reasons you decided to use a Samsun...

Page 338: ...er Package Number of Pins ____________ Package Type _____________________ Intended Application ________________________________________________________________ Product Model Number ________________________________________________________________ Customer Risk Order Agreement We hereby request SEC to produce the above named product in the quantity stated below We believe our risk order product to b...

Page 339: ...FLASH APPLICATION NOTES S3F80JB Programming By Tool ...

Page 340: ...ect TEST pin to VDD S3F80JB supplies high voltage 12 5V by internal high voltage generation circuit NRESET nRESET 12 7 I Chip Initialization VDD VSS VDD VSS 5 32 6 1 Power supply pin for logic circuit VDD should be tied to 3 3 V during programming When writing or erasing using OTP MTP writer user must check the following Vdd Voltage The maximum operating voltage of S3F80JB is 3 6V Refer to the ele...

Page 341: ...S3F80JB 2 This is only an example for setting Vdd This is SPW2 which is one of OPT MTP Writers ...

Page 342: ...Important Note Subject Toggling phenomenon when serial writing programming on the S3F80JB ...

Page 343: ...perating mode it never be occurred 2 ANALYSIS OF PHENOMENON 2 1 FOR SERIAL PROGRAMMING MODE The S3F80JB 9 is needed to nRESET pin 0 GND TEST pin 1 VDD P1 4 1 7 When nRESET pin 0 GND TEST pin 1 VDD In the Figure 1 SDAT signal effects to outdis and data signal See 1 But because MUX level is unknown See 2 outdis and data is toggling This toggling phenomenon is only occurred to port1 4 1 5 1 6 1 7 on ...

Page 344: ...DD TEST pin 0 GND P1 4 1 7 When nRESET pin 1 VDD TEST pin 0 GND In the Figure 2 because TEST signal is low Logic level 0 outdis and data signal is same to MUX 0 signal So in normal operation port1 7 doesn t occurred to toggling phenomenon because of SDAT changing Timing Diagram of Figure1 Figure2 ...

Page 345: ...et to address port and data port for chip test So output disable signal of Port1 0 1 7 is toggling to Input Output mode When S3F80JB Port1 0 1 7 is used to address data port between Advan equipment and S3F80JB When Advan equipment sends data to S3F80JB port1 0 1 7 is input mode And when Advan equipment receives next address to S3F80JB port1 0 1 7 is output mode I e port1 0 1 7 is toggling to Input...

Page 346: ...the 28 SOP type doesn t have port1 4 1 7 port1 0 1 3 and port2 4 2 7 are used to address data port S3F80J9 is supported to 32 SOP and 28 SOP type 4 NOTICE When serial writing programming on S3F80JB port1 4 1 5 1 6 1 7 should be floating node or not connected to any device effected to damage by toggling ...

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