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Samsung S3C9454B, User Manual

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Samsung S3C9454B User Manual Download Page 39

ADDRESSING MODES 

 

S3C9454B/F9454B

 

3-4 

 

 

INDIRECT REGISTER ADDRESSING MODE (Continued) 

dst

OPCODE

PAIR

Point to

register pair

Example

Instruction

References

Program

Memory

Sample Instructions:

CALL

@RR2

JP

@RR2

Program Memory

Register File

Value used in

instruction

OPERAND

REGISTER

Program Memory

16-bit
address
points to
program
memory

 

Figure 3-4. Indirect Register Addressing to Program Memory 

Summary of Contents for S3C9454B

Page 1: ...S3C9454B F9454B 8 BIT CMOS MICROCONTROLLER USER S MANUAL Revision 1 ...

Page 2: ...intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless ag...

Page 3: ...e describes the S3C9454B F9454B interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part II Chapter 6 SAM88RCRI Instruction Set describes the features and conventions of the instruction set used for all S3C9 series microcontrollers Several summary tables are presented for orientation and reference Detailed de...

Page 4: ...gnments 1 4 Pin Descriptions 1 6 Pin Circuits 1 7 Chapter 2 Address Spaces Overview 2 1 Program Memory ROM 2 2 Register Architecture 2 5 Common Working Register Area C0H CFH 2 7 System Stack 2 8 Chapter 3 Addressing Modes Overview 3 1 Register Addressing Mode R 3 2 Indirect Register Addressing Mode IR 3 3 Indexed Addressing Mode X 3 7 Direct Address Mode DA 3 10 Relative Address Mode RA 3 12 Immed...

Page 5: ... 2 Interrupt Pending Function Types 5 2 Interrupt Priority 5 2 Interrupt Source Service Sequence 5 3 Interrupt Service Routines 5 3 Generating Interrupt Vector Addresses 5 3 S3C9454B F9454B Interrupt Structure 5 4 Chapter 6 SAM88RCRI Instruction Set Overview 6 1 Register Addressing 6 1 Addressing Modes 6 1 Flags Register FLAGS 6 4 Flag Descriptions 6 4 Instruction Set Notation 6 5 Condition Codes ...

Page 6: ...ESET and Power Down System Reset 8 1 Overview 8 1 Power Down Modes 8 3 Stop Mode 8 3 Idle Mode 8 3 Hardware Reset Values 8 4 Chapter 9 I O Ports Overview 9 1 Port Data Registers 9 2 Port 0 9 3 Port 1 9 7 Port 2 9 9 Chapter 10 Basic Timer and Timers Module Overview 10 1 Basic Timer BT 10 2 Basic Timer Control Register BTCON 10 2 Basic Timer Function Description 10 3 Timer 0 10 7 Timer 0 Control Reg...

Page 7: ...2 A D Converter Control Register ADCON 12 2 Internal Reference Voltage Levels 12 3 Conversion Timing 12 4 Internal A D Conversion Procedure 12 5 Chapter 13 Electrical Data Overview 13 1 Chapter 14 Mechanical Data Overview 14 1 Chapter 15 S3F9454B MTP Overview 15 1 Operating Mode Characteristics 15 3 Chapter 16 Development Tools Overview 16 1 SHINE 16 1 SAMA Assembler 16 1 SASM86 16 1 HEX2ROM 16 1 ...

Page 8: ...king Register Addressing 3 2 3 3 Indirect Register Addressing to Register File 3 3 3 4 Indirect Register Addressing to Program Memory 3 4 3 5 Indirect Working Register Addressing to Register File 3 5 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 3 7 Indexed Addressing to Register File 3 7 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 3 9 Indexed Ad...

Page 9: ... 2 Circuit Diagram 9 9 9 9 Port 2 Control Register P2CONH High Byte 9 10 9 10 Port 2 Control Register P2CONL Low Byte 9 11 10 1 Basic Timer Control Register BTCON 10 2 10 2 Oscillation Stabilization Time on RESET 10 4 10 3 Oscillation Stabilization Time on STOP Mode Release 10 5 10 4 Timer 0 Control Registers T0CON 10 7 10 5 Simplified Timer 0 Function Diagram Interval Timer Mode 10 8 10 6 Timer 0...

Page 10: ...sions 14 1 14 2 20 SOP 375 Package Dimensions 14 2 14 3 20 SSOP 225 Package Dimensions 14 3 14 4 16 DIP 300A Package Dimensions 14 4 14 5 16 SOP BD300 SG Package Dimensions 14 5 14 6 16 SSOP BD44 Package Dimensions 14 6 15 1 Pin Assignment Diagram 20 Pin Package 15 1 15 2 Pin Assignment Diagram 16 Pin Package 15 2 16 1 SMDS2 or SK 1000 Product Configuration 16 2 16 2 TB9454B Target Board Configura...

Page 11: ...ters 11 2 11 2 PWM output stretch Values for Extension Data Register PWMDATA 1 0 11 3 13 1 Absolute Maximum Ratings 13 2 13 2 DC Electrical Characteristics 13 3 13 3 AC Electrical Characteristics 13 4 13 4 Oscillator Characteristics 13 5 13 5 Oscillation Stabilization Time 13 5 13 6 Data Retention Supply Voltage in Stop Mode 13 7 13 7 A D Converter Electrical Characteristics 13 8 13 8 LVR Circuit ...

Page 12: ...a 2 7 Standard Stack Operations Using PUSH and POP 2 9 Chapter 8 RESET and Power Down Sample S3C9454B F9454B Initialization Routine 8 6 Chapter 10 Basic Timer and Timer 0 Configuring the Basic Timer 10 6 Configuring Timer 0 Interval Mode 10 11 Chapter 11 8 Bit PWM Programming the PWM Module to Sample Specifications 11 7 Chapter 12 A D Converter Configuring A D Converter 12 6 ...

Page 13: ... FLAGS System Flags Register 4 8 P0CONH Port 0 Control Register High Byte 4 9 P0CONL Port 0 Control Register Low Byte 4 10 P0PND Port 0 Interrupt Pending Register 4 11 P1CON Port 1 Control Register 4 12 P2CONH Port 2 Control Register High Byte 4 13 P2CONL Port 2 Control Register Low Byte 4 14 PWMCON PWM Control Register 4 15 STOPCON STOP Mode Control Register 4 16 SYM System Mode Register 4 16 T0C...

Page 14: ...Complement Carry Flag 6 15 CLR Clear 6 16 COM Complement 6 17 CP Compare 6 18 DEC Decrement 6 19 DI Disable Interrupts 6 20 EI Enable Interrupts 6 21 IDLE Idle Operation 6 22 INC Increment 6 23 IRET Interrupt Return 6 24 JP Jump 6 25 JR Jump Relative 6 26 LD Load 6 27 LD Load 6 28 LDC LDE Load Memory 6 29 LDC LDE Load Memory 6 30 LDCD LDED Load Memory and Decrement 6 31 LDCI LDEI Load Memory and I...

Page 15: ...5 PUSH Push To Stack 6 36 RCF Reset Carry Flag 6 37 RET Return 6 38 RL Rotate Left 6 39 RLC Rotate Left Through Carry 6 40 RR Rotate Right 6 41 RRC Rotate Right Through Carry 6 42 SBC Subtract With Carry 6 43 SCF Set Carry Flag 6 44 SRA Shift Right Arithmetic 6 45 STOP Stop Operation 6 46 SUB Subtract 6 47 TCM Test Complement Under Mask 6 48 TM Test Under Mask 6 49 XOR Logical Exclusive OR 6 50 ...

Page 16: ...rsatile general purpose microcontroller that is ideal for use in a wide range of electronics applications requiring simple timer counter PWM In addition the S3C9454B F9454 s advanced CMOS technology provides for low power consumption and wide operating voltage range Using the SAM88RCRI design approach the following peripherals were integrated with the SAM88RCRI core Three configurable I O ports 18...

Page 17: ...ree I O ports Max 18 pins Bit programmable ports 8 bit High speed PWM 8 bit PWM 1 ch Max 156 kHz 6 bit base 2 bit extension Built in Reset Circuit Low voltage detector for safe Reset Timer Counters One 8 bit basic timer for watchdog function One 8 bit timer counter with time interval modes A D Converter Nine analog input pins MAX 10 bit conversion resolution Oscillation Frequency 1 MHz to 10 MHz e...

Page 18: ...O and Interrupt Control 4 KB ROM 208 Byte Register File Timer 0 ADC PWM XIN XOUT OSC Basic Timer ADC0 ADC8 P0 6 PWM Port 0 Port 2 Port 1 P0 0 ADC0 INT0 P0 1 ADC1 INT1 P0 2 ADC2 P0 7 ADC7 P1 0 P1 1 P1 2 P2 0 T0 P2 1 P2 6 NOTE P1 2 is used as input only Figure 1 1 Block Diagram ...

Page 19: ...OP 225 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 VSS XIN P1 0 XOUT P1 1 nRESET P1 2 P2 0 T0 P2 1 P2 2 P2 3 P2 4 P2 5 VDD P0 0 ADC0 INT0 P0 1 ADC1 INT1 P0 2 ADC2 P0 3 ADC3 P0 4 ADC4 P0 5 ADC5 P0 6 ADC6 PWM P0 7 ADC7 P2 6 ADC8 CLO Figure 1 2 Pin Assignment Diagram 20 Pin DIP SOP SSOP Package ...

Page 20: ...OP BD300 SG 16 SSOP BD44 VDD P0 0 ADC0 INT0 P0 1 ADC1 INT1 P0 2 ADC2 P0 3 ADC3 P0 4 ADC4 P0 5 ADC5 P0 6 ADC6 PWM 16 15 14 13 12 11 10 9 VSS XIN P1 0 XOUT P1 1 nRESET P1 2 P2 0 T0 P2 1 P2 2 P2 3 1 2 3 4 5 6 7 8 Figure 1 3 Pin Assignment Diagram 16 Pin DIP SOP SSOP Package ...

Page 21: ...pen drain output Pull up resistors or pull down resistors are assignable by software E 2 XIN XOUT P1 2 I Schmitt trigger input port B RESET P2 0 P2 6 I O Bit programmable I O port for Schmitt trigger input or push pull open drain output Pull up resistors are assignable by software E E 1 ADC8 CLO T0 XIN XOUT Crystal Ceramic or RC oscillator signal for system clock P1 0 P1 1 nRESET I Internal LVR or...

Page 22: ... VDD IN N channel P channel Figure 1 5 Pin Circuit Type A IN Figure 1 6 Pin Circuit Type B VDD Out Output DIsable Data Figure 1 7 Pin Circuit Type C I O Output Disable Data Circuit Type C Pull up Enable VDD Digital Input Figure 1 8 Pin Circuit Type D ...

Page 23: ...t Enable ADC Output Disable Input Mode Data M U X Alternative Output P2 x P2CONH P2CONL N CH Figure 1 9 Pin Circuit Type E VDD I O Digital Input P CH VDD Pull up enable Output Disable Input Mode Data M U X Alternative Output P0 x P0CONH N CH Analog Input Enable ADC Interrupt Input Figure 1 10 Pin Circuit Type E 1 ...

Page 24: ...S3C9454B F9454B PRODUCT OVERVIEW 1 9 VDD I O XIN XOUT VDD Open drain Enable Output Disable Input Mode P1 x Digital Input Pull up enable Pull down enable Figure 1 11 Pin Circuit Type E 2 ...

Page 25: ...PRODUCT OVERVIEW S3C9454B F9454B 1 10 NOTES ...

Page 26: ...register bus carries addresses and data between the CPU and the internal register file The S3C9454B F9454B have 4 Kbytes of mask programmable on chip program memory which is configured as the Internal ROM mode all of the 4 Kbyte internal program memory is used The S3C9454B F9454B microcontroller has 208 general purpose registers in its internal register file Twenty six bytes in the register file a...

Page 27: ...001H are interrupt vector address Unused locations 0002H 00FFH except 3CH 3DH 3EH 3FH can be used as normal program memory 3CH 3DH 3EH 3FH is used smart option ROM cell The program Reset address in the ROM is 0100H 4 095 1000H 0100H 60 4 Kbyte Program Memory Area Interrupt Vector 64 256 0040H 003CH 0000H Decimal HEX Program Start 0002H 0001H 2 1 0 Smart option ROM cell Figure 2 1 Program Memory Ad...

Page 28: ... 2 1 0 MSB LSB Must be initialized to 00H ROM Address 003EH 7 6 5 4 3 2 1 0 MSB LSB LVR enable disable bit 0 Disable 1 Enable LVR level selection bits 11001 2 3 V 10010 3 0 V 01100 3 9 V Not used ROM Address 003FH 7 6 5 4 3 2 1 0 MSB LSB Oscillator selection bits 00 External crystal ceramic oscillator 01 External RC 10 Internal RC 0 5 MHz in VDD 5 V 11 Internal RC 3 2 MHz in VDD 5 V Not used NOTES...

Page 29: ... Address ORG 0000H Vector 00H INT_9454 S3C9454B F9454B has only one interrupt vector Smart Option Setting ORG 003CH DB 00H 003CH must be initialized to 0 DB 00H 003DH must be initialized to 0 DB 0E7H 003EH enable LVR 2 3 V DB 03H 003FH Internal RC 3 2 MHz in VDD 5 V Reset ORG 0100H RESET DI ...

Page 30: ...controllers the addressable area of the internal register file is further expanded by additional register pages at the general purpose register space 00H BFH page0 This register file expansion is not implemented in the S3C9454B F9454B however The specific register types and the area in bytes that they occupy in the internal register file are summarized in Table 2 1 Table 2 1 Register Type Summary ...

Page 31: ...2 6 FFH C0H BFH 00H 192 Bytes 64 Bytes of Common Area D0H CFH E0H DFH Working Registers System Control Registers Peripheral Control Registers General Purpose Register File and Stack Area Figure 2 3 Internal Register File Organization ...

Page 32: ...ea Registers are addressed either as a single 8 bit register or as a paired 16 bit register In 16 bit register pairs the address of the first 8 bit register is always an even number and the address of the next register is an odd number The most significant byte of the 16 bit data is always stored in the even numbered register the least significant byte is always stored in the next 1 odd numbered r...

Page 33: ...ays decremented before a push operation and incremented after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 5 Stack contents after a call instruction Stack contents after an interrupt Top of stack Flags PCH PCL PCL PCH Top of stack Low Address High Address Figure 2 5 Stack Operations Stack Pointer SP Register location D9H ...

Page 34: ...nal register file using PUSH and POP instructions LD SP 0C0H SP C0H Normally the SP is set to C0H by the initialization routine PUSH SYM Stack address 0BFH SYM PUSH R15 Stack address 0BEH R15 PUSH 20H Stack address 0BDH 20H PUSH R3 Stack address 0BCH R3 POP R3 R3 Stack address 0BCH POP 20H 20H Stack address 0BDH POP R15 R15 Stack address 0BEH POP SYM SYM Stack address 0BFH ...

Page 35: ...ADDRESS SPACES S3C9454B F9454B 2 10 NOTES ...

Page 36: ... to determine the location of the data operand The operands specified in SAM88RCRI instructions may be condition codes immediate data or a location in the register file program memory or data memory The SAM88RCRI instruction set supports six explicit addressing modes Not all of these addressing modes are available for each instruction The addressing modes and their symbols are as follows Register ...

Page 37: ...er File Address Point to one register in register file One Operand Instruction Example Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Program Memory Register File Figure 3 1 Register Addressing dst OPCODE 4 Bit Working Register Point to the working register 1 of 8 Two Operand Instruction Example Sample Instruction ADD R1 R2 Where R1 and R2 are registers in the cur...

Page 38: ...e see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location 8 Bit Register File Address One Operand Instruction Example dst Address of operand used by instruction OPCODE ADDRESS Point to one register in register file Sample Instruction RL SHIFT Where SHIFT is the label of an 8...

Page 39: ...PAIR Point to register pair Example Instruction References Program Memory Sample Instructions CALL RR2 JP RR2 Program Memory Register File Value used in instruction OPERAND REGISTER Program Memory 16 bit address points to program memory Figure 3 4 Indirect Register Addressing to Program Memory ...

Page 40: ...Continued dst OPCODE OPERAND 4 Bit Working Register Address Point to the working register 1 of 16 Sample Instruction OR R6 R2 Program Memory Register File src 4 LSBs Value used in instruction OPERAND CFH C0H Figure 3 5 Indirect Working Register Addressing to Register File ...

Page 41: ... LDE RR4 R8 External data memory access Program Memory Register File src Value used in instruction OPERAND Example instruction references either program memory or data memory Program Memory or Data Memory Next 3 Bits Point to working register pair 1 of 8 LSB Selects Register Pair 16 Bit address points to program memory or data memory CFH C0H Figure 3 6 Indirect Working Register Addressing to Progr...

Page 42: ...contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to the base address see Figure 3 9 The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions suppor...

Page 43: ...Address Sample Instructions LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed NEXT 3 Bits Register Pair src 8 Bit 16 Bit Program Memory or Data memory OPERAND Value used in instruction 16 Bit Register File Figure 3 8 Indexed Addressing to Program or Data Memory with ...

Page 44: ...DC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed NEXT 3 Bits Register Pair 16 Bit 16 Bit Program Memory or Datamemory OPERAND Value used in instruction 16 Bit Register File OPCODE XLH OFFSET XLL OFFSET dst src Figure 3 9 Indexed Addressing to Program or Data Me...

Page 45: ...mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H Identical operation to LDC example except that external program memory is accessed dst src OPCODE Program Memory 0 or 1 Lower Address Byte LSB Selec...

Page 46: ...ogram Memory Upper Address Byte Program Memory Address Used Lower Address Byte Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Next OPCODE Figure 3 11 Direct Addressing for Call and Jump Instructions ...

Page 47: ...ions that support RA addressing is JR OPCODE Program Memory Displacement Program Memory Address Used Sample Instructions JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Next OPCODE Signed Displacement Value Current Instruction Current PC Value Figure 3 12 Relative Addressing IMMEDIATE MODE IM In Immediate IM addressing mode the operand value used in the instruction is the value suppl...

Page 48: ...ile You can also use them as a quick reference source when writing application programs System and peripheral registers are summarized in Table 4 1 Figure 4 1 illustrates the important features of the standard register description format Control register descriptions are arranged in alphabetical order according to register mnemonic More information about control registers is presented in the conte...

Page 49: ...D4H R W 0 0 0 System flags register FLAGS D5H R W x x x x Locations D6H D8H are not mapped Stack pointer register SP D9H R W x x x x x x x x Location DAH is not mapped MDS special register MDSREG DBH R W 0 0 0 0 0 0 0 0 Basic timer control register BTCON DCH R W 0 0 0 0 0 0 0 0 Basic timer counter BTCNT DDH R 0 0 0 0 0 0 0 0 Test mode control register FTSTCON DEH W 0 0 0 0 0 0 System mode register...

Page 50: ...nding register P0PND E8H R W 0 0 0 0 Port 1 control register P1CON E9H R W 0 0 0 0 0 0 Port 2 control register High byte P2CONH EAH R W 0 0 0 0 0 0 0 Port 2 control register Low byte P2CONL EBH R W 0 0 0 0 0 0 0 0 Locations ECH F1H are not mapped PWM data register PWMDATA F2H R W 0 0 0 0 0 0 0 0 PWM control register PWMCON F3H R W 0 0 0 0 0 0 0 STOP control register STOPCON F4H R W 0 0 0 0 0 0 0 0...

Page 51: ...d to the register name for bit addressing D5H Register address hexadecimal Register name Register ID Name of individual bit or related bits x R W x R W x R W x R W 0 R W x R W 0 R W x R W Carry Flag C 0 Operation dose not generate a carry or borrow condition 1 Operation generates carry out or borrow into high order bit7 Zero Flag 0 Operation result is a non zero value 1 Operation result is zero Si...

Page 52: ... P2 6 1 0 0 1 Connected with GND internally 1 0 1 0 Connected with GND internally 1 0 1 1 Connected with GND internally 1 1 0 0 Connected with GND internally 1 1 0 1 Connected with GND internally 1 1 1 0 Connected with GND internally 1 1 1 1 Connected with GND internally 3 End of Conversion Status Bit 0 A D conversion is in progress 1 A D conversion complete 2 1 Clock Source Selection Bit note 0 0...

Page 53: ...function Others Enable watchdog timer function 3 2 Basic Timer Input Clock Selection Code 0 0 fOSC 4096 0 1 fOSC 1024 1 0 fOSC 128 1 1 Invalid setting 1 Basic Timer 8 Bit Counter Clear Bit 0 No effect 1 Clear the basic timer counter value 0 Basic Timer Divider Clear Bit 0 No effect 1 Clear both dividers NOTE When you write a 1 to BTCON 0 or BTCON 1 the basic timer counter or basic timer divider is...

Page 54: ... Wake up Function Enable Bit 0 Enable IRQ for main system oscillator wake up function 1 Disable IRQ for main system oscillator wake up function 6 5 Not used for S3C9454B F9454B 4 3 Divided by Selection Bits for CPU Clock frequency 0 0 Divide by 16 fOSC 16 0 1 Divide by 8 fOSC 8 1 0 Divide by 2 fOSC 2 1 1 Non divided clock fOSC 2 0 Not used for S3C9454B F9454B ...

Page 55: ... carry or borrow condition 1 Operation generates a carry out or borrow into high order bit 7 6 Zero Flag Z 0 Operation result is a non zero value 1 Operation result is zero 5 Sign Flag S 0 Operation generates a positive number MSB 0 1 Operation generates a negative number MSB 1 4 Overflow Flag V 0 Operation result is 127 or 128 1 Operation result is 127 or 128 3 0 Not used for S3C9454B F9454B ...

Page 56: ...off 5 4 Port 0 P0 6 ADC6 PWM Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Alternative function PWM output 1 0 Push pull output 1 1 A D converter input ADC6 Schmitt trigger input off 3 2 Port 0 P0 5 ADC5 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 A D converter input ADC5 Schmitt trigger input off 1 0 Port 0 P0 4 ...

Page 57: ...trigger input 0 1 Schmitt trigger input pull up enable 1 0 Push pull output 1 1 A D converter input ADC2 Schmitt trigger input off 3 2 Port 0 P0 1 ADC1 INT1 Configuration Bits 0 0 Schmitt trigger input falling edge interrupt input 0 1 Schmitt trigger input pull up enable falling edge interrupt input 1 0 Push pull output 1 1 A D converter input ADC1 Schmitt trigger input off 1 0 Port 0 P0 0 ADC0 IN...

Page 58: ...e 1 INT1 falling edge interrupt enable 2 Port 0 1 ADC1 INT1 Interrupt Pending Bit 0 No interrupt pending when read 0 Pending bit clear when write 1 Interrupt is pending when read 1 No effect when write 1 Port 0 0 ADC0 INT0 Interrupt Enable Bit 0 INT0 falling edge interrupt disable 1 INT0 falling edge interrupt enable 0 Port 0 0 ADC0 INT0 Interrupt Pending Bit 0 No interrupt pending when read 0 Pen...

Page 59: ...Configure P1 0 as a push pull output 1 Configure P1 0 as a n channel open drain output 5 4 Not used for S3C9454B F9454B 3 2 Port 1 P1 1 Interrupt Pending Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input pull up enable 1 0 Output 1 1 Schmitt trigger input pull down enable 1 0 Port 1 P1 0 Configuration Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input pull up enable 1 0 Output 1 1 Sch...

Page 60: ...trigger input 0 1 x ADC input 1 0 0 Push pull output 1 0 1 Open drain output pull up enable 1 1 0 Open drain output 1 1 1 Alternative function CLO output 3 2 Port 2 2 5 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 Open drain output 1 0 Port 2 2 4 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1...

Page 61: ... input 1 0 Push pull output 1 1 Open drain output 5 4 Port 2 P2 2 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 Open drain output 3 2 Port 2 P2 1 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 Open drain output 1 0 Port 2 P2 0 Configuration Bits 0 0 Schmitt trigger input...

Page 62: ...p counter overflow 1 Reload from 6 bit up counter overflow 3 PWM Counter Clear Bit 0 No effect 1 Clear the PWM counter when write 2 PWM Counter Enable Bit 0 Stop counter 1 Start Resume countering 1 PWM Overflow Interrupt Enable Bit 8 Bit Overflow 0 Disable interrupt 1 Enable interrupt 0 PWM Overflow Interrupt Pending Bit 0 No interrupt pending when read 0 Clear pending bit when write 1 Interrupt i...

Page 63: ...tion NOTE When STOPCON register is not 0A5H value if you use STOP instruction PC is changed to reset address SYM System Mode Register DFH Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W 7 3 Not used for S3C9454B F9454B 3 Global Interrupt Enable Bit 0 Disable all interrupts 1 Enable all interrupt 2 0 Page Select Bits 0 0 0 Page 0 0 0 1 Page 1 Not used for S3C9454B F945...

Page 64: ...r Bit 0 No effect 1 Clear the timer 0 counter when write 2 Not used for the S3C9454B F9454B 1 Timer 0 Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt 0 Timer 0 Interrupt Pending Bit Capture or match interrupt 0 No interrupt pending when read 0 Clear pending bit when write 1 Interrupt is pending when read 1 No effect when write NOTES 1 T0CON 3 is not auto cleared You must pay attention ...

Page 65: ...CONTROL REGISTERS S3C9454B F9454B 4 18 NOTES ...

Page 66: ... interrupt has only one vector address 0000H 0001H 2 The numbern of Sn value is expandable S1 S2 S3 Sn Figure 5 1 S3F9 Series Interrupt Type INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can be controlled in two ways either globally or by specific interrupt level and source The system level control points in the interrupt structure are therefore Global interrupt enable and disable by EI...

Page 67: ...d that you use the EI and DI instructions for this purpose INTERRUPT PENDING FUNCTION TYPES When the interrupt service routine has executed the application program s service routine must clear the appropriate pending bit before the return from interrupt subroutine IRET occurs INTERRUPT PRIORITY Because there is not a interrupt priority register in SAM88RCRI the order of service is determined by a ...

Page 68: ...ssing sequence 1 Reset clear to 0 the global interrupt enable bit in the SYM register DI SYM 3 0 to disable all subsequent interrupts 2 Save the program counter and status flags to stack 3 Branch to the interrupt vector to fetch the service routine s address 4 Pass control to the interrupt service routine When the interrupt service routine is completed an Interrupt Return instruction IRET occurs T...

Page 69: ...upt sources PWM overflow Timer 0 match P0 0 external interrupt P0 1 external interrupt Vector Pending Bits Enable Disable Source T0CON 0 SYM 2 EI DI PWMCON 0 P0PND 0 P0PND 2 T0CON 1 PWMCON 1 P0PND 1 P0PND 3 Timer 0 Match PWM Overflow P0 0 External Interrupt P0 1 External Interrupt 0000H 0001H Figure 5 3 S3C9454B F9454B Interrupt Structure ...

Page 70: ...rations complete the powerful data manipulation capabilities of the SAM88RCRI instruction set REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 13 bit program memory or data memory addresses For detailed information about register addressing please refer to Chapt...

Page 71: ...st src Load external data memory and decrement LDCI dst src Load program memory and increment LDEI dst src Load external data memory and increment POP dst Pop from stack PUSH src Push to stack Arithmetic Instructions ADC dst src Add with carry ADD dst src Add CP dst src Compare DEC dst Decrement INC dst Increment SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src L...

Page 72: ... condition code RET Return Bit Manipulation Instructions TCM dst src Test complement under mask TM dst src Test under mask Rotate and Shift Instructions RL dst Rotate left RLC dst Rotate left through carry RR dst Rotate right RRC dst Rotate right through carry SRA dst Shift right arithmetic CPU Control Instructions CCF Complement carry flag DI Disable interrupts EI Enable interrupts IDLE Enter Idl...

Page 73: ...g S Overflow flag V Not mapped Figure 6 1 System Flags Register FLAGS FLAG DESCRIPTIONS 030303Overflow Flag FLAGS 4 V The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is also cleared to 0 following logic operations Sign Flag FLAGS 5 S Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of t...

Page 74: ... 1 Set to logic one Set or cleared according to operation Value is unaffected x Value is undefined Table 6 3 Instruction Set Symbols Symbol Description dst Destination operand src Source operand Indirect register address prefix PC Program counter FLAGS Flags register D5H Immediate operand or register address prefix H Hexadecimal number suffix D Decimal number suffix B Binary number suffix opc Opco...

Page 75: ...t register or indirect working register Rn or reg reg 0 255 n 0 15 Irr Indirect working register pair only RRp p 0 2 14 IRR Indirect register pair or indirect working register pair RRp or reg reg 0 254 even only where p 0 2 14 X Indexed addressing mode reg Rn reg 0 255 n 0 15 XS Indexed short offset addressing mode addr RRp addr range 128 to 127 where p 0 2 14 XL Indexed long offset addressing mod...

Page 76: ... R1 OR R1 IM 5 POP R1 POP IR1 AND r1 r2 AND r1 Ir2 AND R2 R1 AND IR2 R1 AND R1 IM N 6 COM R1 COM IR1 TCM r1 r2 TCM r1 Ir2 TCM R2 R1 TCM IR2 R1 TCM R1 IM I 7 PUSH R2 PUSH IR2 TM r1 r2 TM r1 Ir2 TM R2 R1 TM IR2 R1 TM R1 IM B 8 LD r1 x r2 B 9 RL R1 RL IR1 LD r2 x r1 L A CP r1 r2 CP r1 Ir2 CP R2 R1 CP IR2 R1 CP R1 IM LDC r1 Irr2 xL E B CLR R1 CLR IR1 XOR r1 r2 XOR r1 Ir2 XOR R2 R1 XOR IR2 R1 XOR R1 IM...

Page 77: ... Reference Continued OPCODE MAP LOWER NIBBLE HEX 8 9 A B C D E F U 0 LD r1 R2 LD r2 R1 JR cc RA LD r1 IM JP cc DA INC r1 P 1 P 2 E 3 R 4 5 N 6 IDLE I 7 STOP B 8 DI B 9 EI L A RET E B IRET C RCF H D SCF E E CCF X F LD r1 R2 LD r2 R1 JR cc RA LD r1 IM JP cc DA INC r1 NOP ...

Page 78: ...Zero Z 1 1110 1 NZ Not zero Z 0 1101 PL Plus S 0 0101 MI Minus S 1 0100 OV Overflow V 1 1100 NOV No overflow V 0 0110 1 EQ Equal Z 1 1110 1 NE Not equal Z 0 1001 GE Greater than or equal S XOR V 0 0001 LT Less than S XOR V 1 1010 GT Greater than Z OR S XOR V 0 0010 LE Less than or equal Z OR S XOR V 1 1111 1 UGE Unsigned greater than or equal C 0 0111 1 ULT Unsigned less than C 1 1011 UGT Unsigned...

Page 79: ... referencing The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time and...

Page 80: ...t is negative cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Examples Given R1 10H R2 03H C flag 1 register 01H 20H register 02H 03H and register 03H 0...

Page 81: ...urred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 R R 6 05 R IR opc dst src 3 6 06 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH ADD R1 R2 R1 15H R2 03H ADD R1 R2 R1 1CH R2 03H ADD 01H 02H Register 01H...

Page 82: ...is set cleared otherwise V Always cleared to 0 Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 R R 6 55 R IR opc dst src 3 6 56 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH AND R1 R2 R1 02H R2 03H AND R1 R2 R1 02H R2 03H AND 01H 02H Register 01H 01H register 02H 03H AND 01H 02H Register 01H 00H register 02...

Page 83: ...RR Examples Given R0 15H R1 21H PC 1A47H and SP 0B2H CALL 1521H SP 0B0H Memory locations 00H 1AH 01H 4AH where 4AH is the address that follows the instruction CALL RR0 SP 0B0H 00H 1AH 01H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0B2H the statement CALL 1521H pushes the current PC value onto the top of the stack The stack pointer now po...

Page 84: ...e carry flag is changed to logic zero if C 0 the value of the carry flag is changed to logic one Flags C Complemented No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 EF Example Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register 0D5H changing its value from logic zero to logic one ...

Page 85: ... dst opc dst 2 4 B0 R 4 B1 IR Examples Given Register 00H 4FH register 01H 02H and register 02H 5EH CLR 00H Register 00H 00H CLR 01H Register 01H 02H register 02H 00H In Register R addressing mode the statement CLR 00H clears the destination register 00H value to 00H In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to 00H ...

Page 86: ...t Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 60 R 4 61 IR Examples Given R1 07H and register 07H 0F1H COM R1 R1 0F8H COM R1 R1 07H register 07H 0EH In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and vice versa leaving the value 0F8H 11111000B In the second exa...

Page 87: ... Addr Mode dst src opc dst src 2 4 A2 r r 6 A3 r lr opc src dst 3 6 A4 R R 6 A5 R IR opc dst src 3 6 A6 R IM Examples 1 Given R1 02H and R2 03H CP R1 R2 Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occur...

Page 88: ... dst value is 128 80H and result value is 127 7FH cleared otherwise Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 00 R 4 01 IR Examples Given R1 03H and register 03H 10H DEC R1 R1 02H DEC R1 Register 03H 0FH In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the state...

Page 89: ...terrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 8F Example Given SYM 04H DI If the value of the SYM register is 04H the statement DI leaves the new value 00H in the register and clears SYM 2 to 0 disabling interrupt processing ...

Page 90: ...as set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the EI instruction Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 9F Example Given SYM 00H EI If the SYM register contains the value 00H that is if interrupts are currently disabled the statement EI sets the SYM register to 04H enabling all interrupts SYM 2 is the e...

Page 91: ... clock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc 1 4 6F Example The instruction IDLE NOP NOP NOP stops the CPU clock but not the system clock ...

Page 92: ...s Opcode Hex Addr Mode dst dst opc 1 4 rE r r 0 to F opc dst 2 4 20 R 4 21 IR Examples Given R0 1BH register 00H 0CH and register 1BH 0FH INC R0 R0 1CH INC 00H Register 00H 0DH INC R0 R0 1BH register 01H 10H In the first example if destination working register R0 contains the value 1BH the statement INC R0 leaves the value 1CH in that same register The next example shows the effect an INC instruct...

Page 93: ... 1 This instruction is used at the end of an interrupt service routine It restores the flag register and the program counter It also re enables global interrupts Flags All flags are restored to their original settings that is the settings before the interrupt occurred Format IRET Normal Bytes Cycles Opcode Hex opc 1 10 BF 12 ...

Page 94: ... 1 The 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 In the first byte of the three byte instruction format conditional jump the condition code and the op code are both four bits Examples Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL_W LABEL_W 1000H PC 1000H JP 00H PC 0120H The first example shows a conditional JP Assuming ...

Page 95: ...d the original value of the program counter is taken to be the address of the first instruction byte following the JR statement Flags No flags are affected Format note Bytes Cycles Opcode Hex Addr Mode dst cc opc dst 2 6 ccB RA cc 0 to F NOTE In the first byte of the two byte instruction format the condition code and the op code are each four bits Example Given The carry flag 1 and LABEL_X 1FF7H J...

Page 96: ...rce s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src dst opc src 2 4 rC r IM 4 r8 r R src opc dst 2 4 r9 R r r 0 to F opc dst src 2 4 C7 r lr 4 D7 Ir r opc src dst 3 6 E4 R R 6 E5 R IR opc dst src 3 6 E6 R IM 6 D6 IR IM opc src dst 3 6 F5 IR R opc dst src x 3 6 87 r x r opc src dst x 3 6 97 x r r ...

Page 97: ...H register 01H 20H LD 01H R0 Register 01H 01H R0 01H LD R1 R0 R1 20H R0 01H LD R0 R1 R0 01H R1 0AH register 01H 0AH LD 00H 01H Register 00H 20H register 01H 20H LD 02H 00H Register 02H 20H register 00H 01H LD 00H 0AH Register 00H 0AH LD 00H 10H Register 00H 01H register 01H 10H LD 00H 02H Register 00H 01H register 01H 02 register 02H 02H LD R0 LOOP R1 R0 0FFH R1 0AH LD LOOP R0 R1 Register 31H 0AH ...

Page 98: ... XS 3 12 E7 r XS rr 4 opc src dst XS 3 12 F7 XS rr r 5 opc dst src XLL XLH 4 14 A7 r XL rr 6 opc src dst XLL XLH 4 14 B7 XL rr r 7 opc dst 0000 DAL DAH 4 14 A7 r DA 8 opc src 0000 DAL DAH 4 14 B7 DA r 9 opc dst 0001 DAL DAH 4 14 A7 r DA 10 opc src 0001 DAL DAH 4 14 B7 DA r NOTES 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 For formats 3 and 4 the ...

Page 99: ...s of program memory location 0061H 01H RR4 R0 AAH R2 00H R3 60H LDE R0 01H RR4 R0 contents of external data memory location 0061H 01H RR4 R0 BBH R4 00H R5 60H LDC note 01H RR4 R0 11H contents of R0 is loaded into program memory location 0061H 01H 0060H LDE 01H RR4 R0 11H contents of R0 is loaded into external data memory location 0061H 01H 0060H LDC R0 1000H RR2 R0 contents of program memory locat...

Page 100: ... unaffected LDCD references program memory and LDED references external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 10 E2 r Irr Examples Given R6 10H R7 33H R8 12H program memory location 1033H 0CDH and external data memory location 1033H 0DDH LDCD ...

Page 101: ... are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes Irr even for program memory and odd for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 10 E3 r Irr Examples Given R6 10H R7 33H R8 12H program memory locations 1033H 0CDH and 1034H 0C5H external data memory locations 1033H 0DDH and 1034H ...

Page 102: ...is instruction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 FF Example When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ...

Page 103: ... Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 R R 6 45 R IR opc dst src 3 6 46 R IM Examples Given R0 15H R1 2AH R2 01H register 00H 08H register 01H 37H and register 08H 8AH OR R0 R1 R0 3FH R1 2AH OR R0 R2 R0 37H R2 01H register 01H 37H OR 00H 01H Register 00H 3FH register 01H 37H OR 01H 00H Register 00H 08H register 01H 0BFH OR 00H 02H Register 00...

Page 104: ...x Addr Mode dst opc dst 2 8 50 R 8 51 IR Examples Given Register 00H 01H register 01H 1BH SP 0D9H 0BBH and stack register 0BBH 55H POP 00H Register 00H 55H SP 0BCH POP 00H Register 00H 01H register 01H 55H SP 0BCH In the first example general register 00H contains the value 01H The statement POP 00H loads the contents of location 0BBH 55H into destination register 00H and then increments the stack...

Page 105: ... Cycles Opcode Hex Addr Mode dst opc src 2 8 70 R 8 71 IR Examples Given Register 40H 4FH register 4FH 0AAH SP 0C0H PUSH 40H Register 40H 4FH stack register 0BFH 4FH SP 0BFH PUSH 40H Register 40H 4FH register 4FH 0AAH stack register 0BFH 0AAH SP 0BFH In the first example if the stack pointer contains the value 0C0H and general register 40H the value 4FH the statement PUSH 40H decrements the stack ...

Page 106: ...g RCF RCF Operation C 0 The carry flag is cleared to logic zero regardless of its previous value Flags C Cleared to 0 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 CF Example Given C 1 or 0 The instruction RCF clears the carry flag C to logic zero ...

Page 107: ...next statement that is executed is the one that is addressed by the new program counter value Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 8 AF 10 Example Given SP 0BCH SP 101AH and PC 1234 RET PC 101AH SP 0BEH The statement RET pops the contents of stack pointer location 0BCH 10H into the high byte of the program counter The stack pointer then pops the value in location 0BDH 1...

Page 108: ...therwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 90 R 4 91 IR Examples Given Register 00H 0AAH register 01H 02H and register 02H 17H RL 00H Register 00H 55H C 1 RL 01H Register 01H 02H register 02H 2EH C 0 In the ...

Page 109: ...rwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 10 R 4 11 IR Examples Given Register 00H 0AAH register 01H 02H and register 02H 17H C 0 RLC 00H Register 00H 54H C 1 RLC 01H Register 01H 02H register 02H 2EH C 0 In the first example if general register 00H has the va...

Page 110: ...rithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 E0 R 4 E1 IR Examples Given Register 00H 31H register 01H 02H and register 02H 17H RR 00H Register 00H 98H C 1 RR 01H Register 01H 02H register 02H 8BH C 1 In the first example if general register 00H contains the value 31H 00110001B ...

Page 111: ...wise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 C0 R 4 C1 IR Examples Given Register 00H 55H register 01H 02H register 02H 17H and C 0 RRC 00H Register 00H 2AH C 1 RRC 01H Register 01H 02H register 02H 0BH C 1 In the first example if general register 00H contains the...

Page 112: ... if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 R R 6 35 R IR opc dst src 3 6 36 R IM Examples Given R1 10H R2 03H C 1 register 01H 20H...

Page 113: ...F Set Carry Flag SCF Operation C 1 The carry flag C is set to logic one regardless of its previous value Flags C Set to 1 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 DF Example The statement SCF sets the carry flag to logic one ...

Page 114: ...cleared otherwise S Set if the result is negative cleared otherwise V Always cleared to 0 Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 D0 R 4 D1 IR Examples Given Register 00H 9AH register 02H 03H register 03H 0BCH and C 1 SRA 00H Register 00H 0CD C 0 SRA 02H Register 02H 03H register 03H 0DEH C 0 In the first example if general register 00H contains the value 9AH 10011010B the stateme...

Page 115: ...ters are retained Stop mode can be released by an external reset operation or External interrupt input For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc 1 4 7F Example The statement LD STOPCON 0A5H STOP NOP NOP NOP halts all microcontrolle...

Page 116: ...the sign of the result is of the same as the sign of the source operand cleared otherwise Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 R R 6 25 R IR opc dst src 3 6 26 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH SUB R1 R2 R1 0FH R2 03H SUB R1 R2 R1 08H R2 03H SUB 01H 02H Register 01H 1EH register 02H 0...

Page 117: ...herwise V Always cleared to 0 Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 R R 6 65 R IR opc dst src 3 6 66 R IM Examples Given R0 0C7H R1 02H R2 12H register 00H 2BH register 01H 02H and register 02H 23H TCM R0 R1 R0 0C7H R1 02H Z 1 TCM R0 R1 R0 0C7H R1 02H register 02H 23H Z 0 TCM 00H 01H Register 00H 2BH register 01H 02H Z 1 TCM 00H 01H Re...

Page 118: ...at Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 R R 6 75 R IR opc dst src 3 6 76 R IM Examples Given R0 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H TM R0 R1 R0 0C7H R1 02H Z 0 TM R0 R1 R0 0C7H R1 02H register 02H 23H Z 0 TM 00H 01H Register 00H 2BH register 01H 02H Z 0 TM 00H 01H Register 00H 2BH register 01H 02H regist...

Page 119: ...ways reset to 0 Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 B2 r r 6 B3 r lr opc src dst 3 6 B4 R R 6 B5 R IR opc dst src 3 6 B6 R IM Examples Given R0 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H XOR R0 R1 R0 0C5H R1 02H XOR R0 R1 R0 0E4H R1 02H register 02H 23H XOR 00H 01H Register 00H 29H register 01H 02H XOR 00H 01H Register 00H 08H register 01...

Page 120: ...he XIN and XOUT pins connect the oscillation source to the on chip clock circuit Simplified external RC oscillator and crystal ceramic oscillator circuits are shown in Figures 7 1 and 7 2 When you use external oscillator P1 0 P1 1 must be set to output port to prevent current consumption S3C9454B F9454B XOUT R Figure 7 1 Main Oscillator Circuit RC Oscillator with Internal Capacitor S3C9454B P9454B...

Page 121: ...read write addressable and has the following functions Oscillator IRQ wake up function enable disable CLKCON 7 Oscillator frequency divide by value non divided 2 8 or 16 CLKCON 4 and CLKCON 3 The CLKCON register controls whether or not an external interrupt can be used to trigger a Stop mode release This is called the IRQ wake up function The IRQ wake up enable bit is CLKCON 7 After a reset the ex...

Page 122: ...al RC Oscillator 3 2 MHz Internal RC Oscillator 0 5 MHz External Crystal Ceramic Oscillator NOTE An external interrupt with RC delay noise filter can be used to release stop mode and wake up the main oscillator In the S3C9454B F9454B the INT0 INT1 external interrupts are of this type P2 6 CLO Smart Option 3F 1 0 in ROM 1 8 External RC Oscillator Figure 7 4 System Clock Circuit Diagram ...

Page 123: ...CLOCK CIRCUIT S3C9454B F9454B 7 4 NOTES ...

Page 124: ...um time interval after the power supply comes within tolerance in order to allow time for internal CPU clock oscillation to stabilize The minimum required oscillation stabilization time for a reset is approximately 6 55 ms 216 fOSC fOSC 10 MHz When a reset occurs during normal operation with both VDD and nRESET at High level the signal at the nRESET pin is forced Low and the Reset operation starts...

Page 125: ...on All interrupts are disabled The watchdog function basic timer is enabled Ports 0 2 are set to input mode Peripheral control and data registers are disabled and reset to their initial values see Table 8 1 The program counter is loaded with the ROM reset address 0100H When the programmed oscillation stabilization time interval has elapsed the address stored in ROM location 0100H and 0101H is fetc...

Page 126: ...d clock value is used If you use an external interrupt for Stop mode release you can also program the duration of the oscillation stabilization interval To do this you must put the appropriate value to BTCON register before entering Stop mode The external interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the on...

Page 127: ...T Value Bit Address R W 7 6 5 4 3 2 1 0 Timer 0 counter register T0CNT D0H R 0 0 0 0 0 0 0 0 Timer 0 data register T0DATA D1H R W 1 1 1 1 1 1 1 1 Timer 0 control register T0CON D2H R W 0 0 0 0 0 Location D3H is not mapped Clock control register CLKCON D4H R W 0 0 0 System flags register FLAGS D5H R W x x x x Locations D6H D8H are not mapped Stack pointer register SP D9H R W x x x x x x x x Locatio...

Page 128: ... register P0PND E8H R W 0 0 0 0 Port 1 control register P1CON E9H R W 0 0 0 0 0 0 Port 2 control register High byte P2CONH EAH R W 0 0 0 0 0 0 0 Port 2 control register Low byte P2CONL EBH R W 0 0 0 0 0 0 0 0 Locations ECH F1H are not mapped PWM data register PWMDATA F2H R W 0 0 0 0 0 0 0 0 PWM control register PWMCON F3H R W 0 0 0 0 0 0 0 STOP control register STOPCON F4H R W 0 0 0 0 0 0 0 0 Loca...

Page 129: ...RG 0100H RESET DI disable interrupt LD BTCON 10100011B Watch dog disable LD CLKCON 00011000B Select non divided CPU clock LD SP 0C0H Stack pointer must be set LD P0CONH 10101010B LD P0CONL 10101010B P0 0 P0 7 push pull output LD P1CON 00001010B P1 0 P1 1 push pull output LD P2CONH 01001010B LD P2CONL 10101010B P2 0 P2 6 push pull output Timer 0 settings LD T0DATA 50H CPU 3 2 MHz interrupt interval...

Page 130: ...ple S3C9454B F9454B Initialization Routine Continued Main loop MAIN NOP Start main loop LD BTCON 02H Enable watchdog function Basic counter BTCNT clear CALL KEY_SCAN CALL LED_DISPLAY CALL JOB JR T MAIN Subroutines KEY_SCAN NOP RET LED_DISPLAY NOP RET JOB NOP RET ...

Page 131: ... PWMCOM 00000010B PWM overflow interrupt enable check JR Z NEXT_CHK2 TM P0PND 00000001B JP NZ PWMOVF_INT NEXT_CHK2 TM P0PND 00000010B INT0 interrupt enable check JR Z NEXT_CHK3 TM P0PND 00000001B JP NZ INT0_INT NEXT_CHK3 TM P0PND 00001000B INT1 interrupt enable check JP Z END_INT TM P0PND 00000100B JP NZ INT1_INT IRET Interrupt return END_INT IRET Timer0 interrupt service routine INT_TIMER0 AND T0...

Page 132: ...9454B F9454B Initialization Routine Continued External interrupt0 service routine INT0_INT AND P0PND 11111110B INT0 Pending bit clear IRET Interrupt return External interrupt1 service routine INT1_INT AND P0PND 11111011B INT1 Pending bit clear IRET Interrupt return END ...

Page 133: ...RESET and POWER DOWN S39454B F9454B 8 10 NOTES ...

Page 134: ...nput or push pull output Pull up resistors are assignable by software Port 0 pins can also be used as alternative function ADC input external interrupt input Bit 1 Bit programmable I O port for schmitt trigger input or push pull open drain output Pull up or pull down resistors are assignable by software Port 1 pins can also oscillator input output or reset input by smart option P1 2 is input only ...

Page 135: ...the structure shown in Figure 9 1 Table 9 2 Port Data Register Summary Register Name Mnemonic Hex R W Port 0 data register P0 E0H R W Port 1 data register P1 E1H R W Port 2 data register P2 E2H R W NOTE A reset operation clears the P0 P2 data register to 00H 7 6 5 4 3 2 1 0 LSB MSB I O Port n Data Register n 0 2 Pn 0 Pn 1 Pn 2 Pn 4 Pn 3 Pn 5 Pn 6 Pn 7 Figure 9 1 Port Data Register Format ...

Page 136: ...ative functions ADC input external interrupt input and PWM output Two control resisters are used to control Port 0 P0CONH E6H and P0CONL E7H You access port 0 directly by writing or reading the corresponding port data register P0 E0H VDD In Out Output DIsable input mode P0 Data VDD Pull up register 50 kΩ typical Circuit type A Input Data To ADC M U X Pull up Enable P0CONH PWM MUX D0 D1 Noise Filte...

Page 137: ...t pull up enable 0 1 Alternative function PWM output 1 0 Push pull output 1 1 A D converter input ADC6 schmitt trigger input off 3 2 Port 0 P0 5 ADC5 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 A D converter input ADC5 schmitt trigger input off 1 0 Port 0 P0 4 ADC4 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Sch...

Page 138: ...tput 1 1 A D converter input ADC2 Schmitt trigger input off 3 2 Port 0 P0 1 ADC1 INT1 Configuration Bits 0 0 Schmitt trigger input falling edge interrupt input 0 1 Schmitt trigger input pull up enable falling edge interrupt input 1 0 Push pull output 1 1 A D converter input ADC1 Schmitt trigger input off 1 0 Port 0 P0 0 ADC0 INT0 Configuration Bits 0 0 Schmitt trigger input falling edge interrupt ...

Page 139: ...terrupt Pending Bit 0 No interrupt pending when read 0 Pending bit clear when write 1 Interrupt is pending when read 1 No effect when write 1 Port 0 0 ADC0 INT0 Interrupt Enable Bit 0 INT0 falling edge interrupt disable 1 INT0 falling edge interrupt enable 0 Port 0 0 ADC0 INT0 Interrupt Pending Bit 0 No interrupt pending when read 0 Pending bit clear when write 1 Interrupt is pending when read 1 N...

Page 140: ...rt option Also P1 2 is used for RESET pin by smart option One control register is used to control port 1 P1CON E9H You address port 1 bits directly by writing or reading the port 1 data register P1 E1H When you use external oscillator P1 0 P1 1 must be set to output port to prevent current consumption VDD In Out Output DIsable input mode P1 Data VDD Pull Up Register 50 kΩ typical Circuit type A In...

Page 141: ...l open drain output 5 4 Not used for S3C9454B F9454B 3 2 Port 1 P1 1 Configuration Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input pull up enable 1 0 Push pull output 1 1 Schmitt trigger input pull down enable 1 0 Port 1 P1 0 Configuration Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input pull up enable 1 0 Push pull output 1 1 Schmitt trigger input pull down enable NOTE When you u...

Page 142: ...ing control register settings It is designed for high current functions such as LED direct drive You address port 2 bits directly by writing or reading the port 2 data register P2 E2H The port 2 control register P2CONH and P2CONL is located at addresses EAH EBH respectively VDD In Out Output DIsable input mode P0 Data VDD Pull up register 50 kΩ typical Circuit Type A Input Data to ADC Pull up Enab...

Page 143: ...utput pull up enable 1 1 0 Open drain output 1 1 1 Alternative function CLO output 3 2 Port 2 P2 5 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 Open drain output 1 0 Port 2 P2 4 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 Open drain output NOTE When noise problem is ...

Page 144: ...guration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 Open drain output 3 2 Port 2 P2 1 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 Open drain output 1 0 Port 2 P2 0 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 T0 m...

Page 145: ...I O PORTS S3C9454B F9454B 9 12 NOTES ...

Page 146: ...ction To signal the end of the required oscillation stabilization interval after a Reset or a Stop mode release The functional components of the basic timer block are Clock frequency divider fOSC divided by 4096 1024 or 128 with multiplexer 8 bit basic timer counter BTCNT DDH read only Basic timer control register BTCON DCH read write Timer 0 Timer 0 has the following functional components Clock f...

Page 147: ...cleared during normal operation by writing a 1 to BTCON 1 To clear the frequency dividers for both the basic timer input clock and the timer 0 clock you write a 1 to BTCON 0 7 6 5 4 3 2 1 0 LSB MSB Basic Timer Control Register BTCON DCH R W Watchdog timer enable bits 1010B Disable watchdog function Other value Enable watchdog function Basic timer counter clear bits 0 No effect 1 Clear basic timer ...

Page 148: ... automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a Reset or when Stop mode has been released by an external interrupt In Stop mode whenever a Reset or an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of fOSC 4096 for Reset or at th...

Page 149: ... 10000B 00000B Reset Release Voltage NOTE Duration of the oscillator stabilization wait time t WAIT when it is released by a Power on reset is 4096 x 16 fOSC tRST RC R and C are value of external power on Reset VDD RESET Internal Reset Release Oscillator XOUT BTCNT clock BTCNT value Oscillator Stabilization Time trst RC 0 8 VDD Figure 10 2 Oscillation Stabilization Time on RESET ...

Page 150: ...ESET External Interrupt Oscillator XOUT BTCNT clock BTCNT Value tWAIT Basic Timer Increment 10000B STOP Release Signal 00000B Normal Operating Mode Normal Operating Mode STOP Mode STOP Mode Release Signal STOP Instruction Execution BTCON 3 BTCON 2 0 0 1 1 0 1 0 1 tWAIT 4096 x 16 fosc 1024 x 16 fosc 128 x 16 fosc Invalid setting tWAIT When fOSC is 10 MHz 6 55 ms 1 64 ms 0 2 ms Figure 10 3 Oscillati...

Page 151: ... 0 DB 0E7H 003EH enable LVR 2 3 V DB 03H 003FH internal RC 3 2 MHz in VDD 5 V Initialize System and Peripherals ORG 0100H RESET DI Disable interrupt LD CLKCON 00011000B Select non divided CPU clock LD SP 0C0H Stack pointer must be set LD BTCON 02H Enable watchdog function Basic timer clock fOSC 4096 Basic counter BTCNT clear EI Enable interrupt Main loop MAIN LD BTCON 02H Enable watchdog function ...

Page 152: ...ation by writing a 1 to T0CON 3 NOTE To use T0 match output P2 0 T0CON 3 must be set to 1 In this case there can be same delay in the timer operation In case time interval is very important make T0CON 3 0 Timer 0 interrupt pending bit 0 No T0 interrupt pending when read 0 Clear T0 pending bit when write 1 Interrupt is pending when read 1 No effect when write 7 6 5 4 3 2 1 0 LSB MSB Timer 0 Control...

Page 153: ...n clears the counter If for example you write the value 10H to T0DATA the counter will increment until it reaches 10H At this point the Timer 0 interrupt request is generated the counter value is reset and counting resumes Comparator CLK Data Register T0DATA Match T0CON 3 Timer 0 counter clear PND IRQ0 T0INT T0CON 1 Interrupt Enable Disable R clear Counter T0CNT NOTE T0CON 3 is not auto cleared yo...

Page 154: ... Count start T0CON 3 1 Match Match Match Match Match Match Match Compare Value T0DATA Up Counter Value T0CNT Counter Clear T0CON 3 Interrupt Request T0CON 0 T0 Match Output P2 0 Clear Clear Clear T0DATA Value change Figure 10 6 Timer 0 Timing Diagram ...

Page 155: ...ontrol Register Write 1010xxxxB to disable Basic Timer Control Register Timer 0 Control Register T0CNT D0H Read Only 8 Bit Comparator T0DATA Buffer Data Bus Data Bus Match Signal Bit 3 IRQ0 Bits 7 6 XIN DIV R 1 4096 1 1024 1 128 Bit 0 DIV R 1 4096 1 1 8 1 256 XIN MUX MUX Bits 3 2 MUX T0DATA D1H Read Write Bit 3 Bit 1 Bit 0 Clear Match Clear When BTCNT 4 is set after releasing from RESET or STOP mo...

Page 156: ...z in VDD 5 V ORG 0100H RESET DI Disable interrupt LD BTCON 10100011B Watchdog disable LD CLKCON 00011000B Select non divided CPU clock LD SP 0C0H Set stack pointer LD P0CONH 10101010B LD P0CONL 10101010B P0 0 0 7 push pull output LD P1CON 00001010B P1 0 P1 1 push pull output LD P2CONH 01001010B LD P2CONL 10101010B P2 0 P2 6 push pull output Timer 0 settings LD T0DATA 50H CPU 3 2 MHz interrupt inte...

Page 157: ...ET Interrupt Service Routines INT_9454 TM T0CON 00000010B Interrupt enable check JR Z NEXT_CHK1 TM T0CON 00000001B If timer 0 interrupt was occurred JP NZ INT_TIMER0 T0CON 0 bit would be set NEXT_CHK1 Interrupt enable bit and pending bit check IRET INT_TIMER0 Timer 0 interrupt service routine AND T0CON 11110110B Pending bit clear IRET END ...

Page 158: ...to 1 You can select a clock for the PWM counter by set PWMCON 6 7 Clocks which you can select are fOSC 64 fOSC 8 fOSC 2 fOSC 1 FUNCTION DESCRIPTION PWM The 8 bit PWM circuits have the following components 6 bit comparator and extension cycle circuit 6 bit reference data register PWMDATA 7 2 2 bit extension data register PWMDATA 1 0 PWM output pins P0 6 PWM PWM Counter To determine the PWM module s...

Page 159: ...er the lower 6 bit of counter matches the reference data register PWMDATA 7 2 If the value in the PWMDATA 7 2 register is not zero an overflow of the lower 6 bits of counter causes the PWM output to toggle to High level In this way the reference value written to the reference data register determines the module s base duty cycle The value in the upper 2 bits of counter is compared with the extensi...

Page 160: ... Extension Data Register PWMDATA 1 0 PWMDATA Bit Bit1 Bit0 Stretched Cycle Number 00 01 2 10 1 3 11 1 2 3 250 ns 250 ns 8 ms 8 ms 250 ns 0H 40H 80H 4 MHz 000000xxB 000001xxB 100000xxB 111111xxB PWM Clock PWM Data Register Values PWMDATA Figure 11 1 8 Bit PWM Basic Waveform ...

Page 161: ...PWM S3C9454B F9454B 11 4 1st 2nd 3th 4th 1st 2nd 3th 4th 500 ns 750 ns 0H 40H 4 MHz 0H 40H PWM Clock 4 MHz 000010xxB PWMDATA 0000 1001B Basic waveform Extended waveform Figure 11 2 8 Bit Extended PWM Waveform ...

Page 162: ...logic zero disabling the entire PWM module 7 6 5 4 3 2 1 0 LSB MSB PWM Control Register PWMCON F3H Reset 00H PWM input clock selection bits 00 fOSC 64 01 fOSC 8 10 fOSC 2 11 fOSC 1 Not used for S3C9454B F9454B PWMDATA reload interval selection bit 0 reload from 8 bit up counter overflow 1 reload from 6 bit up counter overflow PWM counter clear bit 0 No effect 1 Clear the PWM counter PWM counter en...

Page 163: ...WM Extension Data Register From 8 bit up counter 7 6 From 8 bit up counter 5 0 6 bit Data Buffer 6 bit Data Register F2H PWMCON 3 clear 8 or 6 bit up counter overflow DATA BUS 7 0 F2H bit7 2 P0 6 PWM 2 bit Counter 6 bit Counter PWMCON 2 MUX fOSC 64 fOSC fOSC 8 fOSC 2 PWMCON 6 7 F2H bit1 0 Figure 11 4 PWM Functional Block Diagram ...

Page 164: ...ternal RC 3 2 MHz in VDD 5 V Initialize System and Peripherals ORG 0100H RESET DI disable interrupt LD BTCON 10100011B Watchdog disable LD P0CONH 10011010B Configure P0 6 PWM output LD PWMCON 00000110B fOSC 64 counter interrupt enable LD PWMDATA 80H EI Enable interrupt Main loop MAIN JR t MAIN Interrupt Service Routines INT_9454 Interrupt enable bit and pending bit check TM PWMCON 00000010B Interr...

Page 165: ...8 BIT PWM S3C9454B F9454B 11 8 F PROGRAMMING TIP Programming the PWM Module to Sample Specifications Continued INT_PWM PWM interrupt service routine AND PWMCON 11110110B pending bit clear IRET END ...

Page 166: ...ccessive approximation register to 200H the approximate half way point of an 10 bit register This register is then updated automatically during each conversion step The successive approximation block performs 10 bit conversions for one input channel at a time You can dynamically select different channels by manipulating the channel selection bit value ADCON 7 4 in the ADCON register To start the A...

Page 167: ... ten analog input pins ADC0 ADC8 by manipulating the 4 bit value for ADCON 7 ADCON 4 7 6 5 4 3 2 1 0 LSB MSB A D Converter Control Register ADCON F7H R W ADC0 P0 0 ADC1 P0 1 ADC2 P0 2 ADC3 P0 3 ADC4 P0 4 ADC5 P0 5 ADC6 P0 6 ADC7 P0 7 ADC8 P2 6 Connected with GND internally Connected with GND internally A D Conversion input pin selection bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1111 C...

Page 168: ... conversion step The reference voltage level for the first bit conversion is always 1 2 VDD A D Converter Control Register ADCON F7H ADCON 7 4 M U L T I P L E X E R Control Circuit D A Converter VDD VSS Successive Approximation Circuit Analog Comparator Clock Selector ADCON 0 ADEN ADCON 2 1 Conversion Result ADDATAH F8H ADDATAL F9H To data bus ADCON 3 EOC Flag ADC0 P0 0 ADC1 P0 1 ADC2 P0 2 ADC7 P0...

Page 169: ...version process requires 4 steps 4 clock edges to convert each bit and 10 clocks to step up A D conversion Therefore total of 50 clocks are required to complete an 10 bit conversion With an 10 MHz CPU clock frequency one clock cycle is 400 ns 4 fosc If each bit conversion requires 4 clocks the conversion rate is calculated as follows 4 clocks bit 10 bits step up time 10 clock 50 clocks 50 clock 40...

Page 170: ...ing the appropriate value to the ADCON register 4 When conversion has been completed 50 clocks have elapsed the EOC flag is set to 1 so that a check can be made to verify that the conversion was successful 5 The converted digital value is loaded to the output register ADDATAH 8 bit and ADDATAL 2 bit then the ADC module enters an idle state 6 The digital conversion result can now be read from the A...

Page 171: ...5 V ORG 0100H RESET DI disable interrupt LD BTCON 10100011B Watchdog disable LD P0CONH 11111111B Configure P0 4 P0 7 AD input LD P0CONL 11111111B Configure P0 0 P0 3 AD input LD P2CONH 00100000B Configure P2 6 AD input EI Enable interrupt Main loop MAIN CALL AD_CONV Subroutine for AD conversion JR t MAIN AD_CONV LD ADCON 00000001B Select analog input channel P0 0 select conversion speed fOSC 16 se...

Page 172: ... 8 bits of conversion result are stored to ADDATAH register LD R1 ADDATAL Low 2 bits of conversion result are stored to ADDATAL register LD ADCON 00010011B Select analog input channel P0 1 Select conversion speed fOSC 8 Set conversion start bit CONV_LOOP2 TM ADCON 00001000B Check EOC flag JR Z CONV_LOOP2 LD R2 ADDATAH LD R3 ADDATAL RET INT_9454 Interrupt enable bit and pending bit check Pending bi...

Page 173: ...A D CONVERTER S3C9454B F9454B 12 8 NOTES ...

Page 174: ...gs D C electrical characteristics A C electrical characteristics Input timing measurement points Oscillator characteristics Oscillation stabilization time Operating voltage range Schmitt trigger input characteristics Data retention supply voltage in stop mode Stop mode release timing when initiated by a RESET A D converter electrical characteristics LVR circuit characteristics LVR reset timing ...

Page 175: ...age VDD 0 3 to 6 5 V Input voltage VI All ports 0 3 to VDD 0 3 V Output voltage VO All output ports 0 3 to VDD 0 3 V Output current high IOH One I O pin active 25 mA All I O pins active 80 Output current low IOL One I O pin active 30 mA All I O pins active 150 Operating temperature TA 25 to 85 C Storage temperature TSTG 65 to 150 C ...

Page 176: ... 20 Input low leakage current ILIL1 All input except ILIL2 VIN 0 V 1 uA ILIL2 XIN XOUT VIN 0 V 20 Output high leakage current ILOH All output pins VOUT VDD 2 uA Output low leakage current ILOL All output pins VOUT 0 V 2 uA Pull up resistors RP VIN 0 V TA 25 C Ports 0 1 2 VDD 5 V 25 50 100 kΩ Pull down resistors RP VIN 0 V TA 25 C Ports 1 VDD 5 V 25 50 100 Supply current IDD1 Run mode 10 MHz CPU cl...

Page 177: ...ristics TA 25 C to 85 C VDD 2 0 V to 5 5 V Parameter Symbol Conditions Min Typ Max Unit Interrupt input low width tINTL INT0 INT1 VDD 5 V 10 200 ns RESET input low width tRSL Input VDD 5 V 10 1 us tINTL tINTH XIN 0 8 VDD 0 2 VDD Figure 13 1 Input Timing Measurement Points ...

Page 178: ...0 5 Table 13 5 Oscillation Stabilization Time TA 25 C to 85 C VDD 2 0 V to 5 5 V Oscillator Test Condition Min Typ Max Unit Main crystal fOSC 1 0 MHz 20 ms Main ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range 10 ms External clock main system XIN input high and low width tXH tXL 25 500 ns Oscillator stabilization tWAIT when released by a reset 1 2 ...

Page 179: ...ock 6 MHz 1 MHz 1 2 3 4 5 6 7 Supply Voltage V 2 MHz 3 MHz 4 MHz 2 7 5 5 4 5 Figure 13 2 Operating Voltage Range VSS A A 0 2 VDD B 0 4 VDD C 0 6 VDD D 0 8 VDD VDD VOUT VIN B C D 0 3 VDD 0 7 VDD Figure 13 3 Schmitt Trigger Input Characteristics Diagram ...

Page 180: ...etention supply current IDDDR Stop mode VDDDR 2 0 V 0 1 5 uA NOTE Supply current does not include current drawn through internal pull up resistors or external output current loads Data Retention Mode VDDDR Execution Of Stop Instrction VDD Normal Operating Mode Oscillation Stabilization Time Stop Mode tWAIT RESET RESET Occurs NOTE tWAIT is the same as 4096 x 16 x 1 fOSC Figure 13 4 Stop Mode Releas...

Page 181: ...al linearity error DLE 1 Offset error of top EOT 1 3 Offset error of bottom EOB 1 2 Conversion time 1 tCON fOSC 10 MHz 20 µs Analog input voltage VIAN VSS VDD V Analog input impedance RAN 2 MW Analog input current IADIN VDD 5 V 10 µA Analog block current 2 IADC VDD 5 V 1 3 mA VDD 3 V 0 5 1 5 VDD 5 V power down mode 100 500 nA NOTES 1 Conversion time is the time required from the moment a conversio...

Page 182: ... 13 9 Table 13 8 LVR Circuit Characteristics TA 25 C VDD 2 0 V to 5 5 V Parameter Symbol Conditions Min Typ Max Unit Low voltage reset VLVR 2 0 3 3 3 6 2 3 3 0 3 9 2 6 3 6 4 2 V VDD VLVR MAX VLVR VLVR MIN Figure 13 5 LVR Reset Timing ...

Page 183: ...ELECTRICAL DATA S3C9454B F9454B 13 10 NOTES ...

Page 184: ...16 pin DIP package Samsung 16 DIP 300A a 16 pin SOP package Samsung 16 SOP BD300 SG a 16 pin SSOP package Samsung 16 SSOP BD44 Package dimensions are shown in Figure 14 1 14 2 14 3 14 4 14 5 and 14 6 NOTE Dimensions are in millimeters 26 80 MAX 26 40 0 20 1 77 20 DIP 300A 6 40 0 20 20 1 0 46 0 10 1 52 0 10 11 10 0 15 0 2 5 0 1 0 0 0 5 7 62 2 54 0 51 MIN 3 30 0 30 3 25 0 20 5 08 MAX Figure 14 1 20 ...

Page 185: ... NOTE Dimensions are in millimeters 20 SOP 375 10 30 0 30 11 20 1 10 13 14 MAX 12 74 0 20 0 66 0 8 0 203 0 10 0 05 9 53 7 50 0 20 0 85 0 20 0 05 MIN 2 30 0 10 2 50 MAX 0 40 0 10 MAX 0 10 0 05 1 27 Figure 14 2 20 SOP 375 Package Dimensions ...

Page 186: ...3 NOTE Dimensions are in millimeters 20 SSOP 225 6 40 0 20 11 20 1 10 6 90 MAX 6 50 0 20 0 30 0 05 MIN 1 50 0 10 1 85 MAX 0 8 0 15 0 10 0 05 5 72 4 40 0 10 0 50 0 20 0 10 MAX 0 10 0 22 0 05 0 65 Figure 14 3 20 SSOP 225 Package Dimensions ...

Page 187: ...B 14 4 NOTE Dimensions are in millimeters 19 80 MAX 19 40 0 20 0 81 6 40 0 20 16 1 16 DIP 300A 0 46 0 10 1 50 0 10 9 8 0 15 0 2 5 0 1 0 0 0 5 7 62 2 54 0 38 MIN 3 30 0 30 3 25 0 20 5 08 MAX Figure 14 4 16 DIP 300A Package Dimensions ...

Page 188: ...ANICAL DATA 14 5 NOTE Dimensions are in millimeters 16 SOP BD300 SG 9 16 1 8 1 27BSC 0 8 10 10 10 50 10 26 10 56 0 35 0 48 2 35 2 65 0 50 0 75 45 0 23 0 32 0 40 1 27 0 10 0 30 Figure 14 5 16 SOP BD300 SG Package Dimensions ...

Page 189: ...52 0 008 6 40 0 20 0 10 MAX 0 004 MAX 0 004 0 012 0 003 0 10 0 30 0 07 0 031 0 80 0 002 0 05 MIN 0 256 0 004 6 50 0 10 0 004 0 006 0 002 0 10 0 15 0 05 0 019 0 008 0 50 0 20 0 213 5 40 0 173 0 004 4 40 0 10 0 059 0 004 1 50 0 10 0 072 1 85 MAX 0 018 0 45 Figure 14 6 16 SSOP BD44 Package Dimensions ...

Page 190: ...4B in function in D C electrical characteristics and in pin configuration Because of its simple programming requirements the S3F9454B is ideal for use as an evaluation chip for the S3C9454BB F9454B VDD VDD P0 0 ADC0 INT0 SCL P0 1 ADC1 INT1 SDA P0 2 ADC2 P0 3 ADC3 P0 4 ADC4 P0 5 ADC5 P0 6 ADC6 PWM P0 7 ADC7 P2 6 ADC8 CLO S3F9454B 20 19 18 17 16 15 14 13 12 11 VSS VSS XIN P1 0 XOUT P1 1 VPP RESET P1...

Page 191: ...SCL P0 1 ADC1 INT1 SDA P0 2 ADC2 P0 3 ADC3 P0 4 ADC4 P0 5 ADC5 P0 6 ADC6 PWM 16 15 14 13 12 11 10 9 VSS VSS XIN P1 0 XOUT P1 1 VPP RESET P1 2 T0 P2 0 P2 1 P2 2 P2 3 1 2 3 4 5 6 7 8 NOTE The bolds indicate MTP pin name Figure 15 2 Pin Assignment Diagram 16 Pin Package ...

Page 192: ...f S3F9454B and S3C9454B Features Characteristic S3F9454B S3C9454B Program memory 4 Kbyte Flash ROM 4K byte mask ROM Operating voltage VDD 2 0 V to 5 5 V 2 0 V to 5 5 V MTP programming mode VDD 5 V VPP 12 5 V Pin configuration 20 DIP 20 SOP 20 SSOP 16 DIP 16SOP 16 SSOP 8 DIP 8 SOP EPROM programmability User Program multi time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12 5 V is s...

Page 193: ...S3F9454B MTP S3C9454B F9454B 15 4 NOTES ...

Page 194: ... sized moved scrolled highlighted added or removed completely SAMA ASSEMBLER The Samsung Arrangeable Microcontroller SAM Assembler SAMA is a universal assembler and generates object code in standard hexadecimal format Assembled program code includes the object code that is used for ROM data and required SMDS program control data To assemble programs SAMA requires a source file and an auxiliary def...

Page 195: ...c target board MTPs Multi times programmable microcontrollers MTPs are under development for S3C9454B F9454B microcontroller Bus Emulator SMDS2 or SK 1000 RS 232C POD Probe Adapter EPROM Writer Unit RAM Break Display Unit Trace Timer Unit SAM8 Base Unit Power Supply Unit IBM PC AT or Compatible TB9454B Target Board EVA Chip Target Application System Figure 16 1 SMDS2 or SK 1000 Product Configurati...

Page 196: ...ocontrollers It is supported by the SK1000 SMDS2 development systems TB9454B SM1333A GND V CC Idle Stop 20 1 10 11 100 Pin Connector 25 1 RESET To User_VCC Off On U2 External Triggers CH1 CH2 128 QFP S3E9450 EVA Chip J101 SMDS SMDS2 CN1 1 24 20 Pin Connector 8 pin DIP switch Figure 16 2 TB9454B Target Board Configuration ...

Page 197: ... The SK1000 SMDS2 main board supplies VCC only to the target board evaluation chip The target system must have its own power supply NOTE The following symbol in the To User_Vcc Setting column indicates the electrical short off configuration SMDS2 Selection SAM8 In order to write data into program memory that is available in SMDS2 the target board should be selected to be for SMDS2 through a switch...

Page 198: ...om External Trigger Sources of the Application System You can connect an external trigger source to one of the two external trigger channels CH1 or CH2 for the SK 1000 SMDS2 breakpoint and trace functions 3EH 7 3EH 6 3EH 5 3EH 4 3EH 3 3EH 2 3FH 1 3FH 0 OFF ON ON OFF Low High NOTE About EVA chip smart option is determined by DIP switch not software Figure 16 3 DIP Switch for Smart Option ...

Page 199: ...2 2 P2 3 P2 4 P2 5 VDD P0 0 ADC0 INT0 P0 1 ADC1 INT1 P0 2 ADC2 P0 3 ADC3 P0 4 ADC4 P0 5 ADC5 P0 6 ADC6 PWM P0 7 ADC7 P2 6 ADC8 CLO Figure 16 4 20 Pin Connector for TB9454B Target Board 20 Pin Connector Target System J101 1 20 10 11 Part Name AS20D Order Cods SM6304 1 20 10 11 20 Pin Connector Figure 16 5 S3C9454B F9454B Probe Adapter for 20 DIP Package ...

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