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viii S3C84I8/F84I8/C84I9/F84I9 MICROCONTROLLER 

Table of Contents 

(Continued)

 

Chapter 11   

8-Bit Timer A/B 

8-Bit Timer A ................................................................................................................................................. 11-1

 

Overview .............................................................................................................................................. 11-1

 

Function Description ............................................................................................................................ 11-2

 

Timer A Control Register (TACON) ..................................................................................................... 11-3

 

Block Diagram...................................................................................................................................... 11-4

 

8-Bit Timer B ................................................................................................................................................. 11-5

 

Overview .............................................................................................................................................. 11-5

 

Block Diagram...................................................................................................................................... 11-5

 

Timer B Control Register (TBCON) ..................................................................................................... 11-6

 

Timer B Pulse Width Calculations ....................................................................................................... 11-7 

Chapter 12   

16-Bit Timer 1(0, 1) 

Overview ....................................................................................................................................................... 12-1

 

Function Description ............................................................................................................................ 12-2

 

Timer 1(0,1) Control Register (T1CON0, T1CON1) ............................................................................ 12-3

 

Block Diagram...................................................................................................................................... 12-6 

Chapter 13   

10-bit PWM (Pulse width Modulation) 

Overview ....................................................................................................................................................... 13-1

 

Function Description ..................................................................................................................................... 13-1

 

PWM .................................................................................................................................................... 13-1

 

PWM Control Register (PWMCON)..................................................................................................... 13-5 

Chapter 14   

Serial I/O Interface 

Overview ....................................................................................................................................................... 14-1

 

Programming Procedure...................................................................................................................... 14-1

 

Serial I/O Control Registers (SIOCON) ............................................................................................... 14-2

 

SIO Prescaler Register (SIOPS).......................................................................................................... 14-3 
 

 

Summary of Contents for S3C84I8

Page 1: ...is document contains the corrections of errors typos and omissions in the following document Samsung 8 bit MCU S3C84I8 F84I8 C84I9 F84I9 User s Manual Document Number 21 S3 C84I8 F84I8 C84I9 F84I9 072006 Publication July 2006 ...

Page 2: ...n reading Input when writing Input and push pull output port can be assigned P1 3 SCLK 4 44 pin 10 42 pin I Serial clock pin input only pin TEST VPP 4 I Power supply pin for flash ROM cell writing indicates that MTP enters into the writing mode When 12 5 V is applied MTP is in writing mode and when 5 V is applied MTP is in reading mode Option NOTE A 100pF capacitor must be connected between Vpp an...

Page 3: ...S3C84I8 F84I8 C84I9 F84I9 8 BIT CMOS MICROCONTROLLERS USER S MANUAL Revision 1 ...

Page 4: ... to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against al...

Page 5: ...d in the individual hardware module descriptions in Part II Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3C8 series microcontrollers Several summary tables are presented for orientation and reference Detailed descriptions of each instruction are presented in a standard format Each instruction description includes one or more practical exampl...

Page 6: ...ure 2 4 Register Page Pointer PP 2 7 Register Set 1 2 9 Register Set 2 2 9 Prime Register Space 2 10 Working Registers 2 12 Using The Register Pointers 2 13 Register Addressing 2 15 Common Working Register Area C0H CFH 2 17 4 Bit Working Register Addressing 2 18 8 Bit Working Register Addressing 2 20 System and User Stack 2 22 Chapter 3 Addressing Modes Overview 3 1 Register Addressing Mode R 3 2 ...

Page 7: ...Peripheral Interrupt Control Registers 5 10 System Mode Register SYM 5 11 Interrupt Mask Register IMR 5 12 Interrupt Priority Register IPR 5 13 Interrupt Request Register IRQ 5 15 Interrupt Pending Function Types 5 16 Interrupt Source Polling Sequence 5 17 Interrupt Service Routines 5 17 Generating interrupt Vector Addresses 5 18 Nesting of Vectored Interrupts 5 18 Chapter 6 Instruction Set Overvi...

Page 8: ...ister CLKCON 7 3 Chapter 8 RESET and Power Down System Reset 8 1 Overview 8 1 Normal Mode Reset Operation 8 1 Hardware Reset Values 8 2 Power Down Modes 8 5 Stop Mode 8 5 Idle Mode 8 6 Chapter 9 I O Ports Overview 9 1 Port Data Registers 9 2 Port 0 9 3 Port 1 9 5 Port 2 9 8 Port 3 9 12 Port 4 9 14 Chapter 10 Basic Timer Overview 10 1 Basic Timer BT 10 1 basic Timer Control Register BTCON 10 1 Basi...

Page 9: ...Control Register TBCON 11 6 Timer B Pulse Width Calculations 11 7 Chapter 12 16 Bit Timer 1 0 1 Overview 12 1 Function Description 12 2 Timer 1 0 1 Control Register T1CON0 T1CON1 12 3 Block Diagram 12 6 Chapter 13 10 bit PWM Pulse width Modulation Overview 13 1 Function Description 13 1 PWM 13 1 PWM Control Register PWMCON 13 5 Chapter 14 Serial I O Interface Overview 14 1 Programming Procedure 14...

Page 10: ...munication for Multiprocessor Configurations 15 13 Chapter 16 A D Converter Overview 16 1 Function Description 16 1 A D Converter Control Register ADCON 16 2 Internal Reference Voltage Levels 16 4 Conversion Timing 16 4 Internal A D Conversion Procedure 16 5 Chapter 17 Watch Timer Overview 17 1 Watch Timer Control Register WTCON R W 17 2 Watch Timer Circuit Diagram 17 3 Chapter 18 LCD Controller D...

Page 11: ...ntrol Registers 20 2 Sector Erase 20 4 Programming 20 6 Reading 20 9 Hard Lock Protection 20 10 Chapter 21 Electrical Data Overview 21 1 Chapter 22 Mechanical Data Overview 22 1 Chapter 23 Development Tools Overview 23 1 SHINE 23 1 SASM 23 1 SAMA Assembler 23 1 HEX2ROM 23 1 Target Boards 23 2 TB84I9 Target Board 23 3 Idle Led 23 4 Stop Led 23 4 ...

Page 12: ... Slices 2 12 2 9 Contiguous 16 Byte Working Register Block 2 13 2 10 Non Contiguous 16 Byte Working Register Block 2 14 2 11 16 Bit Register Pair 2 15 2 12 Register File Addressing 2 16 2 13 Common Working Register Area 2 17 2 14 4 Bit Working Register Addressing 2 19 2 15 4 Bit Working Register Addressing Example 2 19 2 16 8 Bit Working Register Addressing 2 20 2 17 8 Bit Working Register Address...

Page 13: ...er STOPCON 7 4 9 1 Port 0 Low Byte Control Register P0CON 9 4 9 2 Port 1 High Byte Control Register P1CONH 9 6 9 3 Port 1 Low Byte Control Register P1CONL 9 6 9 4 Port 1 Interrupt Pending Register P1INTPND 9 7 9 5 Port 1 Interrupt Enable Register P1INT 9 8 9 6 Port 2 High Byte Control Register P2CONH 9 9 9 7 Port 2 Low Byte Control Register P2CONL 9 10 9 8 Port 2 Pull up Control Register P2PUR 9 1...

Page 14: ...egister UDATA 15 5 15 4 UART Baud Rate Data Register BRDATAH BRDATAL 15 6 15 5 UART Functional Block Diagram 15 8 15 6 Timing Diagram for UART Mode 0 Operation 15 9 15 7 Timing Diagram for UART Mode 1 Operation 15 10 15 8 Timing Diagram for UART Mode 2 Operation 15 12 15 9 Connection Example for Multiprocessor Serial Data Communications 15 14 16 1 A D Converter Control Register ADCON 16 2 16 2 A D...

Page 15: ...8 21 4 Stop Mode Release Timing initiated by RESET 21 9 21 5 Stop Mode Main Release Timing Initiated by Interrupts 21 10 21 6 Stop Mode Sub Release Timing Initiated by Interrupts 21 10 21 7 Waveform for UART Timing Characteristics 21 11 21 8 Operating Voltage Range 21 13 21 9 The Circuit Diagram to Improve EFT Characteristics 21 14 22 1 42 SDIP 600 Package Dimensions 22 1 22 2 44 QFP 1010 Package ...

Page 16: ...on Set Symbols 6 8 6 4 Instruction Notation Conventions 6 9 6 5 OPCODE Quick Reference 6 10 6 6 Condition Codes 6 12 8 1 S3C84I8 F84I8 84I9 F84I9 Set 1 Register Values After RESET 8 2 8 2 S3C84I8 F84I8 84I9 F84I9 Set 1 Bank 0 Register Values After RESET 8 3 8 3 S3C84I8 F84I8 84I9 F84I9 Set 1 Bank 1 Register Values After RESET 8 4 9 1 S3C84I8 F84I8 84I9 F84I9 Port Configuration Overview 9 1 9 2 Por...

Page 17: ... Frequency fOSC1 21 7 21 6 Main Oscillator Clock Stabilization Time tST1 21 7 21 7 Sub Oscillator Frequency fOSC2 21 8 21 8 Subsystem Oscillator crystal Stabilization Time tST2 21 8 21 9 Data Retention Supply Voltage in Stop Mode 21 9 21 10 UART Timing Characteristics in Mode 0 10 MHz 21 11 21 11 A D Converter Electrical Characteristics 21 12 21 12 LVR Low Voltage Reset Circuit Characteristics 21 ...

Page 18: ...Through P2 0 11 9 To Generate a One Pulse Signal Through P2 0 11 10 Using the Timer A 11 11 Using the Timer B 11 12 Chapter 12 16 bit Timer 1 0 1 Using the Timer 1 0 12 7 Chapter 13 10 Bit PWM Pulse Width Modulation Programming the PWM Module to Sample Specifications 13 7 Chapter 14 Serial I O Interface SIO 14 5 Chapter 16 A D Converter Configuring A D Converter 16 6 Chapter 17 Watch Timer Using t...

Page 19: ...21 P1INTPND Port 1 Interrupt Pending Register 4 22 P1INT Port 1 Interrupt Enable 4 23 P2CONH Port 2 Control Register High Byte 4 24 P2CONL Port 2 Control Register Low Byte 4 25 P2PUR Port 2 Pull up Resistor Control Register 4 26 P3CONH Port 3 Control Register High Byte 4 27 P3CONL Port 3 Control Register Low Byte 4 28 P4CONH Port 4 Control Register High Byte 4 29 P4CONL Port 4 Control Register Low...

Page 20: ...Call Procedure 6 26 CCF Complement Carry Flag 6 27 CLR Clear 6 28 COM Complement 6 29 CP Compare 6 30 CPIJE Compare Increment and Jump on Equal 6 31 CPIJNE Compare Increment and Jump on Non Equal 6 32 DA Decimal Adjust 6 33 DA Decimal Adjust 6 34 DEC Decrement 6 35 DECW Decrement Word 6 36 DI Disable Interrupts 6 37 DIV Divide Unsigned 6 38 DJNZ Decrement and Jump if Non Zero 6 39 EI Enable Interr...

Page 21: ...63 POPUD Pop User Stack Decrementing 6 64 POPUI Pop User Stack Incrementing 6 65 PUSH Push to Stack 6 66 PUSHUD Push User Stack Decrementing 6 67 PUSHUI Push User Stack Incrementing 6 68 RCF Reset Carry Flag 6 69 RET Return 6 70 RL Rotate Left 6 71 RLC Rotate Left through Carry 6 72 RR Rotate Right 6 73 RRC Rotate Right through Carry 6 74 SB0 Select Bank 0 6 75 SB1 Select Bank 1 6 76 SBC Subtract ...

Page 22: ...84I9 is a microcontroller with a 32K byte mask programmable ROM embedded The S3F84I9 is a microcontroller with a 32K byte Full Flash ROM embedded The S3C84I8 is a microcontroller with a 8K byte mask programmable ROM embedded The S3F84I8 is a microcontroller with a 8K byte Half Flash ROM embedded Using a proven modular design approach Samsung engineers have successfully developed the S3C84I8 F84I8 ...

Page 23: ...imer counter Timer A with three operating modes Interval mode capture mode and PWM mode One 8 bit timer Timer B with carrier frequency or PWM generator Two 16 bit timer counter Timer 10 11 with three operating modes Interval mode Capture mode and PWM mode Watch Timer Real time and interval time measurement Four frequency output to BUZ pin Clock generation for LCD LCD Controller Driver Optional 8 C...

Page 24: ...SCK RxD TxD TBPWM Xin Xout nRESET P1 0 TAOUT P1 2 TACAP P1 1 TACK P2 0 TBPWM P1 0 P1 5 INT0 INT3 TBOUT PWM BUZ TAOUT TACAP TACK AD5 AD6 T1OUT1 T1CK1 T1CAP1 P0 0 P0 3 COM0 COM3 AD0 AD3 AVREF AVSS Port 3 P3 0 P3 7 SEG4 SEG11 Port 4 P4 0 P4 7 SEG12 SEG19 COM4 COM7 A D UART P2 7 TxD P2 6 RxD P2 2 T1OUT0 P2 0 T1CK0 P2 1 T1CAP0 P1 3 T1OUT1 P1 4 T1CK1 P1 5 T1CAP1 PWM SIO P2 1 PWM P2 5 SCK P2 4 SO P2 3 SI...

Page 25: ... PWM T1 CK0 P 2 0 T1 CAP 1 AD6 P 1 5 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 33 32 31 30 29 28 27 26 25 24 23 T1 OUT0 A D4 P 2 2 T 1CK 1 AD5 P 1 4 Xtin Xtout SI AD7 P 2 3 P4 5 S EG 17 C O M5 PW M T1 C AP 0 P2 1 P3 3 SEG7 P3 2 SEG6 SO SEG 0 P 2 4 SCK SE G1 P 2 5 R x SE G2 P2 6 TX S EG 3 P2 7 Avref Avss P3 0 SEG4 P3 1 SEG5 INT1 BUZ TACK P1 1 INT0 TAOUT P1 0 P 4 7 S EG 19 C O M7 P 4 6 S EG 18 C O...

Page 26: ...4 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 TBPWM T1CK0 P2 0 PWM T1CAP0 P2 1 T1OUT0 AD4 P2 2 P4 0 SEG12 P3 7 SEG11 P3 6 SEG10 P3 5 SEG9 P3 4 SEG8 P3 3 SEG7 P3 2 SEG6 P3 1 SEG5 P3 0 SEG4 AVss AVref P2 7 SEG3 TxD P2 6 SEG2 RxD P2 5 SEG1 SCK P2 4 SEG0 SO 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 S3C84I9 F84I9 Top View 42 SDIP INT0 TAOUT P1 0 P2 3 AD7 SI INT3 T1OUT1 ...

Page 27: ...D5 T1OUT1 AD6 P2 0 P2 3 P2 4 P2 7 I O Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up Alternately can be used as ADC4 ADC7 SI TBPWM PWM T1CAP0 T1CK0 SEG0 SEG3 SO SCK RxD TxD E D 5 H 17 24 31 21 22 23 26 19 22 ADC4 ADC7 TBWPM PWM T1CAP0 T1CK0 SI SEG0 SEG3 SO SCK RxD TxD P3 0 P3 7 I O Bit programmable port input or output mode sel...

Page 28: ...nput pins for timer A D 5 8 2 P1 1 TACAP I Capture input pins for timer A D 5 9 3 P1 2 TAOUT O Pulse width modulation output pins for timer A D 5 7 1 P1 0 TBPWM O Carrier frequency output pins for timer B D 5 19 13 P2 0 T1CK0 I External clock input pins for timer 1 0 D 5 19 13 P2 0 T1CAP0 I Capture input pins for timer 1 0 D 5 20 14 P2 1 T1OUT0 O Timer 1 0 16 bit PWM mode output or counter match t...

Page 29: ...pe Pin Description Circuit Type Pin Number Share Pins nRESET I System reset pin B 18 12 TEST I Pull down resistor connected internally 15 9 VDD VSS Power input pins 11 12 5 6 Xin Xout I O Main oscillator pins 13 14 7 8 NOTES 1 Pin numbers shown in parentheses are for the 44 pin QFP package 2 42 SDIP is only for S3C84I9 F84I9 ...

Page 30: ...8 F84I8 C84I9 F84I9 PRODUCT OVERVIEW 1 9 PIN CIRCUITS Schmitt Trigger In VDD Pull Up Resistor Figure 1 4 Pin Circuit Type B nRESET P Channel N Channel VDD Out Output Disable Data Figure 1 5 Pin Circuit Type C ...

Page 31: ...put Disable Data Pin Circuit Type C Pull up Enable VDD Figure 1 6 Pin Circuit Type D I O Output Disable Port Data Pin Circuit Type C Pull up enable VDD Noise Filter Ext INT Normal Input VDD M U X Alternative output Figure 1 7 Pin Circuit Type D 5 P1 0 P1 3 ...

Page 32: ...C84I9 F84I9 PRODUCT OVERVIEW 1 11 VDD Pull up Resistor Typical Value 50kΩ VDD Pull up Enable Normal Input Output DIsable In Out Analog Input Port Data M U X Alternative Output Figure 1 8 Pin Circuit Type E P2 2 P2 3 ...

Page 33: ...PRODUCT OVERVIEW S3C84I8 F84I8 C84I9 F84I9 1 12 Out SEG COM VLC3 Output Disable VLC2 VLC1 VSS VLC4 VLC5 Figure 1 9 Pin Circuit Type H 4 ...

Page 34: ...Disable Data VDD Circuit Type H 4 Open Drain EN LCD Out EN SEG COM Input Figure 1 10 Pin Circuit Type H 14 P4 4 P4 7 Pull up Enable P CH N CH VDD I O Output Disable Data VDD Circuit Type H 4 Open Drain EN LCD Out EN COM ADC In EN Normal In ADC In Figure 1 11 Pin Circuit Type H 16 P0 0 P0 3 ...

Page 35: ...VIEW S3C84I8 F84I8 C84I9 F84I9 1 14 Pull up Enable P CH N CH VDD I O Output Disable Data VDD Circuit Type H 4 Open Drain EN LCD Out EN SEG Normal Input Figure 1 12 Pin Circuit Type H 17 2 4 P2 7 P3 0 P3 7 P4 0 P4 3 ...

Page 36: ...Internal register file RAM A 16 bit address bus supports program memory operations A separate 8 bit register bus carries addresses and data between the CPU and the register file The S3C84I9 F84I9 has an internal 32 Kbyte mask programmable ROM 32 Kbyte Flash ROM and 528 byte RAM The S3C84I8 F84I8 has an internal 8 Kbyte mask programmable ROM 8 Kbyte Flash ROM and 272 byte RAM ...

Page 37: ... locations in this address range can be used as normal program memory If you use the vector address area to store a program code be careful not to overwrite the vector addresses stored in these locations The ROM address at which a program execution starts after a reset is 0100H Internal Program Memory Flash Interrupt Vector Area ISP Sector Smart Option Rom Cell 32 767 Decimal 255 0 00H 100H 7FFFH ...

Page 38: ... and 03FH must be logic 1 7 6 5 4 3 2 1 0 MSB LSB ROM Address 003FH LVR on off control bit 0 Disable 1 Enable Not used Not used ROM Address 003DH ROM Address 003CH 7 6 5 4 3 2 1 0 MSB LSB Not used 7 6 5 4 3 2 1 0 MSB LSB ROM Address 003EH ISP Protection size selection 00 256 bytes 01 512 bytes 10 1024 bytes 11 2048 bytes 7 6 5 4 3 2 1 0 MSB LSB ISP Protection enable disable bit 0 Enable Not erasab...

Page 39: ...for general purpose use You can always address set 1 register location regardless of which of the 2 register pages is currently selected The set 1 locations however can only be addressed using direct addressing modes The extension of register space into separately addressable areas sets banks and pages is supported by various addressing mode restrictions the select bank instructions SB0 and SB1 an...

Page 40: ...nk 1 System and Peripheral Control Registers Register Addressing Mode System and Peripheral Control Registers Register Addressing Mode General Purpose Register Register Addressing Mode Bank 0 Page 1 Page 0 Set 2 General Purpose Data Registers Indirect Register Indexed Mode and Stack Operations Prime Data Registers All Addressing Modes LCD Display Registers Figure 2 3 Internal Register File Organiz...

Page 41: ...System and Peripheral Control Registers Register Addressing Mode System and Peripheral Control Registers Register Addressing Mode General Purpose Register Register Addressing Mode Bank 0 Page 0 Set 2 General Purpose Data Registers Indirect Register Indexed Mode and Stack Operations Prime Data Registers All Addressing Modes LCD Display Registers Page 0 Figure 2 4 Internal Register File Organization...

Page 42: ... page pointer s source value lower nibble and the destination value upper nibble are always 0000 automatically selecting page 0 as the source and destination page for register addressing Register Page Pointer PP DFH Set 1 R W LSB MSB 7 6 5 4 3 2 1 0 Destination register page selection bits Destination Page 0 Source register page selection bits Source Page 0 NOTE In the S3C84I9 F84I9 microcontrolle...

Page 43: ... Page Pointer for RAM clear Page 0 Page 1 LD PP 00H Destination 0 Source 0 SRP 0C0H LD R0 0FFH Page 0 RAM clear starts RAMCL0 CLR R0 DJNZ R0 RAMCL0 CLR R0 R0 00H LD PP 10H Destination 1 Source 0 LD R0 0FFH Page 1 RAM clear starts RAMCL1 CLR R0 DJNZ R0 RAMCL1 CLR R0 R0 00H ...

Page 44: ...r areas of the register file Registers in set 1 locations are directly accessible at all times using Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 locations C0H FFH...

Page 45: ...r 3 Addressing Modes The prime register area on page 0 is immediately addressable following a reset In order to address prime registers on pages 0 or 1 you must set the register page pointer PP to the appropriate source and destination values FFH F0H E0H D0H C0H Set 1 Bank 0 Peripheral and I O General purpose CPU and system control FFH C0H Set 2 00H Prime Space BFH Bank 1 Page 1 Page 0 Page 0 LCD ...

Page 46: ...PACES 2 11 FFH F0H E0H D0H C0H Set 1 Bank 0 Peripheral and I O General purpose CPU and system control FFH C0H Set 2 00H Prime Space BFH Bank 1 Page 0 LCD data Register Area Page 2 Figure 2 7 Set 1 Set 2 Prime Area Register S3C84I8 F84I8 ...

Page 47: ... locations of selected working register spaces One working register slice is 8 bytes eight 8 bit working registers R0 R7 or R8 R15 One working register block is 16 bytes sixteen 8 bit working registers R0 R15 All the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one ...

Page 48: ... The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RP0 point to the lower slice and RP1 point to the upper slice see Figure 2 6 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 7 RP0 points to the upper slice and R...

Page 49: ...0 R1 R0 R0 R1 ADC R0 R2 R0 R0 R2 C ADC R0 R3 R0 R0 R3 C ADC R0 R4 R0 R0 R4 C ADC R0 R5 R0 R0 R5 C The sum of these six registers 6FH is located in the register R0 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would h...

Page 50: ...e and an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register and the least signi...

Page 51: ...are implemented and S3C84I8 F84I8 microcontroller page0 1 are inplemented Page0 2 contain all of the addressable registers in the internal register file Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RP0 points to locations C0H C7H and RP1 to locations C8H CFH that is to the common working register area FFH C0H Se...

Page 52: ...ed as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages FFH F0H E0H D0H C0H Set 1 FFH FFH C0H Set 2 00H Prime Space BFH Page 0 Page 0 Following a hardware reset register pointers RP0 and RP1 point to the common working register area locations C0H CFH RP0...

Page 53: ...ter area the address bits are concatenated in the following way to form a complete 8 bit address The high order bit of the 4 bit address selects one of the register pointers 0 selects RP0 1 selects RP1 The five high order bits in the register pointer select an 8 byte slice of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in...

Page 54: ...order bits Address OPCODE Selects RP0 or RP1 RP1 RP0 4 bit address provides three low order bits Figure 2 14 4 Bit Working Register Addressing Register address 76H RP0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 R6 0 1 1 0 1 1 1 0 Selects RP0 Instruction INC R6 OPCODE RP1 0 1 1 1 1 0 0 0 Figure 2 15 4 Bit Working Register Addressing Example ...

Page 55: ... complete address are provided by the original instruction Figure 2 14 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 3 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 011 are...

Page 56: ...21 8 bit address form instruction LD R11 R2 RP0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 Selects RP1 R11 Register address 0ABH RP1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 Specifies working register addressing Figure 2 17 8 Bit Working Register Addressing Example ...

Page 57: ...cks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL SPH Register locations D8H and D9H contain the 16 bit stack pointer SP that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H and the ...

Page 58: ...internal register file using PUSH and POP instructions LD SPL 0FFH SPL FFH Normally the SPL is set to 0FFH by the initialization routine PUSH PP Stack address 0FEH PP PUSH RP0 Stack address 0FDH RP0 PUSH RP1 Stack address 0FCH RP1 PUSH R3 Stack address 0FBH R3 POP R3 R3 Stack address 0FBH POP RP1 RP1 Stack address 0FCH POP RP0 RP0 Stack address 0FDH POP PP PP Stack address 0FEH ...

Page 59: ... determine the location of the data operand The operands specified in SAM89RCinstructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are Register R Indir...

Page 60: ...tion OPCODE OPERAND 8 bit Register File Address Point to One Register in Register File One Operand Instruction Example Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Program Memory Register File Figure 3 1 Register Addressing dst OPCODE 4 bit Working Register Point to the Working Register 1 of 8 Two Operand Instruction Example Sample Instruction ADD R1 R2 Where R1...

Page 61: ...egister to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations C0H FFH in set 1 using the Indirect Register addressing mode dst Address of Operand used by Instruction OPCODE ADDRESS 8 bit Register File Address Point to One Register in Register File One Operand Instruction Example...

Page 62: ...ODE PAIR Points to Register Pair Example Instruction References Program Memory Sample Instructions CALL RR2 JP RR2 Program Memory Register File Value used in Instruction OPERAND REGISTER Program Memory 16 Bit Address Points to Program Memory Figure 3 4 Indirect Register Addressing to Program Memory ...

Page 63: ...Working Register Address Point to the Working Register 1 of 8 Sample Instruction OR R3 R6 Program Memory Register File src 3 LSBs Value used in Instruction OPERAND Selected RP points to start fo working register block RP0 or RP1 MSB Points to RP0 or RP1 Figure 3 5 Indirect Working Register Addressing to Register File ...

Page 64: ...ess Program Memory Register File src Value used in Instruction OPERAND Example Instruction References either Program Memory or Data Memory Program Memory or Data Memory Next 2 bit Point to Working Register Pair 1 of 4 LSB Selects Register Pair 16 Bit address points to program memory or data memory RP0 or RP1 MSB Points to RP0 or RP1 Selected RP points to start of working register block Figure 3 6 ...

Page 65: ...ion is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports indexed addressing mode for the internal register file is the Load instruction LD Th...

Page 66: ...points to start of working register block dst src OPCODE Program Memory x OFFSET 4 bit Working Register Address Sample Instructions LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed NEXT 2 Bits Register Pair Value used in Instruction 8 Bits 16 Bits 16 Bits Figure 3 8...

Page 67: ...ints to start of working register block Sample Instructions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed NEXT 2 Bits Register Pair Value used in Instruction 16 Bits 16 Bits 16 Bits dst src OPCODE Program Memory src OFFSET 4 bit Working Register Address OFF...

Page 68: ...ress mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H Identical operation to LDC example except that external program memory is accessed dst src OPCODE Program Memory 0 or 1 Lower Address Byte LSB ...

Page 69: ...OPCODE Program Memory Lower Address Byte Memory Address Used Upper Address Byte Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Next OPCODE Figure 3 11 Direct Addressing for Call and Jump Instructions ...

Page 70: ...Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Current Instruction Program Memory Locations 0 255 Program Memory OPCODE dst Lower Address Byte Upper Address Byte Next Instruction LSB Must be Zero Sa...

Page 71: ...ion occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR OPCODE Program Memory Displacement Program Memory Address Used Sample Instructions JR ULT OFFSET Where OFFSET is a ...

Page 72: ... the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers The Operand value is in the instruction OPCODE Sample Instruction LD R0 0AAH Program Memory OPERAND Figure 3 14 Immediate Addressing ...

Page 73: ...and Power Down Table 4 1 Set 1 Registers Register Name Mnemonic Decimal Hex R W Timer B control register TBCON 208 D0H R W Timer B data register High Byte TBDATAH 209 D1H R W Timer B data register Low Byte TBDATAL 210 D2H R W Basic timer control register BTCON 211 D3H R W Clock control register CLKCON 212 D4H R W System flags register FLAGS 213 D5H R W Register pointer 0 RP0 214 D6H R W Register p...

Page 74: ...H 236 ECH R W Port 2 control register Low Byte P2CONL 237 EDH R W Port 3 control register High Byte P3CONH 238 EEH R W Port 3 control register Low Byte P3CONL 239 EFH R W Port 4 control register High Byte P4CONH 240 F0H R W Port 4 control register Low Byte P4CONL 241 F1H R W Oscillator control register OSCCON 242 F2H R W Location F3H is not mapped UART pending register UARTPND 244 F4H R W UART dat...

Page 75: ...er register Low Byte T1CNTL0 235 EBH R Timer 1 1 counter register High Byte T1CNTH1 236 ECH R Timer 1 1 counter register Low Byte T1CNTL1 237 EDH R UART baud rate data register High Byte BRDATAH 238 EEH R W UART baud rate data register Low Byte BRDATAL 239 EFH R W SIO pre scalar register SIOPS 240 F0H R W SIO data register SIODATA 241 F1H R W Serial I O control register SIOCON 242 F2H R W PWM data...

Page 76: ...of individual bit or related bits Register name Register ID Sign Flag S 0 Operation does not generate a carry or borrow condition 0 Operation generates carry out or borrow into high order bit 7 0 Operation result is a non zero value 0 Operation result is zero 0 Operation generates positive number MSB 0 0 Operation generates negative number MSB 1 Description of the effect of specific bit settings S...

Page 77: ...only 7 Not used for the S3C84I8 F84I8 C84I9 F84I9 must keep always 0 6 4 A D Input Pin Selection Bits 0 0 0 ADC0 0 0 1 ADC1 0 1 0 ADC2 0 1 1 ADC3 1 0 0 ADC4 1 0 1 ADC5 1 1 0 ADC6 1 1 1 ADC7 3 End of Conversion Bit Read only 0 A D conversion opration is in progress 1 A D conversion opration is complete 2 1 Clock Source Selection Bits 0 0 fxx 16 0 1 fxx 8 1 0 fxx 4 1 1 Not used 0 Start or Enable Bit...

Page 78: ...0 1 fxx 1024 1 0 fxx 128 1 1 fxx 1 Not used 1 Basic Timer Counter Clear Bit 1 0 No effect 1 Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer 2 0 No effect 1 Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to 00H Immediately following the write operation the BTCON 1 value is automatically clear...

Page 79: ... mode only 7 5 Not used for the S3C84I8 F84I8 C84I9 F84I9 must keep always 0 4 3 CPU Clock System Clock Selection Bits note 0 0 fxx 16 0 1 fxx 8 1 0 fxx 2 1 1 fxx 1 non divided 2 0 Not used for the S3C84I8 F84I8 C84I9 F84I9 must keep always 0 NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and ...

Page 80: ...4 Flash Memory Mode Selection Bits 0 1 0 1 Programming mode 1 0 1 0 Sector Erase mode 0 1 1 0 Hard Lock mode Others Not used 3 INT Enable Bit During Sector Erase 0 INT disable 1 INT enable 2 Sector Erase Fail Flag 0 Sector Erase success 1 Sector Erase fail 1 Not used for the S3C84I8 F84I8 C84I9 F84I9 0 Flash Mode Start Bit With Out Programming Mode Reading Mode 0 Stop bit 1 Start bit auto cleared ...

Page 81: ...ory Sector address Bits You have to input High address of sector that s accessed FMSECL Flash Memory Sector Register Low byte FAH Set 1 Bank1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 0 Flash Memory Sector address Bits You have to input Low address of sector that s accessed Ex If you want to erase Sector 8 200H 27FH you input 02H to FMS...

Page 82: ...Programming Enable Register FBH Set 1 Bank1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 0 Flash Memory User Programming Mode Selection Bits Others Disable user programming mode 10100101 Enable user programming mode ...

Page 83: ...gn Flag S 0 Operation generates a positive number MSB 0 1 Operation generates a negative number MSB 1 4 Overflow Flag V 0 Operation result is 127 or 128 1 Operation result is 127 or 128 3 Decimal Adjust Flag D 0 Add operation completed 1 Subtraction operation completed 2 Half Carry Flag H 0 No carry out of bit 3 or no underflow into bit 3 by addition or subtraction 1 Addition generated carry out o...

Page 84: ...able mask 1 Enable un mask 5 Interrupt Level 5 IRQ5 Enable Bit 0 Disable mask 1 Enable un mask 4 Interrupt Level 4 IRQ4 Enable Bit 0 Disable mask 1 Enable un mask 3 Interrupt Level 3 IRQ3 Enable Bit 0 Disable mask 1 Enable un mask 2 Interrupt Level 2 IRQ2 Enable Bit 0 Disable mask 1 Enable un mask 1 Interrupt Level 1 IRQ1 Enable Bit 0 Disable mask 1 Enable un mask 0 Interrupt Level 0 IRQ0 Enable B...

Page 85: ...ht bits of the 16 bit instruction pointer address IP15 IP8 The lower byte of the IP address is located in the IPL register DBH IPL Instruction Pointer Low Byte DBH Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is...

Page 86: ...ps A B and C 0 0 0 Group priority undefined 0 0 1 B C A 0 1 0 A B C 0 1 1 B A C 1 0 0 C A B 1 0 1 C B A 1 1 0 A C B 1 1 1 Group priority undefined 6 Interrupt Subgroup C Priority Control Bit 0 IRQ6 IRQ7 1 IRQ7 IRQ6 5 Interrupt Group C Priority Control Bit 0 IRQ5 IRQ6 IRQ7 1 IRQ6 IRQ7 IRQ5 3 Interrupt Subgroup B Priority Control Bit 0 IRQ3 IRQ4 1 IRQ4 IRQ3 2 Interrupt Group B Priority Control Bit 0...

Page 87: ...ding 6 Interrupt Level 6 IRQ6 Request Pending Bit 0 Not pending 1 Pending 5 Interrupt Level 5 IRQ5 Request Pending Bit 0 Not pending 1 Pending 4 Interrupt Level 4 IRQ4 Request Pending Bit 0 Not pending 1 Pending 3 Interrupt Level 3 IRQ3 Request Pending Bit 0 Not pending 1 Pending 2 Interrupt Level 2 IRQ2 Request Pending Bit 0 Not pending 1 Pending 1 Interrupt Level 1 IRQ1 Request Pending Bit 0 Not...

Page 88: ...sed for S3C84I8 F84I8 C84I9 F84I9 4 LCD Display Control Bit 0 Display off cut off the LCD voltage dividing resistors 1 Normal display on 3 2 LCD Duty and Bias Selection Bits 0 0 1 3 duty 1 3 bias COM0 COM2 SEG0 SEG19 0 1 1 4 duty 1 3 bias COM0 COM3 SEG0 SEG19 1 0 1 8 duty 1 4 bias COM0 COM7 SEG0 SEG15 1 1 1 8 duty 1 5 bias COM0 COM7 SEG0 SEG15 1 0 LCD Clock Selection Bits 0 0 fw 27 256 Hz when fw ...

Page 89: ...7 COM4 COM0 3 P3 0 P3 3 P3 4 P3 7 P4 0 P4 3 P4 4 P4 7 P0 0 P0 3 0 0 0 SEG SEG SEG SEG COM COM 0 0 1 Port SEG SEG SEG COM COM 0 1 0 Port Port SEG SEG COM COM 0 1 1 Port Port Port SEG COM COM 1 0 0 Port Port Port Port COM 1 0 1 Port Port Port Port Port 3 SEG3 P2 7 Selection Bit 0 SEG port 1 Normal I O port 2 SEG2 P2 6 Selection Bit 0 SEG port 1 Normal I O port 1 SEG1 P2 5 Selection Bit 0 SEG port 1 ...

Page 90: ...ssing mode only 7 4 Not used for the S3C84I8 F84I8 C84I9 F84I9 must keep always 0 3 Main System Oscillator Control Bit 0 Main System Oscillator RUN 1 Main System Oscillator STOP 2 Sub System Oscillator Control Bit 0 Sub system oscillator RUN 1 Sub system oscillator STOP 1 Not used for the S3C84I8 F84I8 C84I9 F84I9 must keep always 0 0 System Clock Selection Bit 0 Main oscillator select 1 Subsystem...

Page 91: ...de with pull up 1 0 Push pull output mode 1 1 Alternative function mode AD3 input 5 4 P0 2 AD2 COM2 Configration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 Alternative function mode AD2 input 3 2 P0 1 AD1 COM1 Configration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 Alternative function mode AD1 input 1 0 P0 0 AD0 COM0 Configrati...

Page 92: ... addressing mode only 7 4 Not used for the S3C84I8 F84I8 C84I9 F84I9 must keep always 0 3 2 P1 5 T1CAP1 AD6 Configration Bits 0 0 Input mode T1CAP1 input 0 1 Input mode with pull up T1CAP1 input 1 0 Push pull output mode 1 1 Alternative function mode AD6 1 0 P1 4 T1CK1 AD5 Configration Bits 0 0 Input mode T1CK1 input 0 1 Input mode with pull up T1CK1 input 1 0 Push pull output mode 1 1 Alternative...

Page 93: ...function mode T1OUT1 mode 5 4 P1 2 TACAP INT2 Configration Bits 0 0 Input mode Interrupt input INT2 TACAP 0 1 Input mode with pull up Interrupt input INT2 TACAP 1 0 Push pull output mode 1 1 Alternative function mode Not used 3 2 P1 1 TACK BUZ INT1 Configration Bits 0 0 Input mode Interrupt input INT1 TACK 0 1 Input mode with pull up Interrupt input INT1 TACK 1 0 Push pull output mode 1 1 Alternat...

Page 94: ...ending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 2 P1 2 INT2 Interrupt Pending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 1 P1 1 INT1 Interrupt Pending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 0 P1 0 INT0 Interrupt Pending ...

Page 95: ...nterrupt Disable 1 0 Interrupt Enable Falling edge 1 1 Interrupt Enable Rising edge 5 4 P1 2 s Interrupt Enable Disble Selection Bit 0 X Interrupt Disable 1 0 Interrupt Enable Falling edge 1 1 Interrupt Enable Rising edge 3 3 P1 1 s Interrupt Enable Disble Selection Bit 0 X Interrupt Disable 1 0 Interrupt Enable Falling edge 1 1 Interrupt Enable Rising edge 1 0 P1 0 s Interrupt Enable Disble Selec...

Page 96: ...ush pull output mode 1 1 Alternative function mode TxD output 5 4 P2 6 SEG2 RxD Configration Bits 0 0 Input mode RxD input 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode RxD output 3 2 P2 5 SEG1 SCK Configration Bits 0 0 Input mode SCK input 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode SCK output 1 0 ...

Page 97: ...0 Push pull output mode 1 1 Alternative function mode AD7 5 4 P2 2 AD4 T1OUT0 Configration Bits 0 0 Input mode 0 1 Alternative function mode T1OUT0 1 0 Push pull output mode 1 1 Alternative function mode AD4 3 2 P2 1 PWM T1CAP0 Configration Bits 0 0 Input mode T1CAP0 input 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode PWM mode 1 0 P2 0 TBPWM T1CK0 C...

Page 98: ...Pull up resistor enable 5 P2 5 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 4 P1 4 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 3 P2 3 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 2 P2 2 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 1 P2 1 P...

Page 99: ...put mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 5 4 P3 6 SEG10 Configration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 3 2 P3 5 SEG9 Configration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 1 0 P3 4 SEG8 Configration Bits 0 0 In...

Page 100: ...put mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 5 4 P3 2 SEG6 Configration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 3 3 P3 1 SEG5 Configration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 1 0 P3 0 SEG4 Configration Bits 0 0 Inp...

Page 101: ...de 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 5 4 P4 6 COM6 SEG18 Configration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 3 3 P4 5 COM5 SEG17 Configration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 1 0 P4 4 COM4 SEG16 Configration ...

Page 102: ...nput mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 5 4 P4 2 SEG14 Configration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 3 2 P4 1 SEG13 Configration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 1 0 P4 0 SEG12 Configration Bits 0 0...

Page 103: ...n Bits 0 0 0 0 Source page 0 0 0 0 1 Source page 1 0 0 1 0 Source page 2 Other values Don t care NOTES 1 In the S3C84I8 F84I8 microcontroller the internal register file is configured as two pages Page 0 Page 2 The page 0 is used for the general purpose register file and data register 2 In the S3C84I9 F84I9 microcontroller the internal register file is configured as three pages Page 0 2 The page 0 ...

Page 104: ...n Bit 0 Reload from 10 bit up counter overflow 1 Reload from 8 bit up counter overflow 3 PWM Counter Clear Bit 0 No effect 1 Clear the PWM counter when write 2 PWM Counter Enable Bit 0 Stop counter 1 Start Resume countering 1 PWM Overflow Interrupt Enable Bit 8 Bit Overflow 0 Disable interrupt 1 Enable interrupt 0 PWM Overflow Interrupt Pending Bit 0 No interrupt pending when read 0 Clear pending ...

Page 105: ...ess C0H in register set 1 selecting the 8 byte working register slice C0H C7H 2 0 Not used for the S3C84I8 F84I8 C84I9 F84I9 RP1 Register Pointer 1 D7H Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 1 1 0 0 1 Read Write R W R W R W R W R W Addressing Mode Register addressing only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256 byte working regist...

Page 106: ...e 5 SIO Mode Selection Bit 0 Receive only mode 1 Transmit Receive mode 4 Shift Clock Edge Selection Bit 0 Tx at falling edges Rx at rising edges 1 Tx at rising edges Rx at falling edges 3 SIO Counter Clear and Shift Start Bit 0 No action 1 Clear 3 bit counter and start shifting 2 SIO Shift Operation Enable Bit 0 Disable shift and clock counter 1 Enable shift and clock counter 1 SIO Interrupt Enabl...

Page 107: ... Stack Pointer Address High Byte The high byte stack pointer value is the upper eight bits of the 16 bit stack pointer address SP15 SP8 The lower byte of the stack pointer value is located in register SPL D9H The SP value is undefined following a reset SPL Stack Pointer Low Byte D9H Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressi...

Page 108: ...0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 STOP Control Bits 1 0 1 0 0 1 0 1 Enable stop instruction Other values Disable stop instruction NOTE Before execute the STOP instruction You must set this STPCON register as 10100101b Otherwise the STOP instruction will not be executed ...

Page 109: ...0 4 2 Fast Interrupt Level Selection Bits 0 0 0 IRQ0 0 0 1 IRQ1 0 1 0 IRG2 0 1 1 IRQ3 1 0 0 IRQ4 1 0 1 IRQ5 1 1 0 IRQ6 1 1 1 IRQ7 1 Fast Interrupt Enable Bit 0 Disable fast interrupt processing 1 Enable fast interrupt processing 0 Global Interrupt Enable Bit note 0 Disable global interrupt processing 1 Enable global interrupt processing NOTE Following a reset you enable global interrupt processing...

Page 110: ...0 0 fxx 1 0 1 External clock falling edge 1 1 0 External clock rising edge 1 1 1 Counter stop 4 3 Timer 1 0 Operating Mode Selection Bits 0 0 Interval mode 0 1 Capture mode Capture on rising edge OVF can occur 1 0 Capture mode Capture on falling edge OVF can occur 1 1 PWM mode 2 Timer 1 0 Counter Enable Bit 0 No effect 1 Clear the timer 1 0 counter Auto clear bit 1 Timer 1 0 Match Capture Interrup...

Page 111: ... 0 fxx 1 0 1 External clock falling edge 1 1 0 External clock rising edge 1 1 1 Counter stop 4 3 Timer 1 1 Operating Mode Selection Bits 0 0 Interval mode 0 1 Capture mode Capture on rising edge OVF can occur 1 0 Capture mode Capture on falling edge OVF can occur 1 1 PWM mode 2 Timer 1 1 Counter Enable Bit 0 No effect 1 Clear the timer 1 1 counter Auto clear bit 1 Timer 1 1 Match Capture Interrupt...

Page 112: ...Operating Mode Selection Bits 0 0 Interval mode TAOUT mode 0 1 Capture mode capture on rising edge counter running OVF can occur 1 0 Capture mode capture on falling edge counter running OVF can occur 1 1 PWM mode OVF interrupt can occur 3 Timer A Counter Clear Bit 0 No effect 1 Clear the timer A counter Auto clear bit 2 Timer A Overflow Interrupt Enable Bit 0 Disable overflow interrupt 1 Enable ov...

Page 113: ...x 8 1 0 fxx 64 1 1 fxx 256 5 4 Timer B Interrupt Time Selection Bits 0 0 Elapsed time for low data value 0 1 Elapsed time for high data value 1 0 Elapsed time for low and high data values 1 1 Not Used 3 Timer B Interrupt Enable Bit 0 Disable Interrupt 1 Enable Interrupt 2 Timer B Start Stop Bit 0 Stop timer B 1 Start timer B 1 Timer B Mode Selection Bit 0 One shot mode 1 Repeating mode 0 Timer B O...

Page 114: ...te 1 Interrupt pending 4 Timer 1 1 Match Capture Interrupt Pending Bit 0 No interrupt pending 0 Clear pending bit when write 1 Interrupt pending 3 Timer 1 0 Overflow Interrupt Pending Bit 0 No interrupt pending 0 Clear pending bit when write 1 Interrupt pending 2 Timer 1 0 Match Capture Interrupt Pending Bit 0 No interrupt pending 0 Clear pending bit when write 1 Interrupt pending 1 Timer A Overfl...

Page 115: ...it 0 Disable 1 Enable 3 If Parity disable mode PEN 0 location of the 9th data bit to be transmitted in UART mode 2 0 or 1 If Parity enable mode PEN 1 even odd parity selection bit for transmit data in UART mode 2 0 Even parity bit generation for transmit data 1 Odd parity bit generation for transmit data 2 If Parity disable PEN 0 location of the 9th data bit that was received in UART mode 2 0 or 1...

Page 116: ...pt NOTES 1 In mode 2 if the MCE UARTCON 5 bit is set to 1 then the receive interrupt will not be activated if the received 9th data bit is 0 In mode 1 if MCE 1 then the receive interrupt will not be activated if a valid stop bit was not received In mode 0 the MCE UARTCON 5 bit should be 0 2 The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive an...

Page 117: ... Receive Interrupt Pending Flag 0 Not pending 0 Clear pending bit when write 1 Interrupt pending 0 UART Transmit Interrupt Pending Flag 0 Not pending 0 Clear pending bit when write 1 Interrupt pending NOTES 1 In order to clear a data transmit or receive interrupt pending flag you must write a 0 to the appropriate pending bit 2 To avoid programming errors we recommend using load instruction except ...

Page 118: ... 0 Disable watch timer interrupt 1 Enable watch timer interrupt 5 4 Buzzer Signal Selection Bits 0 0 0 5 kHz buzzer BZOUT signal output 0 1 1 kHz buzzer BZOUT signal output 1 0 2 kHz buzzer BZOUT signal output 1 1 4 kHz buzzer BZOUT signal output 3 2 Watch Timer Speed Selection Bits 0 0 0 5 s Interval 0 1 0 25 s Interval 1 0 0 125 s Interval 1 1 1 955 ms Interval 1 Watch Timer Enable Bit 0 Disable...

Page 119: ...he levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more in...

Page 120: ...t logic There are three possible combinations of interrupt structure components called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V1 one source S1 Type 2 One level IRQn one vector V1 multiple sources S1 Sn Type 3 One level IRQn multiple vectors V1 Vn multiple sources S1 Sn Sn 1 Sn ...

Page 121: ...V 1 S 2 Type 2 IRQn S 3 S n V 1 S 1 V 2 S 2 Type 3 IRQn V 3 S 3 V 1 S 1 Type 1 IRQn V n Sn 1 S n Sn 2 Sn m NOTES 1 The number of Sn and Vn value is expandable 2 In the S3C84I8 F84I8 84I9 F84I9 implementation interrupt types 1 and 3 are used Figure 5 1 S3C8 Series Interrupt Types ...

Page 122: ...rmines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and th...

Page 123: ...pt P1 2 external interrupt P1 3 external interrupt S W S W S W S W D6H IRQ5 Watch timer S W D8H DAH IRQ6 SIO receive transmit PWM overflow interrupt S W S W DCH DEH IRQ7 UART data receive UART data transmit S W S W NOTES 1 Within a given interrupt level the lower vector address has high priority For example DCH has higher priority than DEH within the level IRQ5 the priorities within each level are...

Page 124: ...see Figure 5 3 You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H 32 767 0 255 00H 0100H FFH 7FFFH HEX RESET Address Interrupt Area Vector 32 Kbyte 8 192 0 255 00H 0100H FFH 1FFFH HEX RESET Address I...

Page 125: ...ternal interrupt 2 208 D0H P1 1external interrupt 1 206 CEH P1 0 external interrupt 0 202 CAH Timer 1 1 overflow IRQ2 3 200 C8H Timer 1 1 match capture 2 198 C6H Timer 1 0 overflow 1 196 C4H Timer 1 0 match capture 0 194 C2H Timer A overflow IRQ1 1 192 C0H Timer A match capture 0 190 BEH Timer B underflow IRQ0 NOTES 1 Interrupt priorities are identified in inverse order 0 is the highest priority 1...

Page 126: ...IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source The system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Regist...

Page 127: ...e disable settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be sure to include the necessary register file address register pointer information Interrupt Request Register Read only IRQ0 IRQ7 Interrupts Interrupt Mas...

Page 128: ... 1 0 overflow T1DATAH1 T1DATAL1 E6H E7H bank 1 Timer 1 1 match capture T1CON0 T1CON1 E8H E9H bank 1 Timer 1 1 overflow T1CNTH0 T1CNTL0 EAH EBH bank 1 T1CNTH1 T1CNTL1 ECH EDH bank 1 TINTPND E0H bank 1 P1 0 external interrupt IRQ3 P1CONL E9H bank 0 P1 1 external interrupt P1INT EBH bank 0 P1 2 external interrupt P1INTPND EAH bank 0 P1 3 external interrupt P1EDGE F3H bank 0 Watch timer interrupt IRQ4...

Page 129: ... routine which follows a reset operation Although you can manipulate SYM 0 directly to enable and disable interrupts during the normal operation it is recommended to use the EI and DI instructions for this purpose System Mode Register SYM DEH Set 1 R W 7 6 5 4 3 2 1 0 MS B LSB Global interrupt enable bit 0 Disable all interrupts processing 1 Enable all interrupts processing Fast interrupt enable b...

Page 130: ...terrupt level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode NOTE Before IMR register is changed to any value all interrupts must be dis...

Page 131: ... note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 Group A IRQ0 IRQ1 Group B IRQ2 IRQ3 IRQ4 Group C IRQ5 IRQ6 IRQ7 IPR Group B IRQ2 B1 IRQ4 B2 IRQ3 B22 B21 IPR Group A IRQ1 A2 IRQ0 A1 IPR Group C C1 IRQ7 C2 IRQ6 C22 C21 IRQ5 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control ...

Page 132: ...7 1 IRQ6 IRQ7 IRQ5 Subgroup C 0 IRQ6 IRQ7 1 IRQ7 IRQ6 Group B 0 IRQ2 IRQ3 IRQ4 1 IRQ3 IRQ4 IRQ2 Interrupt Priority Register IPR FFH Set 1 Bank 0 R W LSB MSB 7 6 5 4 3 2 1 0 Group priority 0 0 0 Undefined 0 0 1 B C A 0 1 0 A B C 0 1 1 B A C 1 0 0 C A B 1 0 1 C B A 1 1 0 A C B 1 1 1 Undefined D7 D4 D1 Figure 5 8 Interrupt Priority Register IPR ...

Page 133: ...gister at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it Yo...

Page 134: ...executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the S3C84I8 F84I8 C84I9 F84I9 interrupt structure the timer B underflow interrupt IRQ0 belongs to this category of interrupts in which pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine...

Page 135: ...bled EI SYM 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one level is currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The CPU then initiates an interru...

Page 136: ...d 16 bit vector address NOTE A 16 bit vector address always begins at an even numbered ROM address within the range of 00H FFH NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced To do this you must follow these steps 1 Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR 2 Load the IMR...

Page 137: ...ng rotate and shift operations DATA TYPES The CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a workin...

Page 138: ...src Load program memory and increment LDEPD dst src Load external data memory with pre decrement LDCPD dst src Load program memory with pre decrement LDEPI dst src Load external data memory with pre increment LDCPI dst src Load program memory with pre increment LDW dst src Load word POP dst Pop from stack POPUD dst src Pop user stack decrementing POPUI dst src Pop user stack incrementing PUSH src ...

Page 139: ... with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ...

Page 140: ...E dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bi...

Page 141: ...tate right RRC dst Rotate right through carry SRA dst Shift right arithmetic SWAP dst Swap nibbles CPU Control Instructions CCF Complement carry flag DI Disable interrupts EI Enable interrupts IDLE Enter Idle mode NOP No operation RCF Reset carry flag SB0 Set bank 0 SB1 Set bank 1 SCF Set carry flag SRP src Set register pointers SRP0 src Set register pointer 0 SRP1 src Set register pointer 1 STOP ...

Page 142: ...ister can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then...

Page 143: ... has been performed D Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and it cannot be addressed as a test condition H Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out...

Page 144: ... Set to logic one Set or cleared according to operation Value is unaffected x Value is undefined Table 6 3 Instruction Set Symbols Symbol Description dst Destination operand src Source operand Indirect register address prefix PC Program counter IP Instruction pointer FLAGS Flags register D5H RP Register pointer Immediate operand or register address prefix H Hexadecimal number suffix D Decimal numb...

Page 145: ...r addr 0 254 even number only Ir Indirect working register only Rn n 0 15 IR Indirect register or indirect working register Rn or reg reg 0 255 n 0 15 Irr Indirect working register pair only RRp p 0 2 14 IRR Indirect register pair or indirect working register pair RRp or reg reg 0 254 even only where p 0 2 14 X Indexed addressing mode reg Rn reg 0 255 n 0 15 XS Indexed short offset addressing mode...

Page 146: ...1 r2 TCM r1 Ir2 TCM R2 R1 TCM IR2 R1 TCM R1 IM BAND r0 Rb I 7 PUSH R2 PUSH IR2 TM r1 r2 TM r1 Ir2 TM R2 R1 TM IR2 R1 TM R1 IM BIT r1 b B 8 DECW RR1 DECW IR1 PUSHUD IR1 R2 PUSHUI IR1 R2 MULT R2 RR1 MULT IR2 RR1 MULT IM RR1 LD r1 x r2 B 9 RL R1 RL IR1 POPUD IR2 R1 POPUI IR2 R1 DIV R2 RR1 DIV IR2 RR1 DIV IM RR1 LD r2 x r1 L A INCW RR1 INCW IR1 CP r1 r2 CP r1 Ir2 CP R2 R1 CP IR2 R1 CP R1 IM LDC r1 Irr...

Page 147: ...ODE MAP LOWER NIBBLE HEX 8 9 A B C D E F U 0 LD r1 R2 LD r2 R1 DJNZ r1 RA JR cc RA LD r1 IM JP cc DA INC r1 NEXT P 1 ENTER P 2 EXIT E 3 WFI R 4 SB0 5 SB1 N 6 IDLE I 7 STOP B 8 DI B 9 EI L A RET E B IRET C RCF H D SCF E E CCF X F LD r1 R2 LD r2 R1 DJNZ r1 RA JR cc RA LD r1 IM JP cc DA INC r1 NOP ...

Page 148: ... 1110 1 NZ Not zero Z 0 1101 PL Plus S 0 0101 MI Minus S 1 0100 OV Overflow V 1 1100 NOV No overflow V 0 0110 1 EQ Equal Z 1 1110 1 NE Not equal Z 0 1001 GE Greater than or equal S XOR V 0 0001 LT Less than S XOR V 1 1010 GT Greater than Z OR S XOR V 0 0010 LE Less than or equal Z OR S XOR V 1 1111 1 UGE Unsigned greater than or equal C 0 0111 1 ULT Unsigned less than C 1 1011 UGT Unsigned greater...

Page 149: ...ck reference The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Flag settings that may be affected by the instruction Detailed description of the instruction s format execution time ...

Page 150: ... if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 R R 15 R IR opc dst src 3 6 16 R IM Examples Given R1 10H R2 03H C...

Page 151: ...e same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if a carry from the low order nibble occurred Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 R R 05 R IR opc dst src 3 6 06 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH ADD R1 R2 R1 15H R2 03H ADD R1 R2 R1 1CH...

Page 152: ...erwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 R R 55 R IR opc dst src 3 6 56 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH AND R1 R2 R1 02H R2 03H AND R1 R2 R1 02H R2 03H AND 01H 02H Register 01H 01H register 02H 03H AND 01H 02H Register 01H 00H regis...

Page 153: ...rmat Bytes Cycles Opcode Hex Addr Mode dst src opc dst b 0 src 3 6 67 r0 Rb opc src b 1 dst 3 6 67 Rb r0 NOTE In the second byte of the 3 byte instruction formats the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H and register 01H 05H BAND R1 01H 1 R1 06H register 01H 05H BAND 01H 1 R1 Register 01H...

Page 154: ...ytes Cycles Opcode Hex Addr Mode dst src opc dst b 0 src 3 6 17 r0 Rb NOTE In the second byte of the instruction format the destination address is four bits the bit address 0 is three bits and the LSB address value is one bit in length Example Given R1 07H and register 01H 01H BCP R1 01H 1 R1 07H register 01H 01H If the destination working register R1 contains the value 07H 00000111B and the sourc...

Page 155: ...mat Bytes Cycles Opcode Hex Addr Mode dst opc dst b 0 2 4 57 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITC R1 1 R1 05H If the working register R1 contains the value 07H 00000111B the statement BITC R1 1 complements bit one of the destination and leave...

Page 156: ...ected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst b 0 2 4 77 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address 0 is three bits and the LSB address value is one bit in length Example Given R1 07H BITR R1 1 R1 05H If the value of the working register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination register...

Page 157: ...Format Bytes Cycles Opcode Hex Addr Mode dst opc dst b 1 2 4 77 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITS R1 3 R1 0FH If the working register R1 contains the value 07H 00000111B the statement BITS R1 3 sets bit three of the destination register R1...

Page 158: ...yte instruction format the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bit Examples Given R1 07H and register 01H 03H BOR R1 01H 1 R1 07H register 01H 03H BOR 01H 2 R1 Register 01H 07H R1 07H In the first example the destination working register R1 contains the value 07H 00000111B and the source register 01H the value 03H 00000011...

Page 159: ...flags are affected Format note Bytes Cycles Opcode Hex Addr Mode dst src opc src b 0 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRF SKIP R1 3 PC jumps to SKIP location If the working register R1 contains the value 07H 00000111B the statement...

Page 160: ...e Bytes Cycles Opcode Hex Addr Mode dst src opc src b 1 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRT SKIP R1 1 If the working register R1 contains the value 07H 00000111B the statement BTJRT SKIP R1 1 tests bit one in the source register R...

Page 161: ... opc dst b 0 src 3 6 27 r0 Rb opc src b 1 dst 3 6 27 Rb r0 NOTE In the second byte of the 3 byte instruction format the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H 00000111B and register 01H 03H 00000011B BXOR R1 01H 1 R1 06H register 01H 03H BXOR 01H 2 R1 Register 01H 07H R1 07H In the first ex...

Page 162: ...ction CALL RR0 SP 0000H 0000H 1AH 0001H 49H CALL 40H SP 0000H 0000H 1AH 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to the memory location 0000H The PC is then loaded with the value 3521H the address of the first instruc...

Page 163: ...e carry flag is changed to logic zero If C 0 the value of the carry flag is changed to logic one Flags C Complemented No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 EF Example Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register 0D5H changing its value from logic zero to logic one ...

Page 164: ... dst opc dst 2 4 B0 R 4 B1 IR Examples Given Register 00H 4FH register 01H 02H and register 02H 5EH CLR 00H Register 00H 00H CLR 01H Register 01H 02H register 02H 00H In Register R addressing mode the statement CLR 00H clears the destination register 00H value to 00H In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to 00H ...

Page 165: ...at Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 60 R 4 61 IR Examples Given R1 07H and register 07H 0F1H COM R1 R1 0F8H COM R1 R1 07H register 07H 0EH In the first example the destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and logic zeros to logic ones leaving the value 0F8H 1111100...

Page 166: ... A4 R R 6 A5 R IR opc dst src 3 6 A6 R IM Examples 1 Given R1 02H and R2 03H CP R1 R2 Set the C and S flags The destination working register R1 contains the value 02H and the source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative the C and the S flag value...

Page 167: ...ags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst RA 3 12 C2 r Ir Example Given R1 02H R2 03H and register 03H 02H CPIJE R1 R2 SKIP R2 04H PC jumps to SKIP location In this example the working register R1 contains the value 02H the working register R2 the value 03H and the register 03 contains 02H The statement CPIJE R1 R2 SKIP compares the R2 value 02H 0000001...

Page 168: ...affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst RA 3 12 D2 r Ir Example Given R1 02H R2 03H and register 03H 04H CPIJNE R1 R2 SKIP R2 04H PC jumps to SKIP location The working register R1 contains the value 02H the working register R2 the source pointer the value 03H and the general register 03 the value 04H The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 000...

Page 169: ...arry Before DA Bits 4 7 Value Hex H Flag Before DA Bits 0 3 Value Hex Number Added to Byte Carry After DA 0 0 9 0 0 9 00 0 0 0 8 0 A F 06 0 0 0 9 1 0 3 06 0 ADD 0 A F 0 0 9 60 1 ADC 0 9 F 0 A F 66 1 0 A F 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 SUB 0 0 8 1 6 F FA 06 0 SBC 1 7 F 0 0 9 A0 60 1 1 6 F 1 6 F 9A 66 1 Flags C Set if there was a carry from the mos...

Page 170: ...alues 15 and 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using the standard binary arithmetic 0 0 0 1 0 1 0 1 15 0 0 1 0 0 1 1 1 27 0 0 1 1 1 1 0 0 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 42 Assuming the same values ...

Page 171: ...urred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 00 R 4 01 IR Examples Given R1 03H and register 03H 10H DEC R1 R1 02H DEC R1 Register 03H 0FH In the first example if the working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 de...

Page 172: ...Cycles Opcode Hex Addr Mode dst opc dst 2 8 80 RR 8 81 IR Examples Given R0 12H R1 34H R2 30H register 30H 0FH and register 31H 21H DECW RR0 R0 12H R1 33H DECW R2 Register 30H 0FH register 31H 20H In the first example the destination register R0 contains the value 12H and the register R1 the value 34H The statement DECW RR0 addresses R0 and the following operand R1 as a 16 bit word and decrements ...

Page 173: ...g Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 8F Example Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0 disabling interrupt processing...

Page 174: ...of the quotient 1 cleared otherwise V Set if the quotient is 28 or if the divisor 0 cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Examples Given R0 10H R1 03H R2 40H register 40H 80H DIVRR0 R2 R0 03H R1 40...

Page 175: ...r being used as a counter should be set at the one of location 0C0H to 0CFH with SRP SRP0 or SRP1 instruction Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst r opc dst 2 8 jump taken rA RA 8 no jump r 0 to F Example Given R1 02H and LOOP is the label of a relative address SRP 0C0H DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label i...

Page 176: ...errupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when the EI instruction is executed Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 9F Example Given SYM 00H EI If the SYM register contains the value 00H that is if interrupts are currently disabled the statement EI sets the SYM register to 01H enabling all int...

Page 177: ...inted to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 1F Example The diagram below shows an example of how to use an ENTER statement IP Data Address Data 40 41 42 43 Address Data 1F 01 10 Memory Stack 0050 Before 0022 0040 PC 22 IPH IPL Data IP Address Data 40 41 42 43 Address ...

Page 178: ... to by the instruction pointer is then loaded into the program counter and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 16 2F Example The diagram below shows an example of how to use an EXIT statement IP Data Address Data 50 51 Address Data 60 00 Memory Stack 0050 Before 0022 0040 PC 22 IPH IPL Data IP Address Data 60 Address Data M...

Page 179: ...he CPU clock while allowing the system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc 1 4 6F Example The instruction IDLE stops the CPU clock but it does not stop the system clock ...

Page 180: ...dst opc 1 4 rE r r 0 to F opc dst 2 4 20 R 4 21 IR Examples Given R0 1BH register 00H 0CH and register 1BH 0FH INCR0 R0 1CH INC00H Register 00H 0DH INC R0 R0 1BH register 01H 10H In the first example if the destination working register R0 contains the value 1BH the statement INC R0 leaves the value 1CH in that same register The second example shows the effect an INC instruction has on the register...

Page 181: ...H 0FH and register 03H 0FFH INCW RR0 R0 1AH R1 03H INCW R1 Register 02H 10H register 03H 00H In the first example the working register pair RR0 contains the value 1AH in the register R0 and 02H in the register R1 The statement INCW RR0 increments the 16 bit destination by one leaving the value 03H in the register R1 In the second example the statement INCW R1 uses Indirect Register IR addressing m...

Page 182: ...Opcode Hex opc 1 6 BF Example In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupt are enabled When an interrupt occurs the program counter and the instruction pointer are swapped This causes the PC to jump to the address 100H and the IP to keep the return address The last instruction in the service routine is normally a jump to IRET at the...

Page 183: ... 1 The 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 In the first byte of the 3 byte instruction format conditional jump the condition code and the OPCODE are both four bits Examples Given The carry flag C 1 register 00 01H and register 01 20H Secs JP C LABEL_W LABEL_W 1000H PC 1000H JP 00H PC 0120H The first example shows a conditional JP Assuming ...

Page 184: ...28 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement Flags No flags are affected Format note Bytes Cycles Opcode Hex Addr Mode dst cc opc dst 2 6 ccB RA cc 0 to F NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits in length Example Given The carry flag 1 and L...

Page 185: ...rce s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src dst opc src 2 4 rC r IM 4 r8 r R src opc dst 2 4 r9 R r r 0 to F opc dst src 2 4 C7 r lr 4 D7 Ir r opc src dst 3 6 E4 R R 6 E5 R IR opc dst src 3 6 E6 R IM 6 D6 IR IM opc src dst 3 6 F5 IR R opc dst src x 3 6 87 r x r opc src dst x 3 6 97 x r r ...

Page 186: ...H register 01H 20H LD 01H R0 Register 01H 01H R0 01H LD R1 R0 R1 20H R0 01H LD R0 R1 R0 01H R1 0AH register 01H 0AH LD 00H 01H Register 00H 20H register 01H 20H LD 02H 00H Register 02H 20H register 00H 01H LD 00H 0AH Register 00H 0AH LD 00H 10H Register 00H 01H register 01H 10H LD 00H 02H Register 00H 01H register 01H 02 register 02H 02H LD R0 LOOP R1 R0 0FFH R1 0AH LD LOOP R0 R1 Register 31H 0AH ...

Page 187: ...the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R0 06H and general register 00H 05H LDB R0 00H 2 R0 07H register 00H 05H LDB 00H 0 R0 R0 06H register 00H 04H In the first example the destination working register R0 contains the value 06H and the source general register 00H the value 05H The statement L...

Page 188: ...F7 XS rr r 5 opc dst src XLL XLH 4 14 A7 r XL rr 6 opc src dst XLL XLH 4 14 B7 XL rr r 7 opc dst 0000 DAL DAH 4 14 A7 r DA 8 opc src 0000 DAL DAH 4 14 B7 DA r 9 opc dst 0001 DAL DAH 4 14 A7 r DA 10 opc src 0001 DAL DAH 4 14 B7 DA r NOTES 1 The source src or the working register pair rr for formats 5 and 6 cannot use the register pair 0 1 2 For the formats 3 and 4 the destination XS rr and the sour...

Page 189: ...RR2 R0 6DH R2 01H R3 04H LDE R0 01H RR2 R0 contents of external data memory location 0105H 01H RR2 R0 7DH R2 01H R3 04H LDC 01H RR2 R0 11H contents of R0 is loaded into program memory location 0105H 01H 0104H LDE 01H RR2 R0 11H contents of R0 is loaded into external data memory location 0105H 01H 0104H LDC R0 1000H RR2 R0 contents of program memory location 1104H 1000H 0104H R0 88H R2 01H R3 04H L...

Page 190: ...memory and LDED refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 10 E2 r Irr Examples Given R6 10H R7 33H R8 12H program memory location 1033H 0CDH and external data memory location 1033H 0DDH LDCD R8 RR6 0CDH contents of program memor...

Page 191: ...and LDEI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 10 E3 r Irr Examples Given R6 10H R7 33H R8 12H program memory locations 1033H 0CDH and 1034H 0C5H external data memory locations 1033H 0DDH and 1034H 0D5H LDCI R8 RR6 0CDH cont...

Page 192: ...he source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes Irr an even number for program memory and an odd number for external data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 2 14 F2 Irr r Examples Given R0 77H R6 30H and R7 00H LDCPD RR6 R0 RR6 RR6 1 77H the contents of R0 is loaded int...

Page 193: ...are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 2 14 F3 Irr r Examples Given R0 7FH R6 21H and R7 0FFH LDCPI RR6 R0 RR6 bRR6 1 7FH the contents of R0 is loaded into program memory ...

Page 194: ...03H and register 03H 0FH LDW RR6 RR4 R6 06H R7 1CH R4 06H R5 1CH LDW 00H 02H Register 00H 03H register 01H 0FH register 02H 03H register 03H 0FH LDW RR2 R7 R2 03H R3 0FH LDW 04H 01H Register 04H 03H register 05H 0FH LDW RR6 1234H R6 12H R7 34H LDW 02H 0FEDH Register 02H 0FH register 03H 0EDH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H ...

Page 195: ...t if MSB of the result is a 1 cleared otherwise V Cleared D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Examples Given Register 00H 20H register 01H 03H register 02H 09H register 03H 06H MULT 00H 02H Register 00H 01H register 01H 20H register 02H 09H MULT 00H 01H Register 00H 00H register 01H 0C0H MULT 00H 30H Register 0...

Page 196: ... the program counter The instruction pointer is then incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 10 0F Example The following diagram shows an example of how to use the NEXT instruction Data 01 30 Before After 0045 1P Address Data 0130 PC 43 44 45 Address H Address L Address H Address Data Memory 130 Routine 0043 1P Address Data 0120 PC 43 44 45 Address H Add...

Page 197: ...are executed in sequence in order to affect a timing delay of variable duration Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 FF Example When the instruction NOP is executed in a program no operation occurs Instead there happens a delay in instruction execution time which is of approximately one machine cycle per each NOP instruction encountered ...

Page 198: ...cted Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 R R 6 45 R IR opc dst src 3 6 46 R IM Examples Given R0 15H R1 2AH R2 01H register 00H 08H register 01H 37H and register 08H 8AH OR R0 R1 R0 3FH R1 2AH OR R0 R2 R0 37H R2 01H register 01H 37H OR 00H 01H Register 00H 3FH register 01H 37H OR 01H 00H Register 00H 08H register 01H 0BFH OR 00H 02H ...

Page 199: ...pc dst 2 8 50 R 8 51 IR Examples Given Register 00H 01H register 01H 1BH SPH 0D8H 00H SPL 0D9H 0FBH and stack register 0FBH 55H POP 00H Register 00H 55H SP 00FCH POP 00H Register 00H 01H register 01H 55H SP 00FCH In the first example the general register 00H contains the value 01H The statement POP 00H loads the contents of the location 00FBH 55H into the destination register 00H and then incremen...

Page 200: ... decremented Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 8 92 R IR Example Given Register 00H 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00H Register 00H 41H register 02H 6FH register 42H 6FH 02H If the general register 00H contains the value 42H and the register 42H the value 6FH the statement POPUD 02H 00H loads ...

Page 201: ...pointer is then incremented Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 8 93 R IR Example Given Register 00H 01H and register 01H 70H POPUI 02H 00H Register 00H 02H register 01H 70H register 02H 70H If the general register 00H contains the value 01H and the register 01H the value 70H the statement POPUI 02H 00H loads the value 70H into the destination...

Page 202: ... internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Examples Given Register 40H 4FH register 4FH 0AAH SPH 00H and SPL 00H PUSH 40H Register 40H 4FH stack register 0FFH 4FH SPH 0FFH SPL 0FFH PUSH 40H Register 40H 4FH register 4FH 0AAH stack register 0FFH 0AAH SPH 0FFH SPL 0FFH In the first example if the stack pointer contains the value 0000H and the general register 40H t...

Page 203: ...stack pointer Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 3 8 82 IR R Example Given Register 00H 03H register 01H 05H and register 02H 1AH PUSHUD 00H 01H Register 00H 02H register 01H 05H register 02H 05H If the user stack pointer the register 00H for example contains the value 03H the statement PUSHUD 00H 01H decrements the user stack pointer by one le...

Page 204: ... user stack pointer Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 3 8 83 IR R Example Given Register 00H 03H register 01H 05H and register 04H 2AH PUSHUI 00H 01H Register 00H 04H register 01H 05H register 04H 05H If the user stack pointer the register 00H for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by ...

Page 205: ...g RCF RCF Operation C 0 The carry flag is cleared to logic zero regardless of its previous value Flags C Cleared to 0 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 CF Example Given C 1 or 0 The instruction RCF clears the carry flag C to logic zero ...

Page 206: ...ement to be executed is the one that is addressed by the new program counter value Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 10 AF Example Given SP 00FCH SP 101AH and PC 1234 RET PC 101AH SP 00FEH The RET instruction pops the contents of the stack pointer location 00FCH 10H into the high byte of the program counter The stack pointer then pops the value in the location 00FEH ...

Page 207: ...f the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 90 R 4 91 IR Examples Given Register 00H 0AAH register 01H 02H and register 02H 17H RL 00H Register 00H 55H C 1 RL 01H Register 01H 02H register 02H 2EH C 0 In the first exam...

Page 208: ...metic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 10 R 4 11 IR Examples Given Register 00H 0AAH register 01H 02H and register 02H 17H C 0 RLC 00H Register 00H 54H C 1 RLC 01H Register 01H 02H register 02H 2EH C 0 In the first example if the general regist...

Page 209: ...curred that is if the sign of the destination is changed during the rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 E0 R 4 E1 IR Examples Given Register 00H 31H register 01H 02H and register 02H 17H RR 00H Register 00H 98H C 1 RR 01H Register 01H 02H register 02H 8BH C 1 In the first example if the general register 00H contains the valu...

Page 210: ...tic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 C0 R 4 C1 IR Examples Given Register 00H 55H register 01H 02H register 02H 17H and C 0 RRC 00H Register 00H 2AH C 1 RRC 01H Register 01H 02H register 02H 0BH C 1 In the first example if the general register ...

Page 211: ...lears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting the bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 4F Example The statement SB0 clears FLAGS 0 to 0 selecting the bank 0 register addressing ...

Page 212: ...e selecting the bank 1 register addressing in the set 1 area of the register file NOTE Bank 1 is not implemented in some KS88 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 5F Example The statement SB1 sets FLAGS 0 to 1 selectin the bank 1 register addressing if bank 1 is implemented in the microcontrooler s internla register file ...

Page 213: ...that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 R R 6 35 R IR opc...

Page 214: ...8 SCF Set Carry Flag SCF Operation C 1 The carry flag C is set to logic one regardless of its previous value Flags C Set to 1 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 DF Example The statement SCF sets the carry flag to 1 ...

Page 215: ... S Set if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 D0 R 4 D1 IR Examples Given Register 00H 9AH register 02H 03H register 03H 0BCH and C 1 SRA 00H Register 00H 0CD C 0 SRA 02H Register 02H 03H register 03H 0DEH C 0 In the first example if the general register 00H contains the value 9AH 10011010...

Page 216: ...elected register pointer are written unless both register pointers are selected RP0 3 is then cleared to logic zero and RP1 3 is set to logic one Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode src opc src 2 4 31 IM Examples The statement SRP 40H sets the register pointer 0 RP0 at the location 0D6H to 40H and the register pointer 1 RP1 at the location 0D7H to 48 H The statemen...

Page 217: ...egisters peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc 1 4 7F Example The stat...

Page 218: ...herwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 R R 6 25 R IR opc dst src 3 6 26 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH SUB R1 R2 R1 0FH R2 ...

Page 219: ...t bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 F0 R 4 F1 IR Examples Given Register 00H 3EH register 02H 03H and register 03H 0A4H SWAP 00H Register 00H 0E3H SWAP 02H Register 02H 03H register 03H 4AH In the first example if the general register 00H contains the value 3EH 00111110B the statement SWAP 00H swaps the low...

Page 220: ...s cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 R R 6 65 R IR opc dst src 3 6 66 R IM Examples Given R0 0C7H R1 02H R2 12H register 00H 2BH register 01H 02H and register 02H 23H TCM R0 R1 R0 0C7H R1 02H Z 1 TCM R0 R1 R0 0C7H R1 02H register 02H 23H Z 0 TCM 00H 01H Register 00H 2BH register 01H 02H Z 1 TCM...

Page 221: ...fected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 R R 6 75 R IR opc dst src 3 6 76 R IM Examples Given R0 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H TM R0 R1 R0 0C7H R1 02H Z 0 TM R0 R1 R0 0C7H R1 02H register 02H 23H Z 0 TM 00H 01H Register 00H 2BH register 01H 02H Z 0 TM 00H 01H Register 00H 2BH register 01H...

Page 222: ...an be released by an internal interrupt including a fast interrupt Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4n 3F n 1 2 3 Example The following sample program structure shows the sequence of operations that follow a WFI statement EI WFI Next instruction Main program Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed Enable global ...

Page 223: ... Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 B2 r r 6 B3 r lr opc src dst 3 6 B4 R R 6 B5 R IR opc dst src 3 6 B6 R IM Examples Given R0 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H XOR R0 R1 R0 0C5H R1 02H XOR R0 R1 R0 0E4H R1 02H register 02H 23H XOR 00H 01H Register 00H 29H register 01H 02H XOR 00H 01H Register 00H 08H re...

Page 224: ...nect the external oscillator or clock source to the on chip clock circuit SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal or ceramic resonator oscillation source or an external clock source Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 System clock control register CLKCON Oscillator cont...

Page 225: ...watch timer is operating with sub system clock In Idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers and timer counters Idle mode is released by a reset or by an external or internal interrupt 1 8 1 4096 Frequency Dividing Circuit Stop Release Selector 1 fX fXT Stop Sub system Oscillator Circuit INT OSCCON 0 OSCCON 3 OSCCON 2 Selector 2 STPCON STOP OSC in...

Page 226: ...cted as the CPU clock If necessary you can then increase the CPU clock speed fxx 8 fxx 2 or fxx 1 System Clock Control Register CLKCON D4H Set 1 R W 7 6 5 4 3 2 1 0 MSB LSB Not used must keep always 0 Not used must keep always 0 Divide by selection bits for CPU clock frequency 00 fXX 16 01 fXX 8 10 fXX 2 11 fXX 1 non divided NOTE The fxx can be generated by both main system and sub system oscillat...

Page 227: ...Oscillator Control Register OSCCON F2H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 LSB Not used must keep always 0 System clock selection bit 0 Main oscillator select 1 Subsystem oscillator select Not used must keep always 0 Subsystem oscillator control bit 0 Subsystem oscillator RUN 1 Subsystem oscillator STOP Mainsystem oscillator control bit 0 Mainsystem oscillator RUN 1 Mainsystem oscillator STOP NOTE MS...

Page 228: ...re then reset to their default hardware values In summary the following sequence of events occurs during a reset operation Interrupt is disabled The watchdog function basic timer is enabled Ports 0 4 are set to input mode Peripheral control and data registers are disabled and reset to their default hardware values The program counter PC is loaded with the program reset address in the ROM 0100H Whe...

Page 229: ...1 0 Timer B control register TBCON 208 D0H 0 0 0 0 0 0 0 0 Timer B data register high byte TBDATAH 209 D1H 1 1 1 1 1 1 1 1 Timer B data register low byte TBDATAL 210 D2H 1 1 1 1 1 1 1 1 Basic timer control register BTCON 211 D3H 0 0 0 0 0 0 0 0 Clock Control register CLKCON 212 D4H 0 0 0 0 0 0 0 0 System flags register FLAGS 213 D5H x x x x x x 0 0 Register pointer 0 RP0 214 D6H 1 1 0 0 0 Register...

Page 230: ...igh byte P2CONH 234 EAH 0 0 0 0 0 0 0 0 Port 2 control register low byte P2CONL 235 EBH 0 0 0 0 0 0 0 0 Port 3 control register high byte P3CONH 238 EEH 0 0 0 0 0 0 0 0 Port 3 control register low byte P3CONL 239 EFH 0 0 0 0 0 0 0 0 Port 4 control register high byte P4CONH 240 F0H 0 0 0 0 0 0 0 0 Port 4 control register low byte P4CONL 241 F1H 0 0 0 0 0 0 0 0 Oscillator control register OSCCON 242...

Page 231: ... 0 counter register low byte T1CNTL0 235 EBH 0 0 0 0 0 0 0 0 Timer 1 1 counter register high byte T1CNTH1 236 ECH 0 0 0 0 0 0 0 0 Timer 1 1 counter register low byte T1CNTL1 237 EDH 0 0 0 0 0 0 0 0 UART baud rate data register high BRDATAH 238 EEH 1 1 1 1 1 1 1 1 UART baud rate data register low BRDATAL 239 EFH 1 1 1 1 1 1 1 1 SIO pre scalar register SIOPS 240 F0H 0 0 0 0 0 0 0 0 SIO data register...

Page 232: ...e CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H and 0101H Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller s current internal operating mode The...

Page 233: ... was entered There are two ways to release idle mode 1 Execute a reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slow clock fxx 16 because CLKCON 4 and CLKCON 3 are cleared to 00B If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled int...

Page 234: ...ly P0 0 P0 3 can be used as COM0 COM3 AD0 AD3 1 Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up resistor Alternatively P1 0 P1 5 can be used as INT0 INT3 TAOUT TACK TACAP T1OUT1 T1CK1 T1CAP1 AD5 AD6 2 Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up Alternately...

Page 235: ...for ports 0 1 2 3 and 4 have the general format shown in Table 9 2 Table 9 2 Port Data Register Summary Register Name Mnemonic Decimal Hex Location R W Port 0 data register P0 224 E0H Set 1 Bank 0 R W Port 1 data register P1 225 E1H Set 1 Bank 0 R W Port 2 data register P2 226 E2H Set 1 Bank 0 R W Port 3 data register P3 227 E3H Set 1 Bank 0 R W Port 4 data register P4 228 E4H Set 1 Bank 0 R W ...

Page 236: ... 0 Port 0 Control Register P0CON Port 0 has one 8 bit control registers P0CON for P0 0 P0 3 A reset clears the P0CON registers to 00H configuring all pins to input modes You use control registers settings to select input or output mode push pull and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 0...

Page 237: ... Push pull output mode 1 1 Alternative function mode ADC2 input 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 Alternative function mode ADC1 input 1 0 P0 0 ADC0 COM0 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 Alternative function mode ADC0 input 0 1 Input mode with pull up 0 1 Input mode with pull up 3 2 P0 1 ADC1 COM1Conf...

Page 238: ...the associated peripheral module Port 1 Interrupt Enable Pending and Edge Selection Registers P1INT P1INTPND To process external interrupts at the port 1 pins three additional control registers are provided the port 1 interrupt enable register P1INT EAH SET1 BANK 0 the port 1 interrupt pending bits P1INTPND EBH SET1 BANK 0 The port 1 interrupt pending register bits lets you check for interrupt pen...

Page 239: ... MSB LSB 7 6 P1 3 T1OUT1 INT3 Configuration Bits 0 0 Input mode Interrupt input INT3 0 1 Input mode with pull up Interrupt input INT3 1 0 Push pull output mode 1 1 Alternative function mode T1OUT0 output 5 4 P1 2 TACAP INT2 Configuration Bits 0 0 Input mode Interrupt input INT2 TACAP 0 1 Input mode with pull up Interrupt input INT2 TACAP 1 0 Push pull output mode 1 1 Alternative function mode Not ...

Page 240: ...P1 2 INT2 Interrupt Pending bit 0 Interrupt request is not pending pending bit clear when write 0 1 P1 1 INT1 Interrupt Pending bit 0 Interrupt request is not pending pending bit clear when write 0 0 P1 0 INT0 Interrupt Pending bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 1 Interrupt request is pending 1 Interrupt request is pending 1 Interru...

Page 241: ... Port 2 pins are accessed directly by writing or reading the port 2 data register P2 at location E2H in set 1 bank 0 P2 0 P2 7 can serve as digital inputs outputs push pull or you can configure the following alternative functions General purpose digital I O Alternative function ADC4 ADC7 SI T1CAP0 T1OUT0 T1CK0 TBPWM PWM Port 2 Control Register P2CONH P2CONL Port 2 has two 8 bit control registers P...

Page 242: ... RxD Configuration Bits 0 0 Input mode 0 1 Alternative function mode Not used 3 2 P2 5 SEG1 SCK Configuration Bits 0 0 Input mode 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode SCK output 1 0 P2 4 SEG0 SO Configuration Bits 0 0 Input mode 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode SO output 1 0 Push...

Page 243: ...T1OUT0 Configuration Bits 0 0 Input mode 0 1 Alternative function mode T1OUT1 1 0 Push pull output mode 1 1 Alternative function mode AD4 7 6 P2 1 PWM T1CAP0 Configuration Bits 0 0 Input mode T1CAP0 0 1 Alternative function mode T1CAP0 1 0 Push pull output mode 1 1 Alternative function mode PWM 7 6 P2 0 TBPWM T1CK0 Configuration Bits 0 0 Input mode T1CK0 0 1 Alternative function mode T1CK0 1 0 Pus...

Page 244: ...0 Pull up resistor disable 1 Pull up resistor enable 4 P2 4 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 3 P2 3 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 2 P2 2 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 1 P2 1 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pul...

Page 245: ...le the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 3 control registers must also be enabled in the associated peripheral module Port 3 Control Register High Byte P3CONH EEH Set1 Bank0 R W Reset value 00 7 6 5 4 3 2 1 0 MSB LSB 7 6 P3 7 SEG11 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 ...

Page 246: ...in output 5 4 P3 2 SEG7 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 3 2 P3 1 SEG7 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 1 0 P3 0 SEG7 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open d...

Page 247: ...that any alternative peripheral I O function you configure using the port 4 control registers must also be enabled in the associated peripheral module Port 4 Control Register High Byte P4CONH F0H Set1 Bank0 R W Reset value 00 7 6 5 4 3 2 1 0 MSB LSB 7 6 P4 7 COM7 SEG19 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 0 0 Input ...

Page 248: ...ain output 5 4 P4 2 SEG14 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 3 2 P4 1 SEG13 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 1 0 P4 0 SEG12 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel op...

Page 249: ...t 1 D3H read write BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function It is located in set 1 address D3H and is read write addressable using register addressing mode A reset clears BTCON to 00H This enables the watchdog func...

Page 250: ...lear bit 0 No effect 1 Clear divider Basic timer counter clear bit 0 No effect 1 Clear BTCNT Basic timer input clock selection bit 00 fxx 4096 01 fxx 1024 10 fxx 128 11 fxx 1 Not used Watchdog timer enable bit 1010B Disable watchdog function Other value Enable watchdog function Figure 10 1 Basic Timer Control Register BTCON ...

Page 251: ...ken by a BTCNT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop mode has been released by an external interrupt In Stop mode whenever a reset or an external interrupt occurs the oscillator starts T...

Page 252: ...lation stabilization interval until bit 4 of the basic timer counter overflows MUX fxx 4096 DIV fxx 1024 fxx 128 fxx Bits 3 2 Bit 0 Basic Timer Control Register Write 1010xxxxB to disable Clear Bit 1 RESET or STOP Data Bus 8 Bit Up Counter BTCNT Read Only Start the CPU note OVF RESET R Figure 10 2 Basic Timer Block Diagram ...

Page 253: ...ith a rising or falling edge trigger at the TACAP pin PWM mode TAPWM Timer A has the following functional components Clock frequency divider fxx divided by 1024 256 or 64 with multiplexer External clock input pin TACK 8 bit counter TACNT 8 bit comparator and 8 bit reference data register TADATA I O pins for capture input TACAP or PWM or match output TAOUT Timer A overflow interrupt IRQ1 vector C2H...

Page 254: ...rval timer mode a match signal is generated when the counter value is identical to the value written to the Timer A data register TADATA In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from 00H Although you can use the match signal to generate a timer A overflow interrupt interrupts are not typically us...

Page 255: ...errupt IRQ1 vector C0H you must write TACON 1 to 1 To generate the exact time interval you should write TACON 3 and 0 to 1 which cleared counter and interrupt pending bit When interrupt service routine is served the pending condition must be cleared by software by writing a 0 to the interrupt pending bit TINTPND 0 or TINTPND 1 Timer A Control Register TACON 00 Interval mode TAOUT mode E1H Set 1 Ba...

Page 256: ...ear Match TACON 7 6 f xx 1024 f xx 256 f xx 64 TACK TACON 2 Pending TACON 3 Overflow TAOVF TACAP TAOUT TAPWM TINTPND 0 TACON 5 4 Data Bus 8 Data Bus 8 M U X M U X 8 bit Up Counter Read Only 8 bit Comparator Timer A Buffer Reg Timer A Data Register Read Write M U X TACON 1 Pending TAINT TINTPND 1 TACON 0 TACON 5 4 M U X Figure 11 2 Timer A Functional Block Diagram ...

Page 257: ...t can be used as the programmable buzz signal generator that makes a sound with a various frequency from 200Hz to 20KHz These various frequencies can be used to generate a melody sound Timer B has two functions As a normal interval timer generating a timer B interrupt at programmed time intervals To generate a programmable carrier pulse for a remote control signal at P2 0 BLOCK DIAGRAM TBCON 6 fxx...

Page 258: ...time for high data value 10 Elapsed time for low and high data value 11 Invaild setting Timer B start stop bit 0 Stop timer B 1 Start timer B Timer B interrupt enable bit 0 Disable interrupt 1 Enable interrupt Timer B output flip flop control bit 0 T FF is low 1 T FF is high Figure 11 4 Timer B Control Register TBCON Timer B Data High Byte Register TBDATAH D1H Set 1 Bank 0 R W LSB MSB 7 6 5 4 3 2 ...

Page 259: ...1 x 1 fx 0H TBDATAH 100H where fx The selected clock When T FF 1 tLOW TBDATAH 1 x 1 fx 0H TBDATAH 100H where fx The selected clock tHIGH TBDATAL 1 x 1 fx 0H TBDATAL 100H where fx The selected clock To make tLOW 24 us and tHIGH 15 us fOSC 4 MHz fx 4 MHz 4 1 MHz When T FF 0 tLOW 24 us TBDATAL 1 fx TBDATAL 1 x 1us TBDATAL 23 tHIGH 15 us TBDATAH 1 fx TBDATAH 1 x 1us TBDATAH 14 When T FF 1 tHIGH 15 us ...

Page 260: ...FH T FF 0 TBDATAL 00H TBDATAH 00H T FF 1 TBDATAL 00H TBDATAH 00H High Low Low High Timer B Clock T FF 1 TBDATAL DFH TBDATAH 1FH T FF 0 TBDATAL DFH TBDATAH 1FH T FF 1 TBDATAL 7FH TBDATAH 7FH T FF 0 TBDATAL 7FH TBDATAH 7FH 0H 100H 200H E0 H 20H 20H E0 H 80H 80H 80H 80H Figure 11 6 Timer B Output Flip Flop Waveforms in Repeat Mode ...

Page 261: ...8 795 µs Timer B is used in repeat mode Oscillation frequency is 16 MHz 0 0625 µs fx fxx 4 4MHz 0 25 µs TBDATAH 8 795 µs 0 25 µs 35 18 TBDATAL 17 59 µs 0 25 µs 70 36 Set P2 0 to TBPWM mode ORG 0100H Reset address START DI LD TBDATAL 35 1 Set 17 5 µs LD TBDATAH 70 1 Set 8 75 µs LD TBCON 00100111B Clock Source fxx 4 Disable Timer B interrupt Select repeat mode for Timer B Start Timer B operation Set...

Page 262: ... 4 MHz fx 1 4 clock 1 µs TBDATAH 40 µs 1 µs 40 TBDATAL 1 Set P2 0 to TBPWM mode ORG 0100H Reset address START DI LD TBDATAH 40 1 Set 40 µs LD TBDATAL 1 Set any value except 00H LD TBCON 00010001B Clock Source fxx 4 Disable Timer B interrupt Select one shot mode for Timer B Stop Timer B operation Set Timer B output flip flop T FF high LD P2CONL 03H Set P2 0 to TBPWM mode PULSE_OUT LD TBCON 00000101...

Page 263: ... interrupt SYM LD IMR 00000010b Enable IRQ1 interrupt LD SPH 00000000b Set stack area LD SPL 00000000b LD BTCON 10100011b Disable watch dog LD P1CONL 0ABH Enable TAOUT output SB1 LD TADATA 80h LD TACON 01001010b Match interrupt enable 6 55 ms duration 10 MHz x tal SB0 EI MAIN MAIN ROUTINE JR T MAIN TAMC_INT Interrupt service routine IRET TAOV_INT Interrupt service routine IRET END ...

Page 264: ...ast interrupt LD IMR 00000001b Enable IRQ0 interrupt LD SPH 00000000b Set stack area LD SPL 00000000b LD BTCON 10100011b Disable Watch dog LD P2CONL 03H Enable TBPWM output LD TBDATAH 80h LD TBDATAL 80h LD TBCON 11101110b Enable interrupt fxx 256 Repeat Duration 6 605ms 10 MHz x tal EI MAIN MAIN ROUTINE JR T MAIN TBUN_INT Interrupt service routine IRET END ...

Page 265: ... port with T1OUT0 T1OUT1 pin Timer 1 0 1 has the following functional components Clock frequency divider fxx divided by 1024 256 64 8 1 with multiplexer External clock input pin T1CK0 T1CK1 A 16 bit counter T1CNTH0 L0 T1CNTH1 L1 a 16 bit comparator and two 16 bit reference data register T1DATAH0 L0 T1DATAH1 L1 I O pins for capture input T1CAP0 T1CAP1 or match output T1OUT0 T1OUT1 Timer 1 0 overflo...

Page 266: ... register T1DATAH1 and T1DATAL1 The match signal generates a timer 1 1 match interrupt T1INT1 vector C8H and clears the counter value Capture Mode In capture mode for timer 1 0 a signal edge that is detected at the T1CAP0 pin opens a gate and loads the current counter value into the timer 1 data registers T1DATAH0 T1DATAL0 for rising edge or falling edge You can select rising or falling edge to tr...

Page 267: ...imer 1 0 1 overflow interrupt Enable the timer 1 0 1 match capture interrupt T1CON0 is located in set 1 and Bank 1 at address E8H and is read write addressable using Register addressing mode T1CON1 is located in set 1 and Bank 1 at address E9H and is read write addressable using Register addressing mode A reset clears T1CON0 T1CON1 to 00H This sets timer 1 0 1 to normal interval timer mode selects...

Page 268: ...ce selection bit 000 fxx 1024 001 fxx 256 010 fxx 64 011 fxx 8 100 fxx 101 External clock falling edge 110 External clock rising edge 111 Counter stop Timer 1 operating mode selection bit 00 Interval mode 01 Capture mode capture on rising edge OVF can occur 10 Capture mode capture on falling edge OVF can occur 11 PWM mode Timer 1 match capture interrupt enable bit 0 Disable interrupt 1 Enable inte...

Page 269: ...nterrupt pending bit 0 No interrupt pending 1 Interrrupt pending Timer 1 0 overflow interrupt pending bit 0 No interrupt pending 1 Interrrupt pending Timer 1 0 match capture interrupt pending bit 0 No interrupt pending 1 Interrrupt pending Timer 1 1 overflow interrupt pending bit 0 No interrupt pending 1 Interrrupt pending Timer 1 1 match capture interrupt pending bit 0 No interrupt pending 1 Inte...

Page 270: ...ing bit is located at TINTPND register Clear Match T1CON 7 5 T1CON 0 Pending T1CON 2 Overflow T1OVF T1CAP T1OUT T1PWM TINTPND T1CON 4 3 T1CON 4 3 Data Bus 8 Data Bus 8 M U X M U X 16 bit Up Counter Read Only 16 bit Comparator 16 bit Timer Buffer 16 bit Timer Data Register T1DATAH L M U X T1CON 1 Pending T1INT TINTPND M U X Figure 12 3 Timer 1 0 1 Functional Block Diagram ...

Page 271: ...obal Fast interrupt LD IMR 00001000b Enable IRQ2 interrupt LD SPH 00000000b Set stack area LD SPL 00000000b LD BTCON 10100011b Disable Watch dog SB1 LD T1CON0 01000110b Enable interrupt fxx 64 Interval Interval 1 536 ms 10 MHz x tal LDW T1DATAH0 00F0h T1DATAH0 00h T1DATAL0 F0h SB0 EI MAIN MAIN ROUTINE JR T MIAN TIM1_INT Interrupt service routine IRET END ...

Page 272: ...MCON 3 to 1 You can select a clock for the PWM counter by set PWMCON 6 7 Clocks which you can select are fOSC 64 fOSC 8 fOSC 2 fOSC 1 FUNCTION DESCRIPTION PWM The 10 bit PWM circuits have the following components 8 bit comparator and extension cycle circuit 8 bit reference data register PWMDATAH 7 0 2 bit extension data register PWMDATAL 1 0 PWM output pins P1 5 PWM PWM Counter To determine the PW...

Page 273: ...ut signal toggles to Low level whenever the 8 bit counter matches the reference data register PWMDATAH If the value in the PWMDATAH register is not zero an overflow of the 8 bits of counter causes the PWM output to toggle to High level In this way the reference value written to the reference data register determines the module s base duty cycle The value in the lower 2 bits of PWMDATAL counter is ...

Page 274: ... Data Register PWMDATAL 1 0 PWMDATAL Bit Bit1 Bit0 Stretched Cycle Number 00 01 2 10 1 3 11 1 2 3 250 ns 250 ns 8 ms 8 ms 250 ns 0H 100H 200 4 MHz 00000000B xxxxxx00B 00000001B xxxxxx00B 10000000B xxxxxx00B 11111111B xxxxxx00B PWM Clock Register Values PWMDATAH PWMDATAL PWM Data Figure 13 1 10 Bit PWM Basic Waveform ...

Page 275: ...S3C84I8 F84I8 C84I9 F84I9 13 4 1st 2nd 3th 4th 1st 2nd 3th 4th 500 ns 750 ns 0H 40H 4 MHz 0H 40H PWM Clock 4 MHz 00000010B xxxxxx01B PWMDATA 00001001B xxxxxx01 B Basic waveform Extended waveform Figure 13 2 10 Bit Extended PWM Waveform ...

Page 276: ...PWMCON bits to logic zero disabling the entire PWM module 7 6 5 4 3 2 1 0 LSB MSB PWM Control Register PWMCON F5H R W Reset 00H PWM input clock selection bits 00 fOSC 64 01 fOSC 8 10 fOSC 2 11 fOSC 1 PWM counter clear bit 0 No effect 1 Clear the PWM counter PWM counter enable bit 0 Stop counter 1 Start resume countering PWM OVF interrupt enable bit 0 Disable interrupt 1 Enable interrupt PWM OVF in...

Page 277: ...ion Data Buffer 2 bit Extend bit PWMDATAL 8 bit up counter PWMDATAH 8 bit Data Buffer 8 bit Data Register F3H PWMCON 3 clear 8 bit up counter overflow DATA BUS 7 0 F3H Set1 Bank1 PWMDATAH P2 1 PWM 2 bit Counter 8 bit Counter PWMCON 2 MUX f OSC 64 PWMCON 6 7 Set1 Bank1 F4H PWMDATAL 1 0 f OSC 8 f OSC 2 f OSC Figure 13 4 PWM Functional Block Diagram ...

Page 278: ...itialize System and Peripherals ORG 0100H RESET DI disable interrupt LD BTCON 10100011B Watchdog disable LD P2CONL 00001100B Configure P2 1 PWM output LD PWMCON 00000110B fOSC 64 counter interrupt enable LD PWMDATAH 80H LD PWMDATAL 0 EI Enable interrupt Main loop MAIN JR t MAIN Interrupt Service Routines INT_PWM PWM interrupt service routine AND PWMCON 11111110B pending bit clear IRET END ...

Page 279: ...le data transmission rates you can select an internal or external clock source PROGRAMMING PROCEDURE To program the SIO module follow these basic steps 1 Configure the I O pins at port 2 SO SCK SI by loading the appropriate value to the P2CONL H Register 2 Load an 8 bit value to the SIOCON control register to properly configure the serial I O module In this operation SIOCON 2 must be set to 1 to e...

Page 280: ... operation and the interrupt are disabled The selected data direction is MSB first LSB MSB SIO CONTROL REGISTERS SIOCON F2H Set 1 Bank 1 R W Reset 00H SIOinterrupt enable bit 0 Disable SIO interrupt 1 Enable SIO interrupt SIO Interrupt pending bit 0 No interrupt pending 0 Clear pending condition when write 1 Interrupt is pending 7 6 5 4 3 2 1 0 SIO shift clock select bit 0 Internal clock P S clock...

Page 281: ...nput clock SIO Pre Scaler Registers SIOPS F0H SET1 Bank 1 R W LSB MSB 7 6 5 4 3 2 1 0 Baud Rate XIN 4 SIOPS 1 Figure 14 2 SIO Pre Scaler Register SIOPS SIO INT Pending 3 Bit Counter Clear SIOCON 0 MUX 8 Bit SIO Shift Buffer SIODATA 8 Bit Prescaler 1 2 XIN 2 SIOPS F4H SCK SIOCON 7 Shift Clock Source Select Toggle Prescaler Value 1 SIOPS 1 CLK SIOCON 1 Interrupt Enable CLK SI SIOCON 3 SIOCON 4 Edge ...

Page 282: ...DO1 DO0 D17 D16 D15 D14 D13 D12 D11 D10 SI SCK Figure 14 4 Serial I O Timing in Transmit Receive Mode Tx at falling SIOCON 4 0 IRQS DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 D17 D16 D15 D14 D13 D12 D11 D10 SCK Transmit Complete Set SIOCON 3 SI SO Figure 14 5 Serial I O Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 ...

Page 283: ... Serial I O Timing in Receive Only Mode PROGRAMMING TIP SIO ORG 0000H VECTOR 00H INT_SIO ORG 0100H INITIAL LD SYM 00H Global Fast interrupt disable SYM LD BTCON 10100010B Watch dog disable LD CLKCON 00011000B non divided CPU clock LD SPL 00H LD P2CONH 10101111B SIO setting LD P2CONL 00101010B LD SIOCON 00100110B Enable SIO Interrupt LD SIOPS 20 setting baud rate EI ...

Page 284: ...9 F84I9 14 6 PROGRAMMING TIP SIO Continued MAIN CALL SUB_SIO Data transmit routine JP MAIN SUB_SIO LD SIODATA TRANSBUF 1 byte transmission OR SIOCON 00001000B Shift start 8 bit transmit RET INT_SIO AND SIOCON 11111110 Pending bit clear IRET ...

Page 285: ...or In all operating modes transmission is started when any instruction usually a write operation uses the UDATA register as its destination address In mode 0 serial data reception starts when the receive interrupt pending bit UARTPND 1 is 0 and the receive enable bit UARTCON 4 is 1 In mode 1 and 2 reception starts whenever an incoming start bit 0 is received and the receive enable bit UARTCON 4 is...

Page 286: ...te selection Multiprocessor communication and interrupt control Serial receive enable disable control 9th data bit location for transmit and receive operations mode 2 Parity generation and check for transmit and receive operations mode 2 UART transmit and receive interrupt control A reset clears the UARTCON value to 00H So if you want to use UART module you must write appropriate value to UARTCON ...

Page 287: ...tion bit for transmit data in UART mode 2 0 Even parity bit generation for transmit data 1 Odd parity bit generation for transmit data Operating mode and baud rate selection bits see table below MS0 MCE RE TB8 RB8 RIE TIE MS1 MS0 0 0 1 0 1 x Mode Description 2 Baud Rate 0 1 2 Shift register 8 bit UART 9 bit UART fxx 16 x 16bit BRDATA 1 fxx 16 x 16bit BRDATA 1 fxx 16 x 16bit BRDATA 1 NOTES 1 In mod...

Page 288: ...acknowledged the transmit interrupt pending condition the UARTPND 0 flag must be cleared by software in the interrupt service routine UART Pending Register UARTPND F4H Set1 Bank 0 R W Reset Value 00H MSB LSB PEN RPE RIP TIP 7 6 3 2 UART parity enable disable 0 Disable 1 Enable UART receive parity error 0 No error 1 Parity error UART receive interrupt pending flag 0 Not pending 0 Clear pending bit ...

Page 289: ...UARTCON 2 RB8 is also for settings of the even parity checking RB8 0 or the odd parity checking RB8 1 in the receive mode The parity enable generation checking functions are not available in UART mode 0 and 1 If you don t want to use a parity mode UARTCON 2 RB8 and UARTCON 3 TB8 are a normal control bit as the 9th data bit in this case PEN must be disable 0 in mode 2 Also it is needed to select th...

Page 290: ...Data Register BRDATAH EEH Set1 Bank 1 R W Reset Value FFH BRDATAL EFH Set1 Bank 1 R W Reset Value FFH 7 MSB LSB 6 5 4 3 2 1 0 Brud rate data Figure 15 4 UART Baud Rate Data Register BRDATAH BRDATAL BAUD RATE CALCULATIONS The baud rate is determined by the baud rate data register 16bit BRDATA Mode 0 baud rate fxx 16 16Bit BRDATA 1 Mode 1 baud rate fxx 16 16Bit BRDATA 1 Mode 2 baud rate fxx 16 16Bit...

Page 291: ...MHz 0 0H 11 0BH 38 400 Hz 11 0592 MHz 0 0H 17 11H 19 200 Hz 11 0592 MHz 0 0H 35 23H 9 600 Hz 11 0592 MHz 0 0H 71 47H 4 800 Hz 11 0592 MHz 0 0H 143 8FH 76 800 Hz 10 MHz 0 0H 7 7H 38 400 Hz 10 MHz 0 0H 15 FH 19 200 Hz 10 MHz 0 0H 31 1FH 9 600 Hz 10 MHz 0 0H 64 40H 4 800 Hz 10 MHz 0 0H 129 81H 2 400 Hz 10 MHz 1 1H 3 3H 600 Hz 10 MHz 4 4H 16 10H 38 461 Hz 8 MHz 0 0H 12 0CH 12 500 Hz 8 MHz 0 0H 39 27H ...

Page 292: ...Shift Value MS0 MS1 MS0 MS1 RxD P2 6 SAM88 Internal Data Bus Write to UDATA Baud Rate Generator S D Q CLK TB8 CLK Tx Control Start Tx Clock TIP Shift EN Send Rx Control Rx Clock Start RIP Receive Shift Shift Clock MS0 MS1 fxx SAM88 Internal Data Bus Shift Register UDATA 16 BIT BRDATA TxD P2 7 TxD P2 7 Figure 15 5 UART Functional Block Diagram ...

Page 293: ...ode 0 Receive Procedure 1 Select mode 0 by setting UATCON 6 and 7 to 00B 2 Clear the receive interrupt pending bit UARTPND 1 by writing a 0 to UARTPND 1 3 Set the UART receive enable bit UARTCON 4 to 1 4 The shift clock will now be output to the TxD P2 7 pin and will read the data at the RxD P2 6 pin A UART receive interrupt vector E4H occurs when UARTCON 1 is set to 1 Transmit D0 D1 D2 D3 D4 D5 D...

Page 294: ...CON bits 7 and 6 to 01B 3 Write transmission data to the shift register UDATA F5H The start and stop bits are generated automatically by hardware Mode 1 Receive Procedure 1 Select the baud rate to be generated by 16bit BRDATA 2 Select mode 1 and set the RE Receive Enable bit in the UARTCON register to 1 3 The start bit low 0 condition at the RxD P1 4 pin will cause the UART module to start the ser...

Page 295: ...d rate for mode 2 is fosc 16 x 16bit BRDATA 1 clock frequency Mode 2 Transmit Procedure 1 Select the baud rate generated by 16bit BRDATA 2 Select mode 2 9 bit UART by setting UARTCON bits 6 and 7 to 10B Also select the 9th data bit to be transmitted by writing TB8 to 0 or 1 and set PEN bit of UARTPND register to 0 if you don t use a parity mode If you want to use the parity enable mode select the ...

Page 296: ...Register UARTDATA Start Bit TxD Stop Bit D0 D1 D2 D3 D4 D5 D6 D7 Shift Tx Clock Receive RIP Start Bit Rx Clock Stop Bit RxD D0 D1 D2 D3 D4 D5 D6 D7 Bit Detect Sample Time Shift TB8 or Parity bit RB8 or Parity bit Figure 15 8 Timing Diagram for UART Mode 2 Operation ...

Page 297: ... received with the 9th bit 0 do not generate an interrupt In this case the 9th bit simply separates the address from the serial data Sample Protocol for Master Slave Interaction When the master device wants to transmit a block of data to one of several slaves on a serial line it first sends out an address byte to identify the target slave Note that in this case an address byte differs from a data ...

Page 298: ...xt bytes data 9th bit 0 4 When the target slave receives the first byte all of the slaves are interrupted because the 9th data bit is 1 The targeted slave compares the address byte to its own address and then clears its MCE bit in order to receive incoming data The other slaves continue operating normally Full Duplex Multi S3C84I8 F84I8 C84I9 F84I9 Interconnect TxD RxD Master S3C84I9 F84I9 S3C84I8...

Page 299: ...nversion start or enable bit ADCON 0 A 10 bit conversion operation can be performed for only one analog input channel at a time The read write ADCON register is located in set 1 bank 0 at address F7H During a normal conversion ADC logic initially sets the successive approximation register to 200H the approximate half way point of an 10 bit register This register is then updated automatically durin...

Page 300: ...channel can be selected at a time You can dynamically select any one of the eight analog input pins ADC0 ADC7 by manipulating the 3 bit value for ADCON 6 ADCON 4 Start or Enable bit 0 Disable Operation 1 Start Operation A D Converter Control Register ADCON F7H Set 1 Bank 0 R W ADCON 3 bit is read only 7 6 5 4 3 2 1 0 MSB LSB End of Conversion bit realy only 0 Conversion not complete 1 Conversion c...

Page 301: ...DDATAH ADDATAL Input Pins ADC0 ADC7 P0 0 P0 3 P1 4 P1 5 P2 2 P2 3 10 bit result is loaded into A D Conversion Data Register To ADCON 3 EOC Flag AVref AVss Analog Comparator ADCON 4 6 Select one input pin of the assigned ADCON 0 ADC Enable ADCON 0 A D Conversion enable ADCON 2 1 M u l t i p l e x e r Clock Selector Successive Approximation Logic 10 bit D A Converter Conversion Result ADDATAH ADDATA...

Page 302: ...REF CONVERSION TIMING The A D conversion process requires 4 steps 4 clock edges to convert each bit and 10 clocks to step up A D conversion Therefore total of 50 clocks is required to complete a 10 bit conversion With a 10 MHz CPU clock frequency one clock cycle is 400 ns 4 fxx If each bit conversion requires 4 clocks the conversion rate is calculated as follows 4 clocks bit x 10 bits step up time...

Page 303: ...e value to the ADCON register 4 When conversion has been completed 50 clocks have elapsed the EOC ADCON 3 flag is set to 1 so that a check can be made to verify that the conversion was successful 5 The converted digital value is loaded to the output register ADDATAH 8 bit and ADDATAL 2 bit then the ADC module enters an idle state 6 The digital conversion result can now be read from the ADDATAH and...

Page 304: ...rsion start AD0_CHK TM ADCON 00001000B A D conversion end EOC check JR Z AD0_CHK No LD AD0BUFH ADDATAH 8 bit Conversion data LD AD0BUFL ADDATAL 2 bit Conversion data LD ADCON 00110001B Channel ADC3 fxx 16 Conversion start AD3_CHK TM ADCON 00001000B A D conversion end EOC check JR Z AD3_CHK No LD AD3BUFH ADDATAH 8 bit Conversion data LD AD3BUFL ADDATAL 2 bit Conversion data ...

Page 305: ...matically set to 1 and interrupt requests commence in 1 955 ms or 0 125 0 25 and 0 5 second intervals The watch timer can generate a steady 0 5 kHz 1 kHz 2 kHz or 4 kHz signal to the BUZZER output BZOUT pin By setting WTCON 3 and WTCON 2 to 11b the watch timer will function in high speed mode generating an interrupt every 1 955 ms High speed mode is useful for timing events for program debugging s...

Page 306: ...t WTCON 6 1 Enable watch timer interrupt 0 0 0 5 kHz buzzer BZOUT signal output 0 1 1 kHz buzzer BZOUT signal output 1 0 2 kHz buzzer BZOUT signal output WTCON 5 4 1 1 4 kHz buzzer BZOUT signal output 0 0 Set watch timer interrupt to 0 5 s 0 1 Set watch timer interrupt to 0 25 s 1 0 Set watch timer interrupt to 0 125 s WTCON 3 2 1 1 Set watch timer interrupt to 1 955 ms 0 Disable watch timer clear...

Page 307: ...lector Circuit MUX WTCON 0 WTINT WTCON 6 BUZZER Output BZOUT fW 214 fW 213 fW 212 fW 26 fW 64 0 5 kHz fW 32 1 kHz fW 16 2 kHz fW 8 4 kHz 1 Hz fx Main System Clock 9 8304MHz fXT Subsystem Clock 32768 Hz fw Watch timer Clock Selector WTCON 7 Frequency Dividing Circuit fW 32768 Hz fXT fx 256 Figure 17 1 Watch Timer Circuit Diagram ...

Page 308: ... SYM 00h Disable Global Fast interrupt LD IMR 00010000b Enable IRQ3 interrupt LD SPH 00000000b Set stack area LD SPL 0FFh LD BTCON 10100011b Disable Watch dog LD WTCON 11001110b 0 5 kHz buzzer 1 955ms duration interrupt Interrupt enable fxt 32 768Hz EI MAIN MAIN ROUTINE JR T MIAN WT_INT AND WTCON 11111110b pending clear IRET END ...

Page 309: ...because LCDCK is supplied by the watch timer The LCD mode control register LMOD is used to turn the LCD display on or off to select LCD clock frequency to turn the COM signal output on or off to select bias and duty Data written to the LCD display RAM can be transferred to the segment signal pins automatically without program control The LCD port control register LPOT is used to determine the LCD ...

Page 310: ...4 3 COM4 SEG19 P4 7 COM7 SEG16 P4 4 160 16 D a ta B U S Port Latch LPOT Display RAM Page2 Port Latch Timing Controller MUX SEG Control or Selector COM Control or selector fLCD SEG0 P2 4 COM3 P0 0 COM0 P0 3 COM Control LCD Voltage Control LMOD 16 4 8 Figure 18 2 LCD Circuit Diagram ...

Page 311: ...direct memory access DMA method that is synchronized with the fLCD signal RAM addresses in this location that are not used for LCD display can be allocated to general purpose use COM0 COM1 COM2 COM3 b0 b1 b2 b3 b4 b5 b6 b7 SEG0 COM7 COM6 COM5 COM4 SEG1 SEG2 SEG3 100H 101H 102H 103H 111H 112H 113H SEG17 SEG18 SEG19 Figure 18 3 LCD Display Data RAM Organization Table 18 1 Common and Segment Pins per...

Page 312: ...signal scanning of each segment output This is also referred as the LCD frame frequency Since the LCD clock is generated by watch timer clock fw The watch timer should be enabled when the LCD display is turned on LCD Mode Control Register LMOD F6H SET1 BANK1 R W 7 6 5 4 3 2 1 0 MSB LSB Not used LCD duty and bias selection bits 00 1 3 duty 1 3 bias COM0 COM2 SEG0 SEG19 01 1 4 duty 1 3 bias COM0 COM...

Page 313: ...Normal I O port SEG4 SEG19 and COM0 COM3 selection bits 000 P0 P3 P4 LCD signal pins 001 P3 0 P3 3 Normal I O Others LCD signal pins 010 P3 0 P3 7 Normal I O Others LCD signal pins 011 P3 0 P4 3 Normal I O Others LCD signal pins 100 P3 0 P4 7 Normal I O Others LCD signal pins 101 P0 P3 P4 Normal I O 110 Not available 111 Not available SEG1 P2 5 selection bit 0 SEG port 1 Normal I O port SEG2 P2 6 ...

Page 314: ...GNALS The common signal output pin selection COM pin selection varies according to the selected duty cycle In 1 3 duty mode COM0 COM2 pins are selected In 1 4 duty mode COM0 COM3 pins are selected In 1 8 duty mode COM0 COM7 pins are selected SEGMENT SEG SIGNALS The 19 LCD segment signal pins are connected to corresponding display RAM locations at page 2 Bits of the display RAM are synchronized wit...

Page 315: ...COM6 COM7 COM1 VLC2 VLC3 VLC4 VSS VDD VLC1 SEG0 VLC2 VLC3 VLC4 VSS VDD VLC1 COM2 VLC2 VLC3 VLC4 VSS VDD VLC1 COM0 VLC2 VLC3 VLC4 VSS VDD VLC1 SEG0 COM0 VDD 0V 1 4VLCD VLCD 1 4VLCD 0 1 2 3 7 4 6 5 0 1 2 3 7 4 6 5 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 Figure 18 7 LCD Signal Waveforms 1 8 Duty 1 4 Bias ...

Page 316: ... VLC2 VLC3 VLC4 COM2 VSS VDD VLC1 VLC2 VLC3 VLC4 COM3 VSS VDD VLC1 VLC2 VLC3 VLC4 SEG0 VSS VDD VLC1 VLC2 VLC3 VLC4 SEG1 VSS VDD VLC1 VLC2 VLC3 VLC4 COM0 SEG0 VLCD COM0 VSS VDD VLC1 VLC2 VLC3 VLC4 1 3 VLCD 0V 1 3 VLCD VLCD COM0 COM1 COM2 COM3 SEG1 SEG0 Figure 18 8 LCD Signal Waveforms 1 4 Duty 1 3 Bias ...

Page 317: ... VDD VLC1 VLC2 VLC3 VLC4 COM2 VSS VDD VLC1 VLC2 VLC3 VLC4 SEG0 VSS VDD VLC1 VLC2 VLC3 VLC4 SEG1 VSS VDD VLC1 VLC2 VLC3 VLC4 COM0 SEG0 VLCD COM0 VSS VDD VLC1 VLC2 VLC3 VLC4 1 3 VLCD 0V 1 3 VLCD VLCD COM0 COM1 COM2 SEG2 SEG1 SEG0 0 1 2 Figure 18 9 LCD Signal Waveforms 1 3 Duty 1 3 Bias ...

Page 318: ...on starts All system and peripheral control registers are then set to their default hardware reset values see Table 8 1 The MCU provides a watchdog timer function in order to ensure graceful recovery from software malfunction If watchdog timer is not refreshed before an end of counter condition overflow is reached the internal reset will be activated The S3C84I8 F84I8 84I9 F84I9 has a built in low...

Page 319: ...eference Longger than 1us N F nRESET Watchdog RESET Figure 19 1 Low Voltage Reset Circuit NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you...

Page 320: ...e 12 5V programming power is supplied into the Vpp Test pin The other modules except flash memory module are at a reset state This mode doesn t support sector erase but chips erase and two protection modes Hard lock protection Read protection Table 20 1 Descriptions of Pins Used to Read Write the Flash ROM Main Chip During Programming Pin Name Pin Name Pin No I O Function P1 2 SDAT 3 44 pin 9 42 p...

Page 321: ...EMBEDDED FLASH MEMORY INTERFACE S3C84I8 F84I8 84I9 F84I9 20 2 VDD VSS VDD VSS 5 6 44 pin 11 12 42 pin I Logic power supply pin ...

Page 322: ...ry Control Register FMCON register is available only in user program mode to program some data to the flash memory Flash Memory Control Register FMCON FCH Set1 Bank1 R W 7 6 5 4 3 2 1 0 MSB LSB Flash Operation Start Bit 0 Operation stop 1 Operation start This bit will be cleared automatically just after the corresponding operation completed Flash Memory Mode Selection Bits 0101 Programming mode 10...

Page 323: ...s 00000000B If necessary you can use the user programming mode by setting the value of FMUSR is 10100101B Flash Memory User Programming Enable Register FMUSR FBH Set1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB Flash Memory User Programming Enable bits 10100101 Enable user programming mode Other values Disable user programming mode Figure 20 2 Flash Memory User Programming Enable Register FMUSR ...

Page 324: ...56 sectors to be erased written in flash memory Sectors have all 128byte sizes as program memory areas Sector Erase is not supported in Tool Program Modes MDS mode Minimum 2ms to maximum 100ms delay time for erase is required after setting sector address Sector 0 17 128 byte x 18 Sector 255 128 byte Sector 254 128 byte Sector 127 128 byte Sector 19 128 byte Sector 18 128 byte 08FFH 0000H 0900H 097...

Page 325: ...ou have to input Low address of sector that s accessed Figure 20 5 Flash Memory Sector Address Register FMSECL The Sector Erase Procedure in User Program Mode 1 Set Flash Memory User Programming Enable Register FMUSR to 10100101B 2 Set Flash Memory Sector Address Register FMSECH FMSECL 3 Set Flash Memory Control Register FMCON to 10100001B 4 Set Flash Memory User Programming Enable Register FMUSR ...

Page 326: ... Programming Enable Register FMUSR to 10100101B 3 Set Flash Memory Control Register FMCON to 01010001B 4 Set Flash Memory Sector Address Register FMSECH FMSECL to sector value of the address to write data 5 Load a transmission data into a working register 6 Load a flash memory upper address into upper register of pair working register 7 Load a flash memory lower address into lower register of pair...

Page 327: ...p LD FMUSR 00H User Program mode disable SB0 Case2 Programming in the same sector WR_INSECTOR RR10 Address copy R10 high address R11 low address LD R0 40H SB1 LD FMUSR 0A5H User Program mode enable LD FMCON 01010001B Programming mode enable LD FMSECH 40H Set sector address located in target address to write data LD FMSECL 00H SECTOR128 sector base address 4000H LD R9 33H Load data 33H to write LD ...

Page 328: ...data LD FMSECL 00H SECTOR50 sector base address 1900H LD R9 55H Load data 55H to write LD R10 19H Load flash memory upper address into upper register of pair working register LD R11 40H Load flash memory lower address into lower register of pair working register CALL WR_BYTE WR_INSECTOR128 LD FMSECH 40H Set sector address located in target address to write data LD FMSECL 00H SECTOR128 sector base ...

Page 329: ... flash memory lower address into lower register of pair working register 3 Load receive data from flash memory location area on LDC instruction by indirectly addressing mode PROGRAMMING TIP Reading LD R2 03H load flash memory upper address to upper of pair working register LD R3 00H load flash memory lower address to lower pair working register LOOP LDC R0 RR2 read data from flash memory location ...

Page 330: ...tection is following that Whereas in tool mode the manufacturer of serial tool writer could support Hardware Protection Please refer to the manual of serial program writer tool provided by the manufacturer The program procedure in User program Mode 1 Set Flash Memory User Programming Enable Register FMUSR to 10100101B 2 Set Flash Memory Control Register FMCON to 01100001B 3 Set Flash Memory User P...

Page 331: ...tables and graphs The information is arranged in the following order Absolute maximum ratings Input output capacitance D C electrical characteristics A C electrical characteristics Oscillation characteristics Oscillation stabilization time Data retention supply voltage in stop mode UART timing characteristics in mode 0 A D converter electrical characteristics ...

Page 332: ...0 3 to VDD 0 3 V Output Current High IOH One I O pin active 15 All I O pins active 60 One I O pin active 30 Output Current Low IOL All I O pins active 200 mA Operating Temperature TA 25 to 85 Storage Temperature TSTG 65 to 150 C Table 21 2 Input Output Capacitance TA 25 C to 85 C VDD 0 V Parameter Symbol Conditions Min Typ Max Unit Input Capacitance CIN Output Capacitance COUT I O Capacitance CIO ...

Page 333: ...V to 5 5 V All Ports and nRESET 0 2VDD Input Low Voltage VIL2 VDD 2 5V to 5 5 V XIN and XTIN 0 4 V Output High Voltage VOH VDD 5 0 V IOH 2 mA All Ports VDD 1 0 V VOL1 VDD 5 0 V IOL 16 mA Ports 0 and 4 Output Low Voltage VOL2 VDD 5 0 V IOL 4 mA Ports 1 2 and 3 0 4 2 0 V ILIH1 VIN VDD All input pins except ILIH2 3 Input High Leakage Current ILIH2 VIN VDD XIN XOUT and XTIN XTOUT 20 ILIL1 VIN 0 V All ...

Page 334: ...DC VDD 2 5 V to 5 5 V 15 µA per common pin 120 mV VLCD SEGx Voltage Drop x 0 19 VDS VDD 2 5 V to 5 5 V 15 µA per common pin 120 VLC2 0 8VDD 0 2 0 8VDD 0 8VDD 0 2 VLC3 0 6VDD 0 2 0 6VDD 0 6VDD 0 2 VLC4 0 4VDD 0 2 0 4VDD 0 4VDD 0 2 Middle Output Voltage VLC5 VDD 2 5 V to 5 5 V LCD clock 0Hz VLC1 VDD 0 2VDD 0 2 0 2VDD 0 2VDD 0 2 V RP1 VDD 5 V VIN 0 V TA 25 C All I O pins except nRESET 25 50 100 Pull ...

Page 335: ...l oscillator 400 800 IDD4 Sub idle mode main osc stop VDD 2 5 V to 3 3 V 32768 Hz crystal oscillator 300 600 Supply Current 1 IDD5 3 VDD 4 5V to 5 5 V TA 25 C Stop mode 150 400 uA NOTES 1 Supply current does not include current drawn through internal pull up resistors or external output current loads 2 IDD1 and IDD2 include a power consumption of subsystem oscillator 3 IDD3 and IDD4 are the curren...

Page 336: ... Conditions Min Typ Max Unit Interrupt Input High Low Width Ports 2 tINTH tINTL VDD 5 V 180 ns nRESET Input Low Width tRSL Input 1 0 µs NOTE User must keep more large value then min value tINTL 0 8 VDD 0 2 VDD tINTH 0 2 VDD Figure 21 1 Input Timing for External Interrupts Ports 2 RESET tRSL 0 2 VDD Figure 21 2 Input Timing for nRESET ...

Page 337: ...scillator Test Condition Min Typ Max Unit Main Crystal 10 Main Ceramic fOSC 400 kHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range 4 ms External Clock Main System XIN input High and Low width tXH tXL 50 ns tWAIT when released by a reset 1 216 fOSC sec Oscillator Stabilization Wait Time tWAIT when released by an interrupt 2 sec NOTES 1 fOSC is the oscilla...

Page 338: ...stal C1 C2 XTIN XTOUT R Crystal oscillation frequency C1 100 pF C2 100 pF R 330 Ω XTIN and XTOUT are connected with R and C by soldering 32 32 768 34 kHz Table 21 8 Subsystem Oscillator crystal Stabilization Time tST2 TA 25 C Test Condition Min Typ Max Unit VDD 4 5 V to 5 5 V 800 1600 ms VDD 2 5 to 3 3 V 10 s NOTE Oscillation stabilization time tST2 is the time required for the oscillator to it s ...

Page 339: ...V Data Retention Supply Current IDDDR Stop mode VDDDR 2 5 V 8 µA NOTE Supply current does not include current drawn through internal pull up resistors or external output current loads NOTE tWAIT is the same as 4096 x 16 x 1 fOSC Execution of STOP Instrction RESET occurs VDDDR Stop Mode Oscillation Stabilzation Time Data Retention Mode tWAIT RESET VDD Normal Operating Mode Figure 21 4 Stop Mode Rel...

Page 340: ...6 x 16 x BT clock Figure 21 5 Stop Mode Main Release Timing Initiated by Interrupts Execution of STOP Instruction VDDDR Stop Mode Idle Mode Data Retention Mode tWAIT VDD Interrupt Normal Operating Mode Oscillation Stabilization Time 0 2 VDD NOTE When the case of select the fxx 128 for basic timer input clock before enter the stop mode tWAIT 128 x 16 x 1 32768 62 5 ms Figure 21 6 Stop Mode Sub Rele...

Page 341: ... clock rising edge tS1 300 tCPU 5 Clock rising edge to input data valid tS2 300 Output data hold after clock rising edge tH1 tCPU 50 tCPU Input data hold after clock rising edge tH2 0 Serial port clock High Low level width tHIGH tLOW 200 tCPU 3 400 ns NOTES 1 All timings are in nanoseconds ns and assume a 10 MHz CPU clock frequency 2 The unit tCPU means one CPU clock period 0 2 VDD 0 8 VDD tHIGH t...

Page 342: ...tCON 10 bit conversion 50 x 4 fOSC 3 fOSC 10 MHz 20 µs Analog input voltage VIAN AVSS AVREF V Analog input impedance RAN 2 1000 MΩ Analog reference voltage AVREF 2 5 VDD Analog ground AVSS VSS VSS 0 3 V Analog input current IADIN AVREF VDD 5 V conversion time 20 µs 10 µA AVREF VDD 5 V conversion time 20 µs 1 3 AVREF VDD 3 V conversion time 20 µs 0 5 1 5 mA Analog block current 2 IADC AVREF VDD 5 V...

Page 343: ...25 C Parameter Symbol Test Condition Min Typ Max Unit LVR Voltage Level VLVR LVR is enabled by smart option TA 25 C 2 5 2 8 3 1 V CPU Clock 1 MHz Main Oscillator Frequency 1 2 3 4 5 6 7 Supply Voltage V 8 MHz 10 MHz 5 5 V Minimum instruction clock 1 4 Oscillator clock 2 5 V Figure 21 8 Operating Voltage Range ...

Page 344: ...I9 F84I9 21 14 VDD VSS 104 S3C84I8 F84I8 C84I9 F84I9 Figure 21 9 The Circuit Diagram to Improve EFT Characteristics NOTE To improve EFT characteristics we recommend using power capacitor near S3C84I8 F84I8 C84I9 F84I9 like Figure 21 9 ...

Page 345: ...crocontrollers are available in a 42 SDIP 600 44 QFP 1010 package NOTE Dimensions are in millimeters 39 50 MAX 39 10 0 20 0 50 0 10 1 78 1 77 0 51 MIN 3 30 0 30 3 50 0 20 5 08 MAX 42 SDIP 600 0 15 1 00 0 10 0 2 5 0 1 0 0 0 5 15 24 14 00 0 20 42 22 21 1 Figure 22 1 42 SDIP 600 Package Dimensions ...

Page 346: ...4I9 22 2 44 QFP 1010 44 NOTE Dimensions are in millimeters 10 00 0 20 13 20 0 30 10 00 0 20 13 20 0 30 1 0 35 0 10 0 05 0 80 0 10 MAX 0 80 0 20 0 05 MIN 2 05 0 10 2 30 MAX 0 15 0 10 0 05 0 8 1 00 Figure 22 2 44 QFP 1010 Package Dimensions ...

Page 347: ...ASM The SASM is a re locatable assembler for Samsung s S3C8 series microcontrollers The SASM takes a source file containing assembly language statements and translates them into a corresponding source code an object code and comments The SASM supports macros and conditional assembly It runs on the MS DOS operating system As it produces the re locatable object codes only the user should link object...

Page 348: ...d on the device specific target board TB84I9 is a specific target board for the S3C84I8 F84I8 84I9 F84I9 development Bus Emulator SMDS2 or SK 1000 RS 232C POD Probe Adapter PROM OTP Writer Unit RAM Break Display Unit Trace Timer Unit SAM8 Base Unit Power Supply Unit IBM PC AT or Compatible TB84I9 Target Board EVA Chip Target Application System Figure 23 1 SMDS or SK 1000 Product Configuration ...

Page 349: ...B84I9 Target Board Configuration TB84I9 8 84H5 GND V CC To User_VCC OFF ON SMDS2 SMDS2 J101 42SDIP J102 44QFP 1 5 15 21 10 42 40 25 22 30 35 1 5 15 22 10 44 40 30 23 35 25 20 P2 25 160 30 20 10 1 150 140 130 50 60 70 80 90 100 110 120 RESET R1 D1 C1 C11 U2 R7 R8 Y1 C7 CB C9 C10 JP10 C2 C3 T1T2T3T4 IDLE STOP R5 R4 C12 20 10 1 51 76 26 REV X 200X XX XX CN1 Y2 AR1 C16 SW1 AR2 JP1 Figure 23 2 S3F84I9 ...

Page 350: ...pplies VDD only to the target board evaluation chip The target system must have a power supply of its own Table 23 2 Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part Comments External Triggers Ch1 Ch2 Connector from External Trigger Sources of the Application System You can connect an external trigger source to one of the two external trigger channels CH1 o...

Page 351: ... 4 SI AD7 P2 3 SCK SEG1 P2 5 TX SEG3 P2 7 Avss P3 1 SEG5 P3 3 SEG7 P3 5 SEG9 P3 7 SEG11 P4 1 SEG13 P4 3 SEG15 P4 5 SEG17 COM5 P4 7 SEG19 COM7 P0 1 COM1 AD1 P0 3 COM3 AD3 INT0 TAOUT P1 0 INT2 TACAP P1 2 VDD XOUT TEST Xtout TBPWM T1CK0 P2 0 T1OUT0 AD4 P2 2 T1CAP1 AD6 P1 5 SO SEG0 P2 4 Rx SEG2 P2 6 Avref P3 0 SEG4 P3 2 SEG6 P3 4 SEG8 P3 6 SEG10 P4 0 SEG12 P4 2 SEG14 P4 4 SEG16 COM4 P4 6 SEG18 COM6 P0...

Page 352: ...NT2 TACAP P1 2 AD3 COM3 P0 3 AD2 COM2 P0 2 AD1 COM1 P0 1 AD0 COM0 P0 0 P4 1 SEG13 P4 0 SEG12 P3 7 SEG11 P3 6 SEG10 P3 5 SEG9 P3 4 SEG8 P3 3 SEG7 P3 2 SEG6 P3 1 SEG5 P3 0 SEG4 AVss AVref P2 7 SEG3 TxD P2 6 SEG2 RxD P2 5 SEG1 SCK P2 4 SEG0 SO P2 3 AD7 SI 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 Figure 23 4 42 Pin Connector Pin Assignment for TB84I9 Target Board 44 Pin Connector...

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