Samsung MAX-DN55, Service Manual

Page: 9 / 75

Reference Information
Samsung Electronics 9-7
DRAM data bus
32
DD9_BI
Digital GND (0V)
31
DVSS
DRAM data bus
30
DD5_BI
DRAM data bus
29
DD10_BI
DRAM data bus
28
DD4_BI
DRAM data bus
27
DD11_BI
Digital power (+5V)
26
DVDD
DRAM data bus
25
DD3_BI
DRAM data bus
24
DD12_BI
DRAM data bus
23
DD2_BI
DRAM data bus
22
DD13_BI
Digital GND (0V)
21
DVSS
DRAM data bus
20
DD1_BI
DRAM data bus
19
DD14_BI
DRAM data bus
18
DD0_BI
DRAM data bus
17
DD15_BI
Digital GND (0V)
16
DVSS
System clock output for 26.16 MHz
15
XTO_OUT
System clock input for 26.16 MHz
14
XTI_IN
Digital power (+5V)
13
DVDD
Micom data bus
12
MDA
T0_BI
Micom data bus
11
MDA
T1_BI
Micom data bus
10
MDA
T2_BI
Micom data bus
9
MDA
T3_BI
Micom data bus
8
MDA
T4_BI
Micom data bus
7
MDA
T5_BI
Micom data bus
6
MDA
T6_BI
Micom data bus
5
MDA
T7_BI
Digital GND (0V)
4
DVSS
Micom register select (L -> Register H -> Data)
3
MRZA_IN
Chip select (Active Low)
2
ZCS_IN
Digital GND (0V)
1
DVSS
FUNCTION
PIN
NAME
DVD data/Sub code frame sink (WFSY)
65
SDA
TA5_OUT
DVD data/Sub code serial data (SQDT)
64
SDA
TA4_OUT
DVD data/CD data error flag (C2P0)
63
SDA
TA3_OUT
DVD data/CD data bit clock (BLCK)
62
SDA
TA2_OUT
DVD data/CD data L/R clock (LRCK)
61
SDA
TA1_OUT
DVD data/CD data bitstream output
60
SDA
TA0_OUT
Digital power (+5V)
59
DVDD
Data acknowledge signal output
58
DA
TACK_OUT
Top of sector
57
TOS_OUT
Digital GND (0V)
56
DVSS
Digital GND (0V)
55
DVSS
DRAM address bus
54
DADR3_OUT
DRAM address bus
53
DADR4_OUT
DRAM address bus
52
DADR2_OUT
DRAM address bus
51
DADR5_OUT
DRAM address bus
50
DADR1_OUT
DRAM address bus
49
DADR6_OUT
DRAM address bus
48
DADR0_OUT
Digital GND (0V)
47
DVSS
DRAM address bus
46
DADR7_OUT
DRAM address bus
45
DADR8_OUT
DRAM row address strobe
44
ZRAS_OUT
DRAM output enable 0
43
ZOEO_OUT
Digital power (+5V)
42
DVDD
DRAM output enable 1 (16M, --------, 16M)
41
ZOE1_OUT
DRAM write enable 0 (4M, 8M, 16M)
40
ZWE0_OUT
DRAM write enable 1 (8M ONL
Y)
39
ZWE1_OUT
DRAM upper column address strobe
38
ZUCAS_OUT
DRAM row column address strobe
37
ZLCAS_OUT
Digital GND (0V)
36
DVSS
DRAM data bus
35
DD7_BI
DRAM data bus
34
DD8_BI
DRAM data bus
33
DD6_BI
FUNCTION
PIN
NAME
Digital GND (+5V)
97
DVSS
System clock output for 33.8688MHz
96
CK33MO_OUT
System clock input for 33.8688MHz
95
CK33MI_IN
Digital out
92
TX_OUT
Good frame sync detection result output (“H” active)
93
GFS_OUT
Frame sync out
91
FRSYZ_OUT
Digital GND (0V)
90
DVSS
Digital GND (0V)
89
DVSS
Digital GND (0V)
88
DVSS
Digital GND (0V)
87
DVSS
Digital power (+5V)
86
DVDD
Digital power (+5V)
85
DVDD
Digital GND (0V)
84
DVSS
Digital GND (0V)
83
DVSS
Digital GND (0V)
82
DVSS
PWM output signal
81
PWM00_OUT
PWM output signal
80
PWM01_OUT
PWM output signal
79
PWM02_OUT
PWM output signal
78
PWM03_OUT
Digital power (+5V)
77
DVDD
PWM output signal
76
PWM04_OUT
PWM output signal
75
PWM05_OUT
PWM output signal
74
PWM06_OUT
PWM output signal
73
PWM07_OUT
Digital GND (0V)
72
DVSS
DVD data error output
71
DTER_OUT
Data request from A/V decoder or ROM decoder
70
DA
TREQ_IN
Data strobe (clock) output
69
CSTROBE_OUT
Digital GND (0V)
68
DVSS
DVD data/Sub code serial clock (SQCK)
67
SDA
TA
7_BI
DVD data/Sub code block sink (S0S1)
66
SDA
TA6_OUT
FUNCTION
PIN
NAME
Micom write strobe (schmidt trigger)
128
MWR_IN
Micom read strobe (schmidt trigger)
127
MRD_IN
Interrupt request from micom
126
ZIRQZD_OUT
Micom read/write access wait (“L” wait)
125
ZW
AIT_OUT
Hardware reset active low
124
ZRST_IN
Digital GND (0V)
123
DVSS
BCA input signal
122
BCARZ_IN
When DEEMPHASIS is ON, “HIGH”.
121
DEMPHA_OUT
2
∫ –¡÷
clock of CK33M/16.934MHz
120
CK16M_OUT
Digital power (+5V)
119
DVDD
Digital power (+5V)
118
DVDD
Spindle motor output filter conversion output (3- state)
115
FSW_OUT
Digital power (+5V)
117
DVDD
EFM/EFM+ signal input
116
EFMI_IN
Reference signal for CA
V
114
FG_IN
Spindle motor ON/OFF control output
113
MON_OUT
Spindle motor speed control signal (3-state)
110
MDS_OUT
Spindle motor phase control signal (3-state)
109
MDP_OUT
Digital GND (0V)
112
DVSS
Digital GND (0V)
111
DVSS
Lock signal for SERVO
108
SERLOCK_OUT
Lock signal for CL
V
107
CL
VLOCK_OUT
Lock signal for PLL
106
PLLLOCK_OUT
Digital GND (0V)
105
DVSS
Phase locked clock
104
PLCK_IN
Reference frame pulse
103
RFCK_OUT
Write frame pulse
102
WFCK_OUT
EFM out
101
EFMO_OUT
Test mode setting port
100
TEST2_IN
Test mode setting port
99
TEST1_IN
Test mode setting port
98
TEST0_IN
FUNCTION
PIN
NAME
Digital GND (0V)
94
DVSS