Samsung Electronics
3-5
O
Does the VSYNC waveform
of CI1 pin95 input to EI1
pin 7 ?
O
Check the clock of CI1 pin99
input to VEI1 pin40,
41,42 ?
O
O
There is no field signal and OSD
X
Check connection condition
of CI1, EI1 & short
X
Check CI2 and short.
Check R.G.B waveform input
of VEI1 pin 5,7,9 ?
X
Check R.G.B data input of
CI1,VEI1 and short.
O
Check clock input of
EI1 pin8 ?
O
Check EI1 pin19 input to
NT : "L", PAL : "H"?
X
Check OI2,OI3 and
connection condition
X
Check MI1 pin39 and EQ1.
Check R.G.B waveform input
of EI1 pin12,13,14 ?
X
Check SI1 and short.
O
A
3-2-2 No Field Signal and OSD
Troubleshooting
Summary of Contents for MAX-673V
Page 30: ......
Page 32: ...6 2 CD 6 2 Samsung Electronics Block Diagrams ...
Page 33: ...6 3 Video CD Samsung Electronics 6 3 Block Diagrams ...
Page 40: ...7 PCB Diagrams 7 1 Cassette Deck 7 1 Samsung Electronics ...
Page 41: ...PCB Diagrams Samsung Electronics 7 2 ...
Page 42: ...7 1 1 Top View 7 2 CD 7 2 2 Bottom View 7 3 Samsung Electronics PCB Diagrams ...
Page 46: ...9 2 Option Samsung Electronics 9 2 Schematic Diagrams ...
Page 47: ...9 3 CD 9 3 Samsung Electronics Schematic Diagrams 1 1 2 2 ...