Samsung M391B5273DH0 Hardware User Manual Download | Manualshive

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datasheet

DDR3L SDRAM

Rev. 1.0

Unbuffered DIMM

Absolute Specification [T

OPER

; V

DDQ

= V

DD

= 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)];

NOTE

:

1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements

from CL setting as well as requirements from CWL setting.

2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guar-

anteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns],
rounding up to the next "SupportedCL".

3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or

1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.

4. "Reserved" settings are not allowed. User must program a different value.
5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

8. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to match. For example,

DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte
20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte
18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin
+ tRPmin=36ns+13.125ns) for DDR3-1333(CL9) and 48.125ns (tRPmin=35ns+13.125ns) for DDR3-1600(CL11).

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Summary of Contents for M391B5273DH0

Page 1: ... party to the other party under this document by implication estoppel or other wise Samsung products are not intended for use in life support critical care medical safety equipment or similar applications where product failure could result in loss of life or personal or physical harm or any military or defense application or any governmental procurement to which special terms or provisions may app...

Page 2: ... 2 datasheet DDR3L SDRAM Rev 1 0 Unbuffered DIMM Revision History Revision No History Draft Date Remark Editor 1 0 First Release Sep 2010 S H Kim ...

Page 3: ...tial Signals 15 11 3 1 Differential Signals Definition 15 11 3 2 Differential Swing Requirement for Clock CK CK and Strobe DQS DQS 15 11 3 3 Single ended Requirements for Differential Signals 17 11 3 4 Differential Input Cross Point Voltage 18 11 4 Slew Rate Definition for Single Ended Input Signals 19 11 5 Slew rate definition for Differential Input Signals 19 12 AC DC Output Measurement Levels 1...

Page 4: ...Burst Length 8 Interleave without any limit sequential with starting address 000 only 4 with tCCD 4 which does not allow seamless read or write either On the fly using A12 or MRS Bi directional Differential Data Strobe On Die Termination using ODT pin Average Refresh Period 7 8us at lower then TCASE 85 C 3 9us at 85 C TCASE 95 C Asynchronous Reset 3 Address Configuration Part Number2 Density Organ...

Page 5: ... 214 VSS 14 VSS 134 DM1 54 VDD 174 A12 BC 95 VSS 215 DQ46 15 DQS1 135 NC 55 A11 175 A9 96 DQ42 216 DQ47 16 DQS1 136 VSS 56 A7 176 VDD 97 DQ43 217 VSS 17 VSS 137 DQ14 57 VDD 177 A8 98 VSS 218 DQ52 18 DQ10 138 DQ15 58 A5 178 A6 99 DQ48 219 DQ53 19 DQ11 139 VSS 59 A4 179 VDD 100 DQ49 220 VSS 20 VSS 140 DQ20 60 VDD 180 A3 101 VSS 221 DM6 21 DQ16 141 DQ21 61 A2 181 A1 102 DQS6 222 NC 22 DQ17 142 VSS 62...

Page 6: ...rite enable VDDQ SDRAM I O Driver power supply S0 S1 DIMM Rank Select Lines VREFDQ SDRAM I O reference supply CKE0 CKE1 SDRAM clock enable lines VREFCA SDRAM command address reference supply ODT0 ODT1 On die termination control lines VSS Power supply return ground DQ0 DQ63 DIMM memory data bus VDDSPD Serial EEPROM positive power supply CB0 CB7 DIMM ECC check bits NC Spare Pins no connect DQS0 DQS8...

Page 7: ...oprecharge is selected and BA0 BA1 BA2 defines the bank to be precharged If AP is low autoprecharge is disabled During a pre charge command cycle AP is used in conjunction with BA0 BA1 BA2 to control which bank s to precharge If AP is high all banks will be precharged regardless of the state of BA0 BA1 or BA2 If AP is low BA0 BA1 and BA2 are used to define which bank to precharge A12 BC is sampled...

Page 8: ...o Table Rank 0 DRAM pins are wired straight with no mismatch between the connector pin assignment and the DRAM pin assignment Some of the Rank 1 DRAM pins are cross wired as defined in the table Pins not listed in the table are wired straight 7 1 1 DRAM Pin Wiring Mirroring Figure 1illustrates the wiring in both the mirrored and non mirrored case The lengths of the traces to the DRAM pins is obvio...

Page 9: ... DM5 DM CS DQS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I O 0 I O 1 I O 2 I O 3 I O 4 I O 5 I O 6 I O 7 D5 DQS6 DQS6 DM6 DM CS DQS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I O 0 I O 1 I O 2 I O 3 I O 4 I O 5 I O 6 I O 7 D6 DQS7 DQS7 DM7 DM CS DQS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I O 0 I O 1 I O 2 I O 3 I O 4 I O 5 I O 6 I O 7 D7 DQS8 DQS8 DM8 DM CS DQS DQS CB0 CB1 CB2 CB3 CB4 CB5 ...

Page 10: ... I O 0 I O 1 I O 2 I O 3 I O 4 I O 5 I O 6 I O 7 D9 DM CS DQS DQS I O 0 I O 1 I O 2 I O 3 I O 4 I O 5 I O 6 I O 7 D10 DM CS DQS DQS I O 0 I O 1 I O 2 I O 3 I O 4 I O 5 I O 6 I O 7 D11 DM CS DQS DQS I O 0 I O 1 I O 2 I O 3 I O 4 I O 5 I O 6 I O 7 D12 DM CS DQS DQS I O 0 I O 1 I O 2 I O 3 I O 4 I O 5 I O 6 I O 7 D13 DM CS DQS DQS I O 0 I O 1 I O 2 I O 3 I O 4 I O 5 I O 6 I O 7 D14 DM CS DQS DQS I O ...

Page 11: ...e Extended Temperature Range between 85 C and 95 C case temperature Full specifications are guaranteed in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the refresh interval tREFI to 3 9us It is also possible to specify a component with 1X refresh tREFI to 7 8us in the Extended Temperature Range b If Self Refresh operatio...

Page 12: ...lified symbol for VIL CA AC175 and VIL CA AC150 VIL CA AC175 value is used when VREF 175mV is referenced and VIL CA AC150 value is used when VREF 150mV is referenced Symbol Parameter DDR3 800 1066 1333 1600 Unit NOTE Min Max 1 35V VIH CA DC90 DC input logic high VREF 90 VDD mV 1 5a VIL CA DC90 DC input logic low VSS VREF 90 mV 1 6a VIH CA AC160 AC input logic high VREF 160 Note 2 mV 1 2 VIL CA AC1...

Page 13: ...en VREF 150mV is referenced Symbol Parameter DDR3 800 1066 DDR3 1333 1600 Unit NOTE Min Max Min Max 1 35V VIH DQ DC90 DC input logic high VREF 90 VDD VREF 90 VDD mV 1 5a VIL DQ DC90 DC input logic low VSS VREF 90 VSS VREF 90 mV 1 6a VIH DQ AC160 AC input logic high VREF 160 Note 2 mV 1 2 VIL DQ AC160 AC input logic low Note 2 VREF 160 mV 1 2 VIH DQ AC135 AC input logic high VREF 135 Note 2 VREF 13...

Page 14: ... levels for setup and hold time measurements VIH AC VIH DC VIL AC and VIL DC are dependent on VREF VREF shall be understood as VREF DC as defined in Figure 2 This clarifies that dc variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured System timing and voltage budgets need to account for ...

Page 15: ...s are not defined however they single ended signals CK CK DQS DQS need to be within the respective limits VIH DC max VIL DC min for single ended sig nals as well as the limitations for overshoot and undershoot Refer to overshoot and Undersheet Specification Symbol Parameter DDR3 800 1066 1333 1600 unit NOTE 1 35V 1 5V min max min max VIHdiff differential input high 0 18 NOTE 3 0 20 NOTE 3 V 1 VILd...

Page 16: ... Rate V ns tDVAC ps VIH Ldiff AC 320mV tDVAC ps VIH Ldiff AC 270mV min max min max 4 0 TBD TBD 4 0 TBD TBD 3 0 TBD TBD 2 0 TBD TBD 1 8 TBD TBD 1 6 TBD TBD 1 4 TBD TBD 1 2 TBD TBD 1 0 TBD TBD 1 0 TBD TBD Slew Rate V ns tDVAC ps VIH Ldiff AC 350mV tDVAC ps VIH Ldiff AC 300mV min max min max 4 0 75 175 4 0 57 170 3 0 50 167 2 0 38 163 1 8 34 162 1 6 29 161 1 4 22 159 1 2 13 155 1 0 0 150 1 0 0 150 ...

Page 17: ...le ended signals through the ac levels is used to measure setup time For single ended components of differential signals the requirement to reach VSELmax VSEHmin has no bearing on timing but adds a restriction on the common mode characteristics of these signals Table 6 Single ended levels for CK DQS CK DQS NOTE 1 For CK CK use VIH VIL AC of ADD CMD for strobes DQS DQS use VIH VIL AC of DQs 2 VIH A...

Page 18: ... VSEL 25mV VSEH VDD 2 Vix Max 25mV Table 8 Cross point voltage for differential input signals CK DQS 1 5V NOTE 1 Extended range for VIX is only allowed for clock and if single ended clock input signals CK and CK are monotonic have a single ended swing VSEL VSEH of at least VDD 2 250 mV and the differential slew rate of CK CK is larger than 3 V ns Symbol Parameter DDR3L 800 1066 1333 1600 Unit NOTE...

Page 19: ...Table 11 Differential AC and DC output levels NOTE 1 The swing of 0 2xVDDQ is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT VDDQ 2 at each of the differential outputs Description Measured Defined by From To Differential input slew rate for rising edge CK CK and DQS DQS VILdiffmax VIHdiffmin VIHd...

Page 20: ...itching into a certain direction either from high to low of low to high while all remaining DQ signals in the same byte lane are static i e they stay at either high or low Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction i e from low to high or high to low respectively For the remaining DQ signal switching into the opposite direction the reg...

Page 21: ...R Slew Rate Q Query Output like in DQ which stands for Data in Query Output diff Differential Signals For Ron RZQ 7 setting Figure 8 Differential output slew rate definition Description Measured Defined by From To Differential output slew rate for rising edge VOLdiff AC VOHdiff AC VOHdiff AC VOLdiff AC Delta TRdiff Differential output slew rate for falling edge VOHdiff AC VOLdiff AC VOHdiff AC VOL...

Page 22: ...L 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO FLOATING DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers2 ODT Signal stable at 0 IDD4R Operating Burst Read Current CKE High External clock On tCK CL Refer to Component Datasheet for detail pattern BL 81 AL 0 CS High between RD Command Address Bank Address Inputs partially togglin...

Page 23: ...4 Auto Self Refresh ASR set MR2 A6 0B to disable or 1B to enable feature 5 Self Refresh Temperature Range SRT set MR2 A7 0B for normal or 1B for extended temperature range 6 Refer to DRAM supplier data sheet and or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device 7 IDD current measure method and detail patterns are described on DDR3 component datasheet ...

Page 24: ... mA IDD3N 225 270 225 315 270 315 mA IDD4R 495 585 630 675 720 810 mA 1 IDD4W 540 630 675 720 810 855 mA 1 IDD5B 990 990 1035 1035 1035 1080 mA 1 IDD6 90 108 90 108 90 108 mA IDD7 900 945 1125 1215 1170 1260 mA 1 IDD8 90 108 90 108 90 108 mA Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit NOTE 7 7 7 9 9 9 11 11 11 1 35V 1 5V 1 35V 1 5V 1 35V 1 5V IDD0 405 468 450 540 513 585 mA 1 IDD1 495 558 540 630 60...

Page 25: ... 5 2 5 1 5 2 5 1 5 2 3 1 2 2 3 pF 1 2 3 Input capacitance CK and CK CCK 0 8 1 6 0 8 1 6 TBD TBD TBD TBD pF 2 3 Input capacitance delta CK and CK CDCK 0 0 15 0 0 15 TBD TBD TBD TBD pF 2 3 4 Input capacitance All other input only pins CI 0 75 1 3 0 75 1 3 0 75 1 3 0 75 1 3 pF 2 3 6 Input Output capacitance delta DQS and DQS CDDQS 0 0 2 0 0 2 TBD TBD TBD TBD pF 2 3 5 Input capacitance delta All contr...

Page 26: ...l 1Gb 2Gb 4Gb 8Gb Units NOTE All Bank Refresh to active refresh cmd time tRFC 110 160 300 350 ns Average periodic refresh interval tREFI 0 C TCASE 85 C 7 8 7 8 7 8 7 8 µs 85 C TCASE 95 C 3 9 3 9 3 9 3 9 µs 1 Speed DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 Units NOTE Bin CL tRCD tRP 6 6 6 7 7 7 9 9 9 11 11 11 Parameter min min min min CL 6 7 9 11 tCK tRCD 15 13 13 13 5 13 75 ns tRP 15 13 13 13 5 13 75...

Page 27: ...CWL Settings 5 6 nCK Speed DDR3 1333 Units NOTE CL nRCD nRP 9 9 9 Parameter Symbol min max Internal read command to first data tAA 13 5 13 125 8 20 ns ACT to internal read or write delay time tRCD 13 5 13 125 8 ns PRE command period tRP 13 5 13 125 8 ns ACT to ACT or REF command period tRC 49 5 49 125 8 ns ACT to PRE command period tRAS 36 9 tREFI ns CL 6 CWL 5 tCK AVG 2 5 3 3 ns 1 2 3 6 CWL 6 tCK...

Page 28: ...6 tCK AVG Reserved ns 1 2 3 4 7 CWL 7 8 tCK AVG Reserved ns 4 CL 7 CWL 5 tCK AVG Reserved ns 4 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 4 7 CWL 7 tCK AVG Reserved ns 1 2 3 4 7 CWL 8 tCK AVG Reserved ns 4 CL 8 CWL 5 tCK AVG Reserved ns 4 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 7 CWL 7 tCK AVG Reserved ns 1 2 3 4 7 CWL 8 tCK AVG Reserved ns 1 2 3 4 CL 9 CWL 5 6 tCK AVG Reserved ns 4 CWL 7 tCK AVG 1 5 1 875 ns 1 2 ...

Page 29: ...s functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 6 Any DDR3 1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 7 Any DDR3 1600 speed bin also supports functional operation at lo...

Page 30: ...ERR 6per 222 222 200 200 177 177 155 155 ps Cumulative error across 7 cycles tERR 7per 232 232 209 209 186 186 163 163 ps Cumulative error across 8 cycles tERR 8per 241 241 217 217 193 193 169 169 ps Cumulative error across 9 cycles tERR 9per 249 249 224 224 200 200 175 175 ps Cumulative error across 10 cycles tERR 10per 257 257 231 231 205 205 180 180 ps Cumulative error across 11 cycles tERR 11p...

Page 31: ...5ns max 4nCK 7 5ns max 4nCK 7 5ns e Delay from start of internal write transaction to internal read command tWTR max 4nCK 7 5ns max 4nCK 7 5ns max 4nCK 7 5ns max 4nCK 7 5ns e 18 WRITE recovery time tWR 15 15 15 15 ns e Mode Register Set command cycle time tMRD 4 4 4 4 nCK Mode Register Set command update delay tMOD max 12nCK 15ns max 12nCK 15ns max 12nCK 15ns max 12nCK 15ns CAS to CAS command dela...

Page 32: ...CK 20 Timing of PRE command to Power Down entry tPRPDEN 1 1 1 1 nCK 20 Timing of RD RDA command to Power Down entry tRDPDEN RL 4 1 RL 4 1 RL 4 1 RL 4 1 Timing of WR command to Power Down entry BL8OTF BL8MRS BC4OTF tWRPDEN WL 4 tWR tCK avg WL 4 tWR tCK avg WL 4 tWR tCK avg WL 4 tWR tCK avg nCK 9 Timing of WRA command to Power Down entry BL8OTF BL8MRS BC4OTF tWRAPDEN WL 4 WR 1 WL 4 WR 1 WL 4 WR 1 WL...

Page 33: ...e the device will support tnRP RU tRP tCK avg which is in clock cycles if all input clock jitter specifications are met This means For DDR3 800 6 6 6 of which tRP 15ns the device will support tnRP RU tRP tCK avg 6 as long as the input clock jitter specifications are met i e Precharge com mand at Tm and Active command at Tm 6 is valid even if Tm 6 Tm is less than 15ns due to input clock jitter Spec...

Page 34: ...ose operations 21 Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN min is satisfied there are cases where additional time such as tXPDLL min is also required See Device Operation Timing Diagram Datasheet 22 Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function 23 One ZQCS command can effectively correct a minimum of 0 5 ZQCorrect...

Page 35: ...4 0 54 675 Units Millimeters 9 50 128 95 2 4X 3 00 0 1 30 00 0 15 2 30 17 30 The used device is 256M x8 DDR3L SDRAM FBGA DDR3 SDRAM Part NO K4B2G0846D HY NOTE Tolerances on all dimensions 0 15 unless otherwise specified A B 47 00 71 00 2 50 1 00 0 2 0 15 2 50 0 20 Detail B 5 00 Detail A 1 50 0 10 0 80 0 05 3 80 2x 2 10 0 15 2 50 SPD 1 270 0 10 ...

Page 36: ...Units Millimeters 9 50 128 95 2 4X 3 00 0 1 30 00 0 15 2 30 17 30 The used device is 256M x8 DDR3L SDRAM FBGA DDR3 SDRAM Part NO K4B2G0846D HY NOTE Tolerances on all dimensions 0 15 unless otherwise specified A B 47 00 71 00 2 50 1 00 0 2 0 15 2 50 0 20 Detail B 5 00 Detail A 1 50 0 10 0 80 0 05 3 80 2x 2 10 0 15 2 50 SPD 1 270 0 10 ...

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