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Samsung KS86C6004, Manual

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Samsung KS86C6004 Manual Download Page 165

KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec)

MECHANICAL DATA

13-1

13

MECHANICAL DATA

OVERVIEW

The KS86C6004/C6008/P6008 is available in a 42-pin SDIP package (Samsung: 42-SDIP-600) and a 44-pin
QFP package (44-QFP-1010B). Package dimensions are shown in Figures 13-1 and 13-2.

NOTE:  Dimensions are in millimeters.

0-15 

15.24

0.25

+0.1

=

0.05

0.51MIN

3.30

 

=

0.3

5.08MAX

1.00 

=

0.1

0.50

 

=

0.1

(1.77)

1.778

3.50

 

=

0.2

39.10

 

=

0.2

39.50 MAX

42-SDIP-

14.00

 

=

0.2

#1

#21

#42

#22

Figure 13-1.  42-Pin SDIP Package Mechanical Data (42-SDIP-600 )

Summary of Contents for KS86C6004

Page 1: ...Product Overview Address Spaces Addressing Modes Control Registers Interrupt Structure SAM87RI Instruction Set ...

Page 2: ...ful SAM87RI CPU core Stop and Idle power down modes were implemented to reduce power consumption To increase on chip register space the size of the internal register file was logically expanded The KS86C6004 has 4 K bytes of program memory on chip and KS86C6008 has 8 K bytes Using the SAM87RI design approach the following peripherals were integrated with the SAM87RI core Five configurable I O port...

Page 3: ...stal ceramic oscillator External clock source 6 MHz General I O Bit programmable five I O ports 32 pins total Timer Counter One 8 bit basic timer for watchdog function and programmable oscillation stabilization interval generation function One 8 bit timer counter with Compare Overflow USB Serial Bus Compatible to USB low speed 1 5 Mbps device 1 0 specification Serial bus interface engine SIE Packe...

Page 4: ...T 3 SAM87RI CPU P0 0k0 7 INT2 8 KB ROM P3 0 P3 1 P3 2 P3 3 CLO OSC 224 BYTE REGISTER PORT 4 P4 0 INT1 P4 1 INT1 P4 2 INT1 P4 3 INT1 TIMER 0 PORT 1 PORT 2 P2 0k2 7 INT0 P1 0k1 7 XIN XOUT SAM87RI BUS BASIC TIMER I O PORT AND INTERRUPT CONTROL USB D D 3 3 VOUT 16 bytes USB Buffer Figure 1 1 Block Diagram ...

Page 5: ... INT1 P4 0 INT1 P4 1 RESET INT1 P4 2 INT1 P4 3 P1 7 KS86C6004 KS86C6008 42 SDIP Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 P3 2 P3 3 CLO D D 3 3 VOUT VSS2 P0 0 INT2 P0 1 INT2 P0 2 INT2 P0 3 INT2 P0 4 INT2 P0 5 INT2 P0 6 INT2 P0 7 INT2 P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 Figure 1 2 Pin Assignment Diagram 42 Pin SDIP P...

Page 6: ...T1 P4 2 INT1 RESET NC NC V SS2 P0 0 INT2 P0 1 INT2 P0 2 INT2 P0 3 INT2 P0 4 INT2 P0 5 INT2 P0 6 INT2 P0 7 INT2 INT0 P2 4 INT0 P2 5 INT0 P2 6 INT0 P2 7 V DD V SS1 X OUT X IN TEST P4 0 INT1 P4 1 INT1 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 KS86C6004 KS86C6008 Top View 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 Figure 1 3 Pin Assignment Diagram 44 Pin QFP Packa...

Page 7: ...41 40 37 P3 3 CLO P4 0 P4 3 I O Bit programmable I O port for Schmitt trigger input or open drain output or push pull output Port4 can be individually configured as external interrupt inputs In output mode pull up resistors are assignable by software But in input mode pull up resistors are fixed D 16 17 19 20 10 11 13 14 INT1 D D I O Only be used USB tranceive receive port D D 40 39 36 35 3 3 VOUT...

Page 8: ...er Circuit Type KS86C6004 C6008 P6008 Assignments A I RESET signal input B I O Ports 0 1 and 2 C I O Port 3 D I O Port 4 VDD PULL UP RESISTOR IN Noise Filter Figure 1 4 Pin Circuit Type A RESET OUTPUT DISABLE INPUT DATA MUX D0 D1 MODE INPUT DATA INPUT OUTPUT D0 D1 I O PULL UP ENABLE VSS VDD PULL UP RESISTOR OUTPUT DATA Figure 1 5 Pin Circuit Type B Ports 0 1 and 2 ...

Page 9: ...OVERVIEW KS86C6004 C6008 P6008 MICROCONTROLLER Preliminary Spec 1 8 VDD OPEN DRAIN OUTPUT DISABLE INPUT DATA MODE INPUT DATA INPUT OUTPUT D0 D1 I O OUTPUT DATA VSS MUX D0 D1 Figure 1 6 Pin Circuit Type C Port 3 ...

Page 10: ...OCONTROLLER Preliminary Spec PRODUCT OVERVIEW 1 9 VDD OPEN DRAIN OUTPUT DISABLE INPUT DATA MODE INPUT DATA INPUT OUTPUT D0 D1 I O OUTPUT DATA VSS PULL UP ENABLE VDD PULL UP RESISTOR MUX D0 D1 Figure 1 7 Pin Circuit Type D Port 4 ...

Page 11: ...ICROCONTROLLER Preliminary Spec 1 10 APPLICATION CIRCUIT KEYBOARD MATRIX 0 1 2 3 15 0 1 2 3 7 5V H O S T 5V XOUT XIN VSS1 VSS2 VDD PORT 3 PORT 0 PORT 1 PORT 2 TEST RESET D D KS86C6004 KS86C6008 Figure 1 8 Keyboard Application Circuit Diagram ...

Page 12: ...us carries addresses and data between the CPU and the internal register file The KS86C6004 has 4 K bytes of mask programmable program memory on chip and KS86C6008 has 8 K bytes There is one program memory configuration option Internal ROM mode in which only the 8 Kbyte internal program memory is used The KS86C6004 C6008 P6008 microcontroller has 208 general purpose registers in its internal regist...

Page 13: ...8 has 8 K bytes locations 0H 1FFFH of internal mask programmable program memory The first 2 bytes of the ROM 0000H 0001H are an interrupt vector address The program reset address in the ROM is 0100H DECIMAL HEX 1FFFH KS86C6008 P6008 8 191 2 1 0 0002H 0001H 0000H Interrupt vector 8 KBYTE INTERNAL PROGRAM MEMORY AREA 256 Program start 0100H 4 KBYTE INTERNAL PROGRAM MEMORY AREA 0FFFH KS86C6004 4 095 ...

Page 14: ...RI microcontrollers the addressable area of the internal register file is further expanded by the additional of one or more register pages at general purpose register space 00H BFH This register file expansion is not implemented in the KS86C6004 C6008 P6008 however Page addressing is controlled by the System Mode Register SYM 1 SYM 0 The specific register types and the area in bytes that they occu...

Page 15: ...R Preliminary Spec 2 4 WORKING REGISTERS E0H C0H CFH DFH D0H BFH 00H FFH SYSTEM CONTROL REGISTERS GENERAL PURPOSE REGISTER FILE and STACK AREA 192 BYTES 64 BYTES OF COMMON AREA PERIPHERAL CONTROL REGISTERS Figure 2 2 Internal Register File Organization ...

Page 16: ... used to access this area Registers are addressed either as a single 8 bit register or as a paired 16 bit register In 16 bit register pairs the address of the first 8 bit register is always an even number and the address of the next register is an odd number The most significant byte of the 16 bit data is always stored in the even numbered register the least significant byte is always stored in th...

Page 17: ...e values back to their original locations The stack address is always decremented before a push operation and incremented after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 4 STACK CONTENTS AFTER A CALL INSTRUCTION PCH PCL HIGH ADDRESS PCH TOP OF STACK PCL FLAGS STACK CONTENTS AFTER AN INTERRUPT TOP OF STACK LOW ADDRESS F...

Page 18: ...in the internal register file using PUSH and POP instructions LD SP 0C0H SP C0H Normally the SP is set to 0C0H by the initialization routine PUSH SYM Stack address 0BFH SYM PUSH CLKCON Stack address 0BEH CLKCON PUSH 20H Stack address 0BDH 20H PUSH R3 Stack address 0BCH R3 POP R3 R3 Stack address 0BCH POP 20H 20H Stack address 0BDH POP CLKCON CLKCON Stack address 0BEH POP SYM SYM Stack address 0BFH...

Page 19: ...ADDRESS SPACES KS86C6004 C6008 P6008 MICROCONTROLLER Preliminary Spec 2 8 NOTES ...

Page 20: ...de is the method used to determine the location of the data operand The operands specified in SAM87RI instructions may be condition codes immediate data or a location in the register file program memory or data memory The SAM87RI instruction set supports six explicit addressing modes Not all of these addressing modes are available for each instruction The addressing modes and their symbols are as ...

Page 21: ...ace see Figure 3 2 PROGRAM MEMORY dst OPCODE 8 BIT REGISTER FILE ADDRESS ONE OPERAND INSTRUCTION EXAMPLE REGISTER FILE OPERAND POINTS TO ONE REGISTER IN REGISTER FILE VALUE USED IN INSTRUCTION EXECUTION SAMPLE INSTRUCTION DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing SAMPLE INSTRUCTION ADD R1 R2 Where R1 C1H and R2 C2H PROGRAM MEMORY dst OPCODE 4 BIT ...

Page 22: ...ternal memory space see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location 8 BIT REGISTER FILE ADDRESS ONE OPERAND INSTRUCTION EXAMPLE POINTS TO ONE REGISTER IN REGISTER FILE REGISTER FILE OPERAND PROGRAM MEMORY dst OPCODE ADDRESS ADDRESS OF OPERAND USED BY INSTRUCTION VALU...

Page 23: ...ntinued PROGRAM MEMORY EXAMPLE INSTRUCTION REFERENCES PROGRAM MEMORY POINTS TO REGISTER PAIR REGISTER FILE 16 BIT ADDRESS POINTS TO PROGRAM MEMORY OPERAND VALUE USED IN INSTRUCTION PROGRAM MEMORY PAIR REGISTER dst OPCODE SAMPLE INSTRUCTIONS CALL RR2 JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory ...

Page 24: ...ER ADDRESSING MODE Continued PROGRAM MEMORY dst OPCODE 4 BIT WORKING REGISTER ADDRESS POINTS TO THE WORKING REGISTER 1 OF 16 4 LSBs src SAMPLE INSTRUCTION OR R6 R2 OPERAND VALUE USED IN INSTRUCTION OPERAND CFH C0H REGISTER FILE Figure 3 5 Indirect Working Register Addressing to Register File ...

Page 25: ...ta memory access NEXT 3 BITS POINT TO WORKING REGISTER PAIR 1 OF 8 OPERAND VALUE USED IN INSTRUCTION 4 BIT WORKING REGISTER ADDRESS EXAMPLE INSTRUCTION REFERENCES EITHER PROGRAM MEMORY OR DATA MEMORY PROGRAM MEMORY OPCODE dst src 16 BIT ADDRESS POINTS TO PROGRAM MEMORY OR DATA MEMORY PROGRAM MEMORY OR DATA MEMORY LSB SELECTS CFH C0H REGISTER FILE REGISTER PAIR Figure 3 6 Indirect Working Register ...

Page 26: ...to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to the base address see Figure 3 9 The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE ...

Page 27: ... 8 BITS 16 BITS 16 BITS VALUE USED IN INSTRUCTION PROGRAM MEMORY OR DATA MEMORY POINT TO WORKING REGISTER PAIR 1 OF 8 SAMPLE INSTRUCTIONS LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed OPCODE dst XS OFFSET src REGISTER FILE Figure 3 8 Indexed Addressing to Program...

Page 28: ...ADDED TO OFFSET LSB SELECTS 16 BITS 16 BITS 16 BITS VALUE USED IN INSTRUCTION PROGRAM MEMORY OR DATA MEMORY POINT TO WORKING REGISTER PAIR 1 OF 8 XLH OFFSET SAMPLE INSTRUCTIONS LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed src Figure 3 9 Indexed Addressing ...

Page 29: ...an use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented MEMORY ADDRESS USED LSB SELECTS PROGRAM MEMORY OR DATA MEMORY 0 PROGRAM MEMORY 1 DATA MEMORY PROGRAM OR DATA MEMORY UPPER ADDR BYTE LOWER ADDR BYTE dst src OPCODE 0 OR 1 PROGRAM MEMORY SAMPLE INSTRUCTIONS LDC R5 1234H The values in the prog...

Page 30: ...DE Continued PROGRAM MEMORY NEXT OPCODE LOWER ADDR BYTE PROGRAM MEMORY ADDRESS USED UPPER ADDR BYTE OPCODE SAMPLE INSTRUCTIONS JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions ...

Page 31: ...ruction The instructions that support RA addressing is JR PROGRAM MEMORY PROGRAM MEMORY ADDRESS USED DISPLACEMENT OPCODE SIGNED DISPLACEMENT VALUE CURRENT PC VALUE CURRENT INSTRUCTION NEXT OPCODE SAMPLE INSTRUCTION JR ULT OFFSET Where OFFSET is a value in the range 127 to 28 Figure 3 12 Relative Addressing IMMEDIATE MODE IM In Immediate IM addressing mode the operand value used in the instruction ...

Page 32: ... in the register file You can also use them as a quick reference source when writing application programs System and peripheral registers are summarized in Table 4 1 Figure 4 1 illustrates the important features of the standard register description format Control register descriptions are arranged in alphabetical order according to register mnemonic More information about control registers is pres...

Page 33: ...timer counter register BTCNT 221 DDH R Location DEH is not mapped System mode register SYM 223 DFH R W Port 0 data register P0 224 E0H R W Port 1 data register P1 225 E1H R W Port 2 data register P2 226 E2H R W Port 3 data register P3 227 E3H R W Port 4 data register P4 228 E4H R W Port 3 control register P3CON 229 E5H R W Port 0 control register high byte P0CONH 230 E6H R W Port 0 control registe...

Page 34: ...er EP0CSR 241 F1H R W Interrupt endpoint status register EP1CSR 242 F2H R W Control endpoint byte count register EP0BCNT 243 F3H R W Control endpoint FIFO register EP0FIFO 244 F4H R W Interrupt endpoint FIFO register EP1FIFO 245 F5H R W USB interrupt pending register USBPND 246 F6H R W USB interrupt enable register USBINT 247 F7H R W USB power management register PWRMGR 248 F8H R W Locations F9H F...

Page 35: ...nly Read write Not used Bit number s that is are appended to the register name for bit addressing Description of the effect of specific bit settings Name of individual bit or bit function Addressing mode or modes you can use to modify register values 7 6 5 4 3 2 1 0 x x x x x x 0 0 R W R W R W R W R W R W R W R W Not used Undetermined value Logic zero Logic one x 0 1 RESET value notation Zero Flag...

Page 36: ...0 Disable watchdog function Any other value Enable watchdog function 3 and 2 Basic Timer Input Clock Selection Bits 0 0 fOSC 4096 0 1 fOSC 1024 1 0 fOSC 128 1 1 Invalid setting 1 Basic Timer Counter Clear Bit note 0 No effect 1 Clear BTCNT 0 Basic Timer Divider Clear Bit note 0 No effect 1 Clear both dividers NOTE When you write a 1 to BTCON 0 or BTCON 1 the basic timer counter or basic timer divi...

Page 37: ...er down mode 1 Disable IRQ for main system oscillator wake up in power down mode 6 and 5 Not used for KS86C6004 C6008 P6008 4 and 3 CPU Clock System Clock Selection Bits 1 0 0 Divide by 16 fOSC 16 0 1 Divide by 8 fOSC 8 1 0 Divide by 2 fOSC 2 1 1 Non divided clock fOSC 2 2 0 Not used for KS86C6004 C6008 P6008 NOTES 1 After a reset the slowest clock divided by 16 is selected as the system clock To ...

Page 38: ...r End Bit 0 No effect when write 1 SIE sets this bit when a control transfer ends before DATA_END bit3 is set 3 Setup Data End Bit 0 No effect when write 1 MCU set this bit after loading or unloading the last packet data into the FIFO 2 STALL Signal Receive Bit 0 MCU clear this bit to end the STALL condition 1 SIE sets this bit if a control transaction is ended due to a protocol violation 1 In Pac...

Page 39: ...PKT_RDY Once set the contents are valid till MCU re writes them 2 FIFO Flush Bit 0 No effect when write 1 When MCU writes a one to this register the FIFO is flushed and IN_PKT_RDY cleared The MCU should wait for IN_PKT_RDY to be cleared for the flush to take place 1 Force STALL Bit 0 No effect when write 1 MCU writes a 1 to this register to issue a STALL handshake to USB MCU clears this bit to end...

Page 40: ...Address Register F0H Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 Not used for KS86C6004 C6008 P6008 6 0 FADDR This register holds the USB address assigned by the host computer FADDR is located at address F0H and is read write addressable ...

Page 41: ...R W R W R W 7 Carry Flag C 0 Operation does not generate a carry or borrow condition 6 Zero Flag Z 0 Operation result is a non zero value 1 Operation result is zero 5 Sign Flag S 0 Operation generates a positive number MSB 0 1 Operation generates a negative number MSB 1 4 Overflow Flag V 0 Operation result is 127 or 128 1 Operation result is 127 or 128 3 0 Not used for KS86C6004 C6008 P6008 ...

Page 42: ...ion Bits 0 0 Schmitt trigger input rising edge external interrupt 0 1 Schmitt trigger input falling edge external interrupt with pull up 1 0 N CH open drain output mode 1 1 N CH open drain output mode with pull up 3 and 2 Port 0 P0 5 Configuration Bits 0 0 Schmitt trigger input rising edge external interrupt 0 1 Schmitt trigger input falling edge external interrupt with pull up 1 0 N CH open drain...

Page 43: ...on Bits 0 0 Schmitt trigger input rising edge external interrupt 0 1 Schmitt trigger input falling edge external interrupt with pull up 1 0 N CH open drain output mode 1 1 N CH open drain output mode with pull up 3 and 2 Port 0 P0 1 Configuration Bits 0 0 Schmitt trigger input rising edge external interrupt 0 1 Schmitt trigger input falling edge external interrupt with pull up 1 0 N CH open drain ...

Page 44: ... interrupt disable 1 External interrupt enable 5 P0 5 Configuration Bits 0 External interrupt disable 1 External interrupt enable 4 P0 4 Configuration Bits 0 External interrupt disable 1 External interrupt enable 3 P0 3 Configuration Bits 0 External interrupt disable 1 External interrupt enable 2 P0 2 Configuration Bits 0 External interrupt disable 1 External interrupt enable 1 P0 1 Configuration ...

Page 45: ... 0 No pending when read clear pending bit when write 1 Pending when read no effect when write 4 P0 4 Interrupt Pending Bit 0 No pending when read clear pending bit when write 1 Pending when read no effect when write 3 P0 3 Interrupt Pending Bit 0 No pending when read clear pending bit when write 1 Pending when read no effect when write 2 P0 2 Interrupt Pending Bit 0 No pending when read clear pend...

Page 46: ...n drain output mode with pull up 5 and 4 Port 1 P1 6 Configuration Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input with pull up 1 0 N CH open drain output mode 1 1 N CH open drain output mode with pull up 3 and 2 Port 1 P1 5 Configuration Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input with pull up 1 0 N CH open drain output mode 1 1 N CH open drain output mode with pull up 1 and...

Page 47: ... drain output mode with pull up 5 and 4 Port 1 P1 2 Configuration Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input with pull up 1 0 N CH open drain output mode 1 1 N CH open drain output mode with pull up 3 and 2 Port 1 P1 1 Configuration Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input with pull up 1 0 N CH open drain output mode 1 1 N CH open drain output mode with pull up 1 and ...

Page 48: ...on Bits 0 0 Schmitt trigger input rising edge external interrupt 0 1 Schmitt trigger input falling edges external interrupt with pull up 1 0 N CH open drain output mode 1 1 N CH open drain output mode with pull up 3 and 2 Port 2 P2 5 Configuration Bits 0 0 Schmitt trigger input rising edge external interrupt 0 1 Schmitt trigger input falling edges external interrupt with pull up 1 0 N CH open drai...

Page 49: ...n Bits 0 0 Schmitt trigger input rising edge external interrupt 0 1 Schmitt trigger input falling edges external interrupt with pull up 1 0 N CH open drain output mode 1 1 N CH open drain output mode with pull up 3 and 2 Port 2 P2 1 Configuration Bits 0 0 Schmitt trigger input rising edge external interrupt 0 1 Schmitt trigger input falling edges external interrupt with pull up 1 0 N CH open drain...

Page 50: ...errupt disable 1 External interrupt enable 5 P2 5 Interrupt Enable Bit 0 External interrupt disable 1 External interrupt enable 4 P2 4 Interrupt Enable Bit 0 External interrupt disable 1 External interrupt enable 3 P2 3 Interrupt Enable Bit 0 External interrupt disable 1 External interrupt enable 2 P2 2 Interrupt Enable Bit 0 External interrupt disable 1 External interrupt enable 1 P2 1 Interrupt ...

Page 51: ...Pending when read no effect when write 4 P2 4 Interrupt Pending Bit 0 No pending when read clear pending bit when write 1 Pending when read no effect when write 3 P2 3 Interrupt Pending Bit 0 No pending when read clear pending bit when write 1 Pending when read no effect when write 2 P2 2 Interrupt Pending Bit 0 No pending when read clear pending bit when write 1 Pending when read no effect when w...

Page 52: ...tput CLO mode CLO comes from system clock circuit 1 0 Push pull output 1 1 N channel open drain output mode 5 and 4 Port 3 P3 2 Configuration Bits 0 x Schmitt trigger input 1 0 Push pull output 1 1 N channel open drain output mode 3 and 2 Port 3 P3 1 Configuration Bits 0 x Schmitt trigger input 1 0 Push pull output 1 1 N channel open drain output mode 1 and 0 Port 3 P3 0 Configuration Bits 0 x Sch...

Page 53: ...4 P4 2 Configuration Control Bits 0 0 Schmitt trigger input falling edge external interrupt with pull up 0 1 N CH open drain output mode with pull up 1 0 N CH open drain output mode 1 1 Output pull pull mode 3 and 2 Port 4 P4 1 Configuration Control Bits 0 0 Schmitt trigger input falling edge external interrupt with pull up 0 1 N CH open drain output mode with pull up 1 0 N CH open drain output mo...

Page 54: ...able 4 P4 0 Interrupt Enable Bit 0 External interrupt disable 1 External interrupt enable 3 P4 3 Interrupt Pending Bit 0 No pending when bit is read clear pending bit when bit is write 1 Pending when bit is read no effect when bit is write 2 P4 2 Interrupt Pending Bit 0 No pending when bit is read clear pending bit when bit is write 1 Pending when bit is read no effect when bit is write 1 P4 1 Int...

Page 55: ...P6008 1 RESUME Signal Sending Bit 0 RESUME signal is ended 1 While in suspend state if the MCU wants to initiate a resume it writes a 1 to this register for 10ms maximum of 15ms and clears this register In suspend mode if this bit is a 1 USB generates resume signaling 0 SUSPEND Status Bit 0 Cleared when MCU writes a zero to SEND_RESUME or function receives resume signal from the host while in susp...

Page 56: ... R W R W R W 7 3 Not used for KS86C6004 C6008 P6008 2 Global Interrupt Enable Bit note 0 Disable global interrupt processing 1 Enable global interrupt processing 1 and 0 Page Selection Bits 0 0 Addressing page 0 locations for KS86C6004 C6008 P6008 Other values Enable global interrupt processing NOTE SYM must be selected bit 1 and 0 into 00 for KS86C6004 C6008 P6008 ...

Page 57: ...d whenever T0DATA value equals to T0CNT value 0 1 Invalid selection 1 0 1 1 Overflow mode OVF interrupt can occur 3 T0 Counter Clear Bit T0CLR 0 No effect when written 1 Clear T0 counter 2 T0 Overflow Interrupt Enable Bit T0OVF 0 Disable T0 overflow interrupt 1 Enable T0 overflow interrupt 1 T0 Match Interrupt Enable Bit T0INT 0 Disable T0 match interrupt 1 Enable T0 match interrupt 0 T0 Interrupt...

Page 58: ...ceived this bit gets set 2 SUSPEND Interrupt Pending Bit 0 No effect once read this bit is cleared automatically 1 This bit is set when suspend signaling is received 1 ENDPOINT1 Interrupt Pending Bit 0 No effect once read this bit is cleared automatically 1 This bit is set when endpoint1 needs to be serviced 0 ENDPOINT1 Interrupt Pending Bit 0 No effect once read this bit is cleared automatically ...

Page 59: ...d Write R W R W R W R W R W R W R W R W 7 3 Not used for KS86C6004 C6008 P6008 2 SUSPEND RESUME Interrupt Enable Bit 0 Disable SUSPEND and RESEME interrupt 1 Enable SUSPEND and RESEME interrupt 1 ENDPOINT1 Interrupt Pending Bit 0 Disable ENDPOINT 1 interrupt 1 Enable ENDPOINT 1 interrupt 0 ENDPOINT1 Interrupt Pending Bit 0 Disable ENDPOINT 0 interrupt 1 Enable ENDPOINT 0 interrupt ...

Page 60: ...T USB RESET Register FFH Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 1 Read Write R W R W R W R W R W R W R W R W 7 1 Not used for KS86C6004 C6008 P6008 0 USB Reset Signal Receive Bit 0 No effect this is automatically cleared once read 1 This bit is set when host send USB reset signal ...

Page 61: ...CONTROL REGISTERS KS86C6004 C6008 P6008 MICROCONTROLLER Preliminary Spec 4 30 NOTES ...

Page 62: ...ic interrupt level and source The system level control points in the interrupt structure are therefore Global interrupt enable and disable by EI and DI instructions Interrupt source enable and disable settings in the corresponding peripheral control register s ENABLE DISABLE INTERRUPT INSTRUCTIONS EI DI The system mode register SYM DFH is used to enable and disable interrupt processing SYM 2 is th...

Page 63: ...broutine IRET occurs INTERRUPT PRIORITY Because there is not a interrupt priority register in SAM87RI the order of service is determined by a sequence of source which is executed in interrupt service routine S Q R EI INSTRUCTION EXECUTION RESET SOURCE INTERRUPTS VECTOR INTERRUPT CYCLE GLOBAL INTERRUPT CONTROL EI DI instructions INTERRUPT PENDING REGISTER SOURCE INTERRUPT ENABLE INTERRUPT PRIORITY ...

Page 64: ...the following processing sequence 1 Reset clear to 0 the global interrupt enable bit in the SYM register DI SYM 2 0 to disable all subsequent interrupts 2 Save the program counter and status flags to stack 3 Branch to the interrupt vector to fetch the service routine s address 4 Pass control to the interrupt service routine When the interrupt service routine is completed an Interrupt Return instru...

Page 65: ...pt Timer 0 Overflow Interrupt P0 X External Interrupt P2 X External Interrupt PENDING BITS 0000H ENABLE DISABLE T0CON 0 EI DI SYM 2 T0CON 1 T0CON 2 P0PND X P0INT X P2PND X P2INT X P4INTPND 0 P4INTPND 4 P4INTPND 1 P4INTPND 5 P4INTPND 2 P4INTPND 6 P4INTPND 3 P4INTPND 7 USBPND 0 USBINT 0 P4 0 External Interrupt P4 1 External Interrupt P4 2 External Interrupt P4 3 External Interrupt Endpoint 0 Interru...

Page 66: ...tate and shift operations complete the powerful data manipulation capabilities of the SAM87RI instruction set REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 13 bit program memory or data memory addresses For detailed information about register addressing pleas...

Page 67: ...st src Load external data memory and decrement LDCI dst src Load program memory and increment LDEI dst src Load external data memory and increment POP dst Pop from stack PUSH src Push to stack Arithmetic Instructions ADC dst src Add with carry ADD dst src Add CP dst src Compare DEC dst Decrement INC dst Increment SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src L...

Page 68: ...t Jump relative on condition code RET Return Bit Manipulation Instructions TCM dst src Test complement under mask TM dst src Test under mask Rotate and Shift Instructions RL dst Rotate left RLC dst Rotate left through carry RR dst Rotate right RRC dst Rotate right through carry SRA dst Shift right arithmetic CPU Control Instructions CCF Complement carry flag DI Disable interrupts EI Enable interru...

Page 69: ...arry flag C Zero flag Z Sign flag S Overflow flag V Figure 6 1 System Flags Register FLAGS FLAG DESCRIPTIONS Overflow Flag FLAGS 4 V The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is also cleared to 0 following logic operations Sign Flag FLAGS 5 S Following arithmetic logic rotate or shift operations the sign bit identifies the state ...

Page 70: ...ared to logic zero 1 Set to logic one Set or cleared according to operation Value is unaffected x Value is undefined Table 6 3 Instruction Set Symbols Symbol Description dst Destination operand src Source operand Indirect register address prefix PC Program counter FLAGS Flags register D5H Immediate operand or register address prefix H Hexadecimal number suffix D Decimal number suffix B Binary numb...

Page 71: ...n n 0 15 IR Indirect register or indirect working register Rn or reg reg 0 255 n 0 15 Irr Indirect working register pair only RRp p 0 2 14 IRR Indirect register pair or indirect working register pair RRp or reg reg 0 254 even only where p 0 2 14 X Indexed addressing mode reg Rn reg 0 255 n 0 15 XS Indexed short offset addressing mode addr RRp addr range 128 to 127 where p 0 2 14 XL Indexed long of...

Page 72: ...Ir2 OR R2 R1 OR IR2 R1 OR R1 IM 5 POP R1 POP IR1 AND r1 r2 AND r1 Ir2 AND R2 R1 AND IR2 R1 AND R1 IM N 6 COM R1 COM IR1 TCM r1 r2 TCM r1 Ir2 TCM R2 R1 TCM IR2 R1 TCM R1 IM I 7 PUSH R2 PUSH IR2 TM r1 r2 TM r1 Ir2 TM R2 R1 TM IR2 R1 TM R1 IM B 8 LD r1 x r2 B 9 RL R1 RL IR1 LD r2 x r1 L A CP r1 r2 CP r1 Ir2 CP R2 R1 CP IR2 R1 CP R1 IM LDC r1 Irr2 xL E B CLR R1 CLR IR1 XOR r1 r2 XOR r1 Ir2 XOR R2 R1 X...

Page 73: ...le 6 5 Opcode Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX 8 9 A B C D E F U 0 LD r1 R2 LD r2 R1 JR cc RA LD r1 IM JP cc DA INC r1 P 1 P 2 E 3 R 4 5 N 6 IDLE I 7 STOP B 8 DI B 9 EI L A RET E B IRET C RCF H D SCF E E CCF X F LD r1 R2 LD r2 R1 JR cc RA LD r1 IM JP cc DA INC r1 NOP ...

Page 74: ...carry C 0 0110 Z Zero Z 1 1110 NZ Not zero Z 0 1101 PL Plus S 0 0101 MI Minus S 1 0100 OV Overflow V 1 1100 NOV No overflow V 0 0110 EQ Equal Z 1 1110 NE Not equal Z 0 1001 GE Greater than or equal S XOR V 0 0001 LT Less than S XOR V 1 1010 GT Greater than Z OR S XOR V 0 0010 LE Less than or equal Z OR S XOR V 1 1111 UGE Unsigned greater than or equal C 0 0111 ULT Unsigned less than C 1 1011 UGT U...

Page 75: ...ility and for fast referencing The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format ...

Page 76: ...ic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 6 12 r r 13 r lr opc src dst 3 10 14 R R 15 R IR opc dst src 3 10 16 R IM Exam...

Page 77: ...oth operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if a carry from the low order nibble occurred Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 6 02 r r 03 r lr opc src dst 3 10 04 R R 05 R IR opc dst src 3 10 06 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH ADD R1 R2 R1 15H R...

Page 78: ...bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 6 52 r r 53 r lr opc src dst 3 10 54 R R 55 R IR opc dst src 3 10 56 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH AND R1 R2 R1 02H R2 03H AND R1 R2 R1 02H R2 03H AND 01H 02H Register 01H 01H register 02H 03H AND 01H 02...

Page 79: ... opc dst 2 18 F4 IRR Examples Given R0 15H R1 21H PC 1A47H and SP 0B2H CALL 1521H SP 0B0H Memory locations 00H 1AH 01H 4AH where 4AH is the address that follows the instruction CALL RR0 SP 0B0H 00H 1AH 01H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0B2H the statement CALL 1521H pushes the current PC value onto the top of the stack The st...

Page 80: ... 1 the value of the carry flag is changed to logic zero if C 0 the value of the carry flag is changed to logic one Flags C Complemented No other flags are affected Format Bytes Cycles Opcode Hex opc 1 6 EF Example Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register 0D5H changing its value from logic zero to logic one ...

Page 81: ...pcode Hex Addr Mode dst opc dst 2 6 B0 R B1 IR Examples Given Register 00H 4FH register 01H 02H and register 02H 5EH CLR 00H Register 00H 00H CLR 01H Register 01H 02H register 02H 00H In Register R addressing mode the statement CLR 00H clears the destination register 00H value to 00H In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register val...

Page 82: ... D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 6 60 R 61 IR Examples Given R1 07H and register 07H 0F1H COM R1 R1 0F8H COM R1 R1 07H register 07H 0EH In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and vice versa leaving the value 0F...

Page 83: ...d Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 6 A2 r r A3 r lr opc src dst 3 10 A4 R R A5 R IR opc dst src 3 10 A6 R IM Examples 1 Given R1 02H and R2 03H CP R1 R2 Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination ...

Page 84: ...hat is dst value is 128 80H and result value is 127 7FH cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 6 00 R 01 IR Examples Given R1 03H and register 03H 10H DEC R1 R1 02H DEC R1 Register 03H 0FH In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H I...

Page 85: ...rrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 6 8F Example Given SYM 04H DI If the value of the SYM register is 04H the statement DI leaves the new value 00H in the register and clears SYM 2 to 0 disabling inter...

Page 86: ...upt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the EI instruction Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 6 9F Example Given SYM 00H EI If the SYM register contains the value 00H that is if interrupts are currently disabled the statement EI sets the SYM register to 04H enabling all interr...

Page 87: ...instruction stops the CPU clock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc 1 3 6F Example The instruction IDLE stops the CPU clock but not the system clock ...

Page 88: ... H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst dst opc 1 6 rE r r 0 to F opc dst 2 6 20 R 21 IR Examples Given R0 1BH register 00H 0CH and register 1BH 0FH INC R0 R0 1CH INC 00H Register 00H 0DH INC R0 R0 1BH register 01H 10H In the first example if destination working register R0 contains the value 1BH the statement INC R0 leaves the value 1CH in that same register The next example sh...

Page 89: ... PC SP SP SP 2 SYM 2 1 This instruction is used at the end of an interrupt service routine It restores the flag register and the program counter It also re enables global interrupts Flags All flags are restored to their original settings that is the settings before the interrupt occurred Format IRET Normal Bytes Cycles Opcode Hex opc 1 16 BF ...

Page 90: ...r a conditional jump and the 2 byte format for an unconditional jump 2 In the first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits 3 For a conditional jump execution time is 12 cycles if the jump is taken or 10 cycles if it is not taken Examples Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL_W LABEL_W 1000H P...

Page 91: ...ram counter is taken to be the address of the first instruction byte following the JR statement Flags No flags are affected Format 1 Bytes Cycles Opcode Hex Addr Mode dst cc opc dst 2 10 12 2 ccB RA cc 0 to F NOTES 1 In the first byte of the two byte instruction format the condition code and the opcode are each four bits 2 Instruction execution time is 12 cycles if the jump is taken or 10 cycles i...

Page 92: ...ination The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src dst opc src 2 6 rC r IM 6 r8 r R src opc dst 2 6 r9 R r r 0 to F opc dst src 2 6 C7 r lr 6 D7 Ir r opc src dst 3 10 E4 R R 10 E5 R IR opc dst src 3 10 E6 R IM 10 D6 IR IM opc src dst 3 10 F5 IR R opc dst src x 3 10 87 r x r opc src dst x 3 10 97 x r r ...

Page 93: ...0H LD R0 01H R0 20H register 01H 20H LD 01H R0 Register 01H 01H R0 01H LD R1 R0 R1 20H R0 01H LD R0 R1 R0 01H R1 0AH register 01H 0AH LD 00H 01H Register 00H 20H register 01H 20H LD 02H 00H Register 02H 20H register 00H 01H LD 00H 0AH Register 00H 0AH LD 00H 10H Register 00H 01H register 01H 10H LD 00H 02H Register 00H 01H register 01H 02 register 02H 02H LD R0 LOOP R1 R0 0FFH R1 0AH LD LOOP R0 R1...

Page 94: ...Irr r 3 opc dst src XS 3 18 E7 r XS rr 4 opc src dst XS 3 18 F7 XS rr r 5 opc dst src XLL XLH 4 20 A7 r XL rr 6 opc src dst XLL XLH 4 20 B7 XL rr r 7 opc dst 0000 DAL DAH 4 20 A7 r DA 8 opc src 0000 DAL DAH 4 20 B7 DA r 9 opc dst 0001 DAL DAH 4 20 A7 r DA 10 opc src 0001 DAL DAH 4 20 B7 DA r NOTES 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 For f...

Page 95: ...DC R0 01H RR4 R0 contents of program memory location 0061H 01H RR4 R0 AAH R2 00H R3 60H LDE R0 01H RR4 R0 contents of external data memory location 0061H 01H RR4 R0 BBH R4 00H R5 60H LDC 01H RR4 R0 11H contents of R0 is loaded into program memory location 0061H 01H 0060H LDE 01H RR4 R0 11H contents of R0 is loaded into external data memory location 0061H 01H 0060H LDC R0 1000H RR2 R0 contents of p...

Page 96: ...s of the source are unaffected LDCD references program memory and LDED references external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 16 E2 r Irr Examples Given R6 10H R7 33H R8 12H program memory location 1033H 0CDH and external data memory locati...

Page 97: ...tents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes Irr even for program memory and odd for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 16 E3 r Irr Examples Given R6 10H R7 33H R8 12H program memory locations 1033H 0CDH and 1034H 0C5H external data memory locations 10...

Page 98: ...he CPU executes this instruction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 6 FF Example When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ...

Page 99: ...Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 6 42 r r 6 43 r lr opc src dst 3 10 44 R R 10 45 R IR opc dst src 3 10 46 R IM Examples Given R0 15H R1 2AH R2 01H register 00H 08H register 01H 37H and register 08H 8AH OR R0 R1 R0 3FH R1 2AH OR R0 R2 R0 37H R2 01H register 01H 37H OR 00H 01H Register 00H 3FH register 01H 37H OR 01H 00H Register 00H 08H registe...

Page 100: ... Cycles Opcode Hex Addr Mode dst opc dst 2 10 50 R 10 51 IR Examples Given Register 00H 01H register 01H 1BH SP 0D9H 0BBH and stack register 0BBH 55H POP 00H Register 00H 55H SP 0BCH POP 00H Register 00H 01H register 01H 55H SP 0BCH In the first example general register 00H contains the value 01H The statement POP 00H loads the contents of location 0BBH 55H into destination register 00H and then i...

Page 101: ...ected Format Bytes Cycles Opcode Hex Addr Mode dst opc src 2 10 70 R 12 71 IR Examples Given Register 40H 4FH register 4FH 0AAH SP 0C0H PUSH 40H Register 40H 4FH stack register 0BFH 4FH SP 0BFH PUSH 40H Register 40H 4FH register 4FH 0AAH stack register 0BFH 0AAH SP 0BFH In the first example if the stack pointer contains the value 0C0H and general register 40H the value 4FH the statement PUSH 40H d...

Page 102: ...CF Reset Carry Flag RCF RCF Operation C 0 The carry flag is cleared to logic zero regardless of its previous value Flags C Cleared to 0 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 6 CF Example Given C 1 or 0 The instruction RCF clears the carry flag C to logic zero ...

Page 103: ...program counter The next statement that is executed is the one that is addressed by the new program counter value Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 AF Example Given SP 0BCH SP 101AH and PC 1234 RET PC 101AH SP 0BEH The statement RET pops the contents of stack pointer location 0BCH 10H into the high byte of the program counter The stack pointer then pops the value ...

Page 104: ...ared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 6 90 R 6 91 IR Examples Given Register 00H 0AAH register 01H 02H and register 02H 17H RL 00H Register 00H 55H C 1 RL 01H Register 01H ...

Page 105: ...d otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 6 10 R 6 11 IR Examples Given Register 00H 0AAH register 01H 02H and register 02H 17H C 0 RLC 00H Register 00H 54H C 1 RLC 01H Register 01H 02H register 02H 2EH C 0 In the first example if...

Page 106: ... if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 6 E0 R 6 E1 IR Examples Given Register 00H 31H register 01H 02H and register 02H 17H RR 00H Register 00H 98H C 1 RR 01H Register 01H 02H register 02H 8BH C 1 In the first example if general register 00H co...

Page 107: ...otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 6 C0 R 6 C1 IR Examples Given Register 00H 55H register 01H 02H register 02H 17H and C 0 RRC 00H Register 00H 2AH C 1 RRC 01H Register 01H 02H register 02H 0BH C 1 In the first example if ge...

Page 108: ...etic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 6 32 r r 6 33 r lr opc src dst 3...

Page 109: ...minary Spec 6 44 SCF Set Carry Flag SCF Operation C 1 The carry flag C is set to logic one regardless of its previous value Flags C Set to 1 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 6 DF Example The statement SCF sets the carry flag to logic one ...

Page 110: ... is 0 cleared otherwise S Set if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 6 D0 R 6 D1 IR Examples Given Register 00H 9AH register 02H 03H register 03H 0BCH and C 1 SRA 00H Register 00H 0CD C 0 SRA 02H Register 02H 03H register 03H 0DEH C 0 In the first example if general register 00H contains the...

Page 111: ... of on chip CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or External interrupt input For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc 1 3 ...

Page 112: ...urce operand cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 6 22 r r 6 23 r lr opc src dst 3 10 24 R R 10 25 R IR opc dst src 3 10 26 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03...

Page 113: ...d otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 6 62 r r 6 63 r lr opc src dst 3 10 64 R R 10 65 R IR opc dst src 3 10 66 R IM Examples Given R0 0C7H R1 02H R2 12H register 00H 2BH register 01H 02H and register 02H 23H TCM R0 R1 R0 0C7H R1 02H Z 1 TCM R0 R1 R0 0C7H R1 02H register 02H 23H Z 0 TCM 00H 01H Register 00H 2BH re...

Page 114: ...D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 6 72 r r 6 73 r lr opc src dst 3 10 74 R R 10 75 R IR opc dst src 3 10 76 R IM Examples Given R0 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H TM R0 R1 R0 0C7H R1 02H Z 0 TM R0 R1 R0 0C7H R1 02H register 02H 23H Z 0 TM 00H 01H Register 00H 2BH register 01H 02H Z 0 TM 00H 01H Registe...

Page 115: ...V Always reset to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 6 B2 r r 6 B3 r lr opc src dst 3 10 B4 R R 10 B5 R IR opc dst src 3 10 B6 R IM Examples Given R0 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H XOR R0 R1 R0 0C5H R1 02H XOR R0 R1 R0 0E4H R1 02H register 02H 23H XOR 00H 01H Register 00H 29H register 01H 02H XOR 00H...

Page 116: ...Clock Circuit RESET and Power Down I O Ports Basic Timer and Timer 0 USB Block Universal Serial Bus Electrical Data Mechanical Data KS86P6008 OTP ...

Page 117: ... The two power down modes Stop mode and Idle mode affect clock oscillation as follows In Stop mode the main oscillator freezes halting the CPU and peripherals The contents of the register file and current system register values are retained Stop mode is released and the oscillator started by a reset operation or by an external interrupt with RC delay noise filter for KS86C6004 C6008 P6008 INT0 INT...

Page 118: ...e IRQ wake up enable bit is CLKCON 7 After a reset the external interrupt oscillator wake up function is enabled the main oscillator is activated and the fOSC 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed to fOSC fOSC 2 or fOSC 8 MSB LSB 7 6 5 4 3 2 1 0 SYSTEM CLOCK CONTROL REGISTER CLKCON D4H R W Not used for KS86C6004 C6008 P6008 D...

Page 119: ...ONTROLLERS Preliminary Spec CLOCK CIRCUIT 3 STOP Instruction NOISE FILTER MAIN OSC CLKCON 7 INT Pin Oscillator Wake up 1 2 1 8 1 16 M U X CLKCON 3 4 CPU CLOCK P3CON P3 3 CLO Oscillator STOP Figure 7 3 System Clock Circuit Diagram ...

Page 120: ...CLOCK CIRCUIT KS86C6004 C6008 P6008 MICROCONTROLLERS Preliminary Spec 7 4 NOTES ...

Page 121: ...set operation starts All system and peripheral control registers are then set to their default hardware reset values see Table 8 1 The following sequence of events occurs during a reset operation All interrupts are disabled The watchdog function basic timer is enabled Ports 0 4 are set to Schmitt trigger input mode and all pull up resistors are disabled Peripheral control and data registers are di...

Page 122: ...KCON 4 register values remain unchanged and the currently selected clock value is used If you use an external interrupt for Stop mode release you can also program the duration of the oscillation stabilization interval To do this you must make the appropriate control and clock settings before entering Stop mode The external interrupt is serviced when the Stop mode release occurs Following the IRET ...

Page 123: ...R15 192 207 C0H CFH x x x x x x x x Timer 0 counter T0CNT 208 D0H 0 0 0 0 0 0 0 0 Timer 0 data register T0DATA 209 D1H 1 1 1 1 1 1 1 1 Timer 0 control register T0CON 210 D2H 0 0 0 0 0 0 0 0 Location D3H is not mapped Clock control register CLKCON 212 D4H 0 0 0 0 0 0 0 0 System flags register FLAGS 213 D5H 0 0 0 0 Locations D6H D8H are not mapped Port 0 interrupt control register P0INT 216 D8H 0 0 ...

Page 124: ...register P2INT 236 ECH 0 0 0 0 0 0 0 0 Port 2 interrupt pending register P2PND 237 EDH 0 0 0 0 0 0 0 0 Port 4 control register P4CON 238 EEH 0 0 0 0 0 0 0 0 Port 4 interrupt enable pending register P4INTPND 239 EFH 0 0 0 0 0 0 0 0 USB function address register FADDR 240 F0H 0 0 0 0 0 0 0 0 Control endpoint status register EP0CSR 241 F1H 0 0 0 0 0 0 0 0 Interrupt endpoint status register EP1CSR 242...

Page 125: ...n output Port0 can be individually configured as external interrupt inputs Pull up resistors are assignable by software Bit 1 Bit programmable I O port for Schmitt trigger input or open drain output Pull up resistors are assignable by software Bit 2 Bit programmable I O port for Schmitt trigger input or open drain output Port2 can be individually configured as external interrupt inputs Pull up res...

Page 126: ...er Summary Register Name Mnemonic Decimal Hex R W Port 0 data register P0 224 E0H R W Port 1 data register P1 225 E1H R W Port 2 data register P2 226 E2H R W Port 3 data register P3 227 E3H R W Port 4 data register P4 228 E4H R W MSB LSB 7 6 5 4 3 2 1 0 I O PORT n DATA REGISTER n 0 Pn 7 Pn 6 Pn 5 Pn 4 Pn 3 Pn 2 Pn 1 Pn 0 NOTE Because only the four lower nibble pins of port 3 and port 4 are mapped ...

Page 127: ...igger inputs In typical keyboard controller applications the sixteen port 0 and port 1 pins can be used to check pressed key from keyboard matrix by generating keystrobe output signals 7 5 3 1 0 0 1 1 6 4 2 0 0 1 0 1 Port Mode Selection Schmitt trigger input rising edge external interrupt mode Schmitt trigger input falling edge external interrupt mode with pull up N CH open drain output mode N CH ...

Page 128: ...n Schmitt trigger input mode Schmitt trigger input mode with pull up N CH open drain output mode N CH open drain output mode with pull up MSB LSB 7 6 5 4 3 2 1 0 PORT 1 CONTROL REGISTERS P1CONH E8H R W P1CONL E9H R W P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 P1CONH P1CONL Figure 9 3 Port 1 Control Registers P1CONH P1CONL ...

Page 129: ...r P2INT you can configure specific port 2 pins to generate interrupt requests when rising or falling signal edges are detected The application program polls the port 2 interrupt pending register P2PND to detect interrupt requests When an interrupt request is acknowledged the corresponding pending bit must be cleared by the interrupt service routine In case of keyboard applications the port 2 pins ...

Page 130: ...2 1 0 P2 7 INT0 P2 6 INT0 P2 5 INT0 P2 4 INT0 P2 3 INT0 P2 2 INT0 P2 1 INT0 P2 0 INT0 Figure 9 5 Port 2 Interrupt Enable Register P2INT PORT 2 INTERRUPT PENDING REGISTER P2PND EDH R W MSB LSB 7 6 5 4 3 2 1 0 P2 7 INT0 P2 6 INT0 P2 5 INT0 P2 4 INT0 P2 3 INT0 P2 2 INT0 P2 1 INT0 P2 0 INT0 Port 2 interrupt request pending bits 0 No interrupt is pending 1 Interrupt request is pending Figure 9 6 Port 2...

Page 131: ...ort 3 pins as n channel open drain outputs P3 3 can be used to system clock output CLO port MSB LSB 7 6 5 4 3 2 1 0 PORT3 CONTROL REGISTER P3CON E5H R W 5 3 1 0 1 1 4 2 0 x 0 1 Port Mode Selection Pin 3 2 Pin 3 0 Schmitt trigger input Push pull output N CH open drain output P3 3 CLO P3 2 P3 1 P3 0 7 0 0 1 1 6 0 1 0 1 Port Mode Selection Pin 3 3 Schmitt trigger input System Clock output CLO mode CL...

Page 132: ... registers used for interrupt control P4INTPND EFH By setting bits in the port 4 interrupt enable and pending register P4INTPND 7 P4INTPND 4 you can configure specific port 4 pins to generate interrupt requests when falling signal edges are detected The application program polls the interrupt pending register P4INTPND 3 P4INTPND 0 to detect interrupt requests When an interrupt request is acknowled...

Page 133: ...rupt control settings 0 Disable interrupt at P4 n pin 1 Enable interrupt at P4 n pin P4INTPND 3 0 Port 4 interrupt pending bits 0 No interrupt request pending 1 Interrupt request is pending MSB LSB 7 6 5 4 3 2 1 0 P4 3 INT1 P4 2 INT1 P4 1 INT1 P4 0 INT1 P4 3 INT1 P4 2 INT1 P4 1 INT1 P4 0 INT1 Figure 9 9 Port 4 Interrupt Enable and Pending Register P4INTPND ...

Page 134: ...I O PORTS KS86C6004 C6008 P6008 MICROCONTROLLER Preliminary Spec 9 10 NOTES ...

Page 135: ...tion interval after a reset or a Stop mode release The functional components of the basic timer block are Clock frequency divider fOSC divided by 4096 1024 or 128 with multiplexer 8 bit basic timer counter BTCNT DDH read only Basic timer control register BTCON DCH read write Timer 0 Timer 0 has two operating modes one of which you select by the appropriate T0CON setting Interval timer mode Overflo...

Page 136: ...imer register control bits BTCON 7 BTCON 4 The 8 bit basic timer counter BTCNT can be cleared at any time during normal operation by writing a 1 to BTCON 1 To clear the frequency dividers for both the basic timer input clock and the timer 0 clock you write a 1 to BTCON 0 MSB LSB 7 6 5 4 3 2 1 0 BASIC TIMER CONTROL REGISTER BTCON DCH R W Watchdog timer enable bits 1010B Disable watchdog function Ot...

Page 137: ...If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop mode has been released by an external interrupt In Stop mode whenever a reset or an external interrupt occurs the oscillator starts The BTCNT value then starts increa...

Page 138: ...tWAIT when it is released by a Power on reset is 4096x16 fosc trst RC R is external resister and C is on chip capacitor tWAIT 4096x16x1 fosc Basic timer increment and CPU operations are IDLE mode Oscillation stabilization time Normal operating mode 00000B 10000B 0 8 VDD Reset Release Voltage trst RC Oscillator stabilization time 0 8 VDD BTCNT clock Figure 10 2 Oscillation Stabilization Time on RES...

Page 139: ...perating mode STOP mode Oscillation stabilization time Normal operating mode 00000B 10000B tWAIT When fosc is 6 MHz tWAIT BTCON 3 BTCON 2 5 46 ms 4096 x 16 fosc 0 0 1 365 ms 0 1 0 17 ms 1 0 1 1 1024 x 16 fosc 128 x 16 fosc Invalid setting NOTE Duration of the oscillator stabilization wait time tWAIT it is released by an interrupt is determined by the setting in basic timer control register BTCON F...

Page 140: ...upt pending condition the application program polls T0CON 0 When a 1 is detected a timer 0 match capture interrupt is pending When the interrupt request has been serviced the pending condition must be cleared by software by writing a 0 to the timer 0 interrupt pending bit T0CON 0 MSB LSB 7 6 5 4 3 2 1 0 TIMER 0 CONTROL REGISTER T0CON D2H R W Timer 0 interrupt pending bit 0 No interrupt pending 0 C...

Page 141: ... counter will increment until it reaches 10H At this point the T0 match interrupt is generated the counter value is reset and counting resumes Overflow Mode In overflow mode a overflow signal is generated regardless of the value written to the T0 reference data register when the counter value is overflowed The overflow signal generates a timer 0 overflow interrupt and then T0 counter is cleared Co...

Page 142: ... Only 8 Bit Comparator R Bits 5 4 Match Signal Bit 3 T0CLR Bit 1 T0INT IRQ Match Overflow 8 8 Bits 7 6 Bit 0 8 Bit Basic Counter BTCNT Read Only Bit 2 OVINT T0DATA Buffer Register Overflow OVF When BTCNT 4 is set after releasing from RESET or STOP mode CPU clock starts Bits 3 2 Write 1010xxxxB to disable Bits 7 6 5 4 1 4096 1 256 1 8 T0DATA When 8 Bit counter is cleared this buffer is open Data Bu...

Page 143: ...KS86C6004 C6008 P6008 MICROCONTROLLER Preliminary Spec BASIC TIMER and TIMER 0 10 9 NOTES ...

Page 144: ... describe as a microcontroller with SAM 87RI core with an on chip USB peripheral as can be seen in figure 11 1 The KS86C6004 C6008 P6008 comes equipped with Serial Interface Engine SIE which handles the communication protocol of the USB The KS86C6004 C6008 P6008 supports the following control logic packet decoding generation CRC generation checking NRZI encoding decoding Sync detection EOP end of ...

Page 145: ...S86C6004 C6008 P6008 supports three packet types Token Data and Handshake Each transaction starts when the host controller sends a Token Packet to the USB device The Token packets are generated by the USB host and decoded by the USB device A Token Packet includes the type description direction of the transaction USB device address and the endpoint number Data and Handshake packets are both decoded...

Page 146: ... and sets DATA_END bit3 in the EP0CSR register The function controller use this register s value to decode USB Token packet address At reset if the device is not yet configured the value is reset to 0 MSB LSB 7 6 5 4 3 2 1 0 USB Function Address Register FADDR F0H R W Not used for KS86C6004 C6008 P6008 7 bit programming device address This register maintains the USB address assigned by the host Th...

Page 147: ...t packet of data into the FIFO and at the same time IN_PKT_RDY bit is set While it clears OUT_PKT_RDY bit after unloading the last packet of data For a zero length data phase when it clears OUT_PKT_RDY bit and sets IN_PKT_RDY bit Bit2 SENT_STALL USB sets this bit if a control transaction has ended due to a protocol violation An interrupt is generated when this bit gets set MCU clears this bit to e...

Page 148: ...pec UNIVERSAL SERIAL BUS 11 5 MSB LSB 7 6 5 4 3 2 1 0 CLEAR_ SETUP_END CLEAR_ OUT_PKT_RDY SEND_STALL SETUP_END DATA_END SENT_STALL OUT_PKT_RDY IN_PKT_RDY Control Endpoint Status Register EP0CSR F1H R W Figure 11 3 Control Endpoint Status Register EP0CSR ...

Page 149: ..._PKT_RDY to be cleared for the flush to take place Bit1 FORCE_STALL MCU writes 1 to this register to issue a STALL Handshake to USB MCU clears this bit to end the STALL condition Bit0 IN_PKT_RDY MCU sets this bit after writing a packet of data into Endpoint 1 FIFO USB clears this bit once the packet has been successfully sent to the Host An interrupt is generated when USB clears this bit so MCU ca...

Page 150: ...s located at address F5H and is able to write USB INTERRUPT PENDING REGISTER USBPND USBPND register has the interrupt bits for endpoints and power management This register is cleared once read by MCU While any one of the bits is set an interrupt is generated USBPND is located at address F6H and is read write addressable Bit7 4 Not used Bit3 RESUME_PND While in suspend mode if resume signaling is r...

Page 151: ...nables bits for suspend and resume is combined into a single bit bit 2 Bit7 3 Not used Bit2 ENABLE_SUSPEND_RESUME_INT 1 Enable SUSPEND and RESUME INTERRUPT 0 Disable SUSPEND and RESUME INTERRUPT default Bit1 ENABLE_ENDPT1_INT 1 Enable ENDPOINT 1 INTERRUPT default 0 Disable ENDPOINT 1 INTERRUPT Bit0 ENABLE_ENDPT0_INT 1 Enable ENDPOINT 0 INTERRUPT default 0 Disable ENDPOINT 0 INTERRUPT MSB LSB 7 6 5...

Page 152: ...to initiate RESUME it writes 1 to this register for 10ms maximum of 15 ms and clears this register In SUSPEND mode if this bit reads 1 USB generates RESUME signaling Bit0 SUSPEND_STATE Suspend state is set when the MCU sets suspend interrupt This bit is cleared automatically when MCU writes 0 to SEND_RESUME bit to end the RESUME signaling after SEND_RESUME is set for 10 ms MCU receives RESUMES sig...

Page 153: ...from the Host when there has been no activities on UBS for a certain period of time This register is located at address FFH and is read write addressable Bit7 1 Not used Bit0 USBRST This bit is set when the Host issues an USB reset signal MSB LSB 7 6 5 4 3 2 1 0 USB RESET Register USBRST FFH R W Not used USBRST Figure 11 8 USB RESET Register USBRST ...

Page 154: ...gs D C electrical characteristics Input Output capacitance A C electrical characteristics Input timing for external interrupt Ports 0 2 and 4 Input timing for RESET Oscillator characteristics Oscillation stabilization time Clock timing measurement points at XIN Data retention supply voltage in Stop mode Stop mode release timing when initiated by a reset Stop mode release timing when initiated by a...

Page 155: ... 3 to 6 5 V Input Voltage VIN All input ports 0 3 to VDD 0 3 V Output Voltage VO All output ports 0 3 to VDD 0 3 V Output Current High IOH One I O pin active 18 mA All I O pins active 60 Output Current Low IOL One I O pin active 30 mA Total pin current for ports 3 100 Total pin current for ports 0 1 2 4 100 Operating Temperature TA 40 to 85 C Storage Temperature TSTG 65 to 150 C ...

Page 156: ...rts 0 1 and 2 VDD 1 0 V Output Low Voltage VOL IOL 1 mA All output port 0 4 V Output High Leakage Current ILOH 1 VOUT VDD All I O pins and output pins 3 µA Output Low Leakage Current ILOL 1 VOUT 0 V All I O pins and output pins 3 µA Pull up Resistors RL1 VIN 0 V Ports 0 1 2 4 25 50 100 KΩ RL2 VIN 0 V RESET only 100 220 300 Supply Current 2 IDD1 Normal operation mode 6 MHz CPU clock 5 5 12 mA IDD2 ...

Page 157: ...onnected to VSS 10 pF Output Capacitance COUT I O Capacitance CIO Table 12 4 A C Electrical Characteristics TA 40 C to 85 C VDD 4 5 V to 6 0 V Parameter Symbol Conditions Min Typ Max Unit Interrupt Input High Low Width tINTH tINTL P0 P2 and P4 200 ns RESET Input Low Width tRSL RESET 1 000 tINTL tINTH 0 8 VDD 0 2VDD Figure 12 1 Input timing for external interrupt Ports 0 2 and 4 RESET tRSL 0 2VDD F...

Page 158: ...equency 6 0 Table 12 6 Oscillation Stabilization Time TA 40 C 85 C VDD 4 5 V to 5 5 V Oscillator Test Condition Min Typ Max Unit Main Crystal fOSC 6 0 MHz 10 ms Main Ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range Oscillator Stabilization Wait Time tWAIT stop mode release time by a reset 216 fOSC tWAIT stop mode release time by an interrupt note N...

Page 159: ...ntion Supply Voltage in Stop Mode TA 40 C to 85 C Parameter Symbol Conditions Min Typ Max Unit Data Retention Supply Voltage VDDDR Stop mode 2 0 6 V Data Retention Supply Current IDDDR Stop mode VDDDR 2 0 V 300 µA XIN tXL tXH 1 fOSC VDD 0 5V 0 4 V Figure 12 3 Clock Timing Measurement Points at XIN ...

Page 160: ...ERATION IDLE MODE BASIC TIMER ACTIVE 0 8 VDD 0 2 VDD NORMAL OPERATING MODE Figure 12 4 Stop Mode Release Timing When Initiated by a Reset tWAIT VDD EXTERNAL INTERRUPT EXECUTION OF STOP INSTRUCTION VDDDR DATA RETENTION MODE STOP MODE IDLE MODE BASIC TIMER ACTIVE 0 8 VDD 0 2 VDD NORMAL OPERATING MODE Figure 12 5 Stop Mode Release Timing When Initiated by an External Interrupt ...

Page 161: ...150 150 Source EOP Width TEOPT 7 Figure 12 7 1 25 1 5 µs Differential to EOP Transition Skew TDEOP 7 Figure 12 7 40 100 ns Receiver Data Jitter Tolerance 7 Figure 12 8 At Host Upstream To Next Transition TUJR1 152 152 For Paired Transitions TUJR2 200 200 At Function Downstream To Next Transition TDJR1 75 75 For Paired Transitions TDJR2 45 45 EOP Width at Receiver 7 Figure 12 7 Must Reject as EOP T...

Page 162: ...KS86C6004 C6008 P6008 MICROCONTROLLER Preliminary Spec ELECTRICAL DATA 12 9 ...

Page 163: ...12 6 Differential Data Jitter Differential Data Lines Differential Data to SE0 Skew N x TPERIOD TDEOP Source EOP Width TEOP Receiver EOP Width T EOPR1 TEOPR2 TPERIOD Crossover Points Crossover Points Extended Figure 12 7 Differential to EOP Transition Skew and EOP Width Differential Data Lines TPERIOD TJR TJR1 TJR2 Consecutive Transitions N x TPERIOD TJR1 Paired Transitions N x TPERIOD TJR2 Figure...

Page 164: ...KS86C6004 C6008 P6008 MICROCONTROLLER Preliminary Spec ELECTRICAL DATA 12 11 NOTES ...

Page 165: ...DIP package Samsung 42 SDIP 600 and a 44 pin QFP package 44 QFP 1010B Package dimensions are shown in Figures 13 1 and 13 2 NOTE Dimensions are in millimeters 0 15 15 24 0 2 5 0 1 0 0 5 0 51MIN 3 30 0 3 5 08MAX 1 00 0 1 0 50 0 1 1 77 1 778 3 50 0 2 39 10 0 2 39 50 MAX 42 SDIP 14 00 0 2 1 21 42 22 Figure 13 1 42 Pin SDIP Package Mechanical Data 42 SDIP 600 ...

Page 166: ...iminary Spec 13 2 NOTE Dimensions are in millimeters 44 QFP 1010B 13 20 0 3 44 1 00 1 13 20 0 3 10 00 0 2 0 35 0 10 0 05 0 10 MAX 0 15 0 10 0 05 0 8 0 05 MIN 2 05 0 10 2 30 MAX 0 80 20 0 80 10 00 0 2 Figure 13 2 44 Pin QFP Package Mechanical Data 44 QFP 1010B ...

Page 167: ...ogramming requirements the KS86P6008 is ideal for use as an evaluation chip for the KS86C6004 C6008 P3 1 P3 0 INT0 P2 0 INT0 P2 1 INT0 P2 2 INT0 P2 3 INT0 P2 4 INT0 P2 5 SDAT INT0 P2 6 SCLK INT0 P2 7 VDD VDD VSS VSS1 XOUT XOUT XIN XIN TEST TEST INT1 P4 0 INT1 P4 1 RESET RESET INT1 P4 2 INT1 P4 3 P1 7 KS86P6008 42 SDIP Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 P3 2 P3 3 CLO D D...

Page 168: ...T RESET NC NC V SS2 P0 0 INT2 P0 1 INT2 P0 2 INT2 P0 3 INT2 P0 4 INT2 P0 5 INT2 P0 6 INT2 P0 7 INT2 INT0 P2 4 INT0 P2 5 INT0 P2 6 SDAT INT0 P2 7 SCLK V DD V DD V SS1 V SS X OUT X OUT X IN X IN TEST TEST P4 0 INT1 P4 1 INT1 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 KS86P6008 Top View 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 Figure 14 2 KS86P6008 Pin Assignmen...

Page 169: ...2 Comparison of KS86P6008 and KS86C6004 C6008 Features Characteristic KS86P6008 KS86C6004 C6008 Program Memory 8 Kbyte EPROM 8 Kbyte mask ROM Operating Voltage VDD 4 5 V to 5 5 V 4 5 V to 5 5 V OTP Programming Mode VDD 5 V VPP RESET 12 5 V Pin Configuration 42 SDIP 44 QFP 42 SDIP 44 QFP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12 5 V i...

Page 170: ... 4 START Address First Location VDD 5V VPP 12 5V x 0 Program One 1ms Pulse Increment X x 10 Verify 1 Byte Last Address VDD VPP 5 V Compare All Byte Device Passed Increment Address Verify Byte Device Failed PASS FAIL NO FAIL YES FAIL NO Figure 14 3 OTP Programming Algorithm ...

Page 171: ...40 C to 85 C VDD 4 5 V to 5 5 V Parameter Symbol Conditions Min Typ Max Unit Supply Current note IDD1 Normal mode 6 MHz CPU clock 5 5 12 mA IDD2 Idle mode 6 MHz CPU clock 2 2 5 IDD3 Stop mode 180 300 µA NOTE Supply current does not include current drawn through internal pull up resistors or external output current loads ...

Page 172: ...KS86P6008 OTP KS86C6004 C6008 P6008 MICROCONTROLLER Preliminary Spec 14 6 NOTES ...

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