Level 3 Repair
Distribution, transmission, or infringement of any content or data from this document without Samsung’s written authorization is strictly prohibited.
Confidential and proprietary-the contents in this service guide subject to change without prior notice.
8-47
R
9
2
0
VREG_LVS4_1.8V
TP902
C945
TP903
VREG_L9_2P85
TP900
R
9
2
6
VREG_LVS4_1.8V
VREG_L33_1.2V
R
9
2
8
R922
R917
C946
VREG_L9_2P85
R918
R
9
3
2
C944
R
9
2
7
R
9
2
1
F5
PIOS|SPI_SI
F
6
S
P
I_
V
C
C
R
9
2
9
E3
PIO2|CBSEL0
E4
PIOS|SPI_SO
E5
PIOS|SPI_SCK
E6
PIO1
F
1
V
C
C
IO
_
2
3
F2
GBIN4|PIO2
F3
PIO2|CBSEL1
F4
CRESET_B
D1
GBIN6|PIO3|DP06A
D
2
G
N
D
D
3
G
N
D
D
4
G
N
D
D5
PIOS|SPI_SS_B
D6
PIO1
E1
PIO3|DP06B
E2
GBIN5|PIO2
B5
PIO1
B6
PIO1
C1
GBIN7|PIO3|DP05B
C2
PIO3|DP05A
C3
PIO0
C4
CDONE
C5
GBIN3|PIO1
C6
PIO1
A3
GBIN1|PIO0
A
4
V
C
C
IO
_
0
1
A
5
V
P
P
_
F
A
S
T
A
6
V
P
P
_
2
V
5
B1
PIO3|DP01A
B
2
V
C
C
B3
GBIN0|PIO0
B4
GBIN2|PIO1
U905
N
C
1
N
C
2
A1
PIO3|DP01B
A2
PIO0
TP901
VREG_S4_1P8
VREG_LVS4_1.8V
R923
R
9
3
0
VREG_LVS4_1.8V
R
9
1
9
VPS_SOUND_EN
WLAN_EN
BT_EN
BT_WAKE
VSIL_A_1P2_EN
MHL_RST
FPGA_RST_N
FPGA_SPI_CLK
FPGA_MAIN_CLK
FPGA_SPI_SI
CRESET_B
IRDA_CONTROL
IRDA_IRQ
CDONE
BARCODE_EN
