Samsung DVD-905, Service Manual

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Reference Information
2-12 Samsung Electronics
2. Operation
1) Input circuit
RF data equalized in RF stage is AC-coupled via pin 50 and input as 2.1Vpp. Then, the bias voltage becomes
1.65V by means of DC bias in IC.
2) PLL circuit
The input data generates the clock necessary for the PLL circuit. PLL circuit for clock generation generates
the phase error signal through RLLD (pin 38), PDOP (pin 37), PDON (pin 36). The loop filter consists of
built-in OP Amp and external parts.
The RLLD signal occurs only when the velocity difference between clock and data is large, and it sets the PLL
oeprational velocity. RLLD signal doesnÕt occur at normal play except during searches
3) Data slicer
As the PLL generates the clocks, the slice circuit converts the analog signal to digital. that is, it switches to 1
if greater than regular reference voltage, and to 0 if less. The sliced signal may be observed at pin 34 (ED7)
with a scope. If the signal has an error, it is necessary to check that the bias of input RF signal is correct, as
well as the condensor at pin 42 (SLCO).
4) CLV circuit]
The signal is input to the circuit which generates DMO and CLV signals to control the rotation of the spindle
motor. The control signal is output via pin 54(DMO). Then, the output signal is the 3d signal (a pulse derived
from the midpoint voltage). If an error occurs in spindle motor during DVD play, check this signal.
5) Modulation and ID. Sync detection
The signal is synchronized, using the generated clocks, and Sync. signal is detected through Sync. signal
detection circuit for modulation and all other signal processes. Sync. signal canÕt be observed externally, but
the interrupt at each 1.4ms cycle may be checked on pin 23 (during normal detection, the interrupt signal is
generated periodically). It is difficult to precisely define 1.4ms cycle, because other interrupts are also
occuring.
During Sync. detection, the recorded signal is converted to data by means of an 8/16 modulation circuit.
The modulated signal is saved in memory, and interfaced externally for error correction.
7) Error correction circuit]
The data saved in external buffer memory after modulation are read by data processor sequentially for error
correction. The data with all corrections are output by request of the next stage (video decoder).
8) VBR buffering]
The disc jumps the track repeatedly on waveform while checking each signal during normal play of DVD
because it uses the VBR method (completely different from existing CD, video CD, etc). VBR play method
enhances the data efficiency to improve the screen quality twofold, by using additional data for complex
video and less data for simple video at compression. It saves the data in memory, and if the memory is full, it
stops the play instantly to reset. If the data is removed, it repeats play because the play velocity varies
according to data compression ratio. This process is known as VBR, and the used memory is known as the
track buffer (or VBR buffer). A 4MIT DRAM attached to data processor includes this function.
9) Protection circuit]
Read if protected, and key for protection release from Read-in area (starting at first disc play). These
operations are performed by TC6804 automatically.
Protection IC is located between output of data processor and input of video decoder, (the next stage).
it decodes the protected data after recognizing the key information read from disc and data status. If a disc
violates the protection method, it stops the operation and reports to Micom.