SERVICE MANUAL
Document No
Date of Origin
Date of REV
51-L-DSR004
98-10-21
PAGE REV.
0
PAGE
38 /102
S-00-005(96.03.27)
REV.1
7-9-2-4.
Check the AGC Loop as follows.
I
:
Junction
of R125 & C118
Q
:
Junction
of R131 & C121
AGC_CTL
:
Junction
of R122 & Pin 41 of U100
AGC Voltage
:
TP101
5us
Vp-p : 650mV
I
Q
figure 7-9-2-4.
I, Q signal wave form
7-9-2-5.
Check the final Decoded
Data output 'FECD' 0 to 7
7-9-2-6.
Check the Output Control
Signal as follows.
when The status of CH_SYNC
is HIGH(+3.3V)
the STB is channel
locking
and the ERROR is HIGH(+3.3V)
means there is no error
during channel
locking.
Decoded
Data
:
Pin 11,12,13,14,17,18,19
or 20 of U100
BYTE_CLK
:
TP117
F_START
:
TP114
DATA_VALID
:
TP116
CH_SYNC
:
TP119
ERROR
:
TP115