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Samsung C8274X, User Manual

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INSTRUCTION SET 

 

 

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 

6-86  

 

WFI

 

—

 

Wait for Interrupt

 

WFI

 

Operation:

 

 

The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take 
place during this wait state. The WFI status can be released by an internal interrupt, including a 
fast interrupt. 

Flags: 

No flags are affected. 

Format: 

 

    Bytes 

Cycles

Opcode 

(Hex) 

  opc 

    1 

4n 

3F 

 

( n    =    1, 2, 3, … )

 

 

Example: 

The following sample program structure shows the sequence of operations that follow a "WFI" 
statement: 

EI
WFI

(Next instruction)

Main program

.

.

.

.

.

.

Interrupt occurs

Interrupt service routine

.

.

.

Clear interrupt flag

IRET

Service routine completed

(Enable global interrupt)
(Wait for interrupt)

 

Summary of Contents for C8274X

Page 1: ...S3C8275X F8275X C8278X F8278X C8274X F8274X 8 BIT CMOS MICROCONTROLLERS USER S MANUAL Revision 1 4 ...

Page 2: ...ife or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages e...

Page 3: ...hed in the S3C8275X F8275X C8278X F8278X C8274X F8274X User s Manual Revision 1 have been changed These changes for S3C8275X F8275X C8278X F8278X C8274X F8274X microcontroller which are described in detail in the Revision Descriptions section below are related to the followings Chapter 16 Embedded flash memory interface Chapter 17 Electrical Data Chapter 7 Clock Circuit Chapter 2 Address Spaces DI...

Page 4: ... internal release only 1 April 2005 First edition Reviewed by Finechips 1 1 July 2005 Second edition Reviewed by Finechips 1 2 August 2005 Third edition Reviewed by Finechips 1 3 May 2006 Fourth edition Reviewed by Finechips 1 4 April 2007 Fifth edition Reviewed by Finechips ...

Page 5: ...ck is erased 4 Maximum number of writing erasing is 10 000 times for full flash S3F8275 and 100 times for half flash S3F8278X F8274X 5 The chip erasing is available in Tool Program Mode only 2 Condition of Operating Voltage Condition of operating voltage is modified fx 0 4 2MHz to fx 0 4 4 2MHz at 2 0V 3 6V and fx 0 8MHz to fx 0 4 8MHz at 2 5V 3 6V in the page 17 2 3 CHAPTHER 16 Embedded Flash Mem...

Page 6: ...gram Memory Address Space and Figure 5 3 ROM Vector Address Area 2 CHAPTHER 17 Electrical Data It is changed VDD 2 0 V to 3 6 V into VDD 2 2 V to 3 6 V in the Table 17 12 3 DEVICE NAME The device name is changed S3C8275 F8275 C8278 F8278 C8274 F8274 to S3C8275X F8275X C8278X F8278X C8274X F8274X The X means Commercial type ...

Page 7: ...ck reference source when writing programs Chapter 5 Interrupt Structure describes the S3C8275X F8275X C8278X F8278X C8274X F8274X interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part II Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3C8 series microco...

Page 8: ...2 3 Register Architecture 2 5 Register Page Pointer PP 2 8 Register Set 1 2 10 Register Set 2 2 10 Prime Register Space 2 11 Working Registers 2 12 Using the Register Points 2 13 Register Addressing 2 15 Common Working Register Area C0H CFH 2 17 4 Bit Working Register Addressing 2 18 8 Bit Working Register Addressing 2 20 System and User Stack 2 22 Chapter 3 Addressing Modes Overview 3 1 Register ...

Page 9: ...Control Registers 5 8 System Mode Register SYM 5 9 Interrupt Mask Register IMR 5 10 Interrupt Priority Register IPR 5 11 Interrupt Request Register IRQ 5 13 Interrupt Pending Function Types 5 14 Interrupt Source Polling Sequence 5 15 Interrupt Service Routines 5 15 Generating Interrupt Vector Addresses 5 16 Nesting of Vectored Interrupts 5 16 Instruction Pointer IP 5 16 Fast Interrupt Processing 5...

Page 10: ...ock Output Control Register CLOCON 7 5 Oscillator Control Register OSCCON 7 6 Switching the CPU Clock 7 7 Chapter 8 RESET and Power Down System Reset 8 1 Overview 8 1 Normal Mode Reset Operation 8 1 Hardware Reset Values 8 2 Power Down Modes 8 5 Stop Mode 8 5 Idle Mode 8 6 Chapter 9 I O Ports Overview 9 1 Port Data Registers 9 2 port 0 9 3 port 1 9 7 port 2 9 11 port 3 9 13 Port 4 9 15 Port 5 9 17...

Page 11: ... Watch Timer Circuit Diagram 12 3 Chapter 13 LCD Controller Driver Overview 13 1 LCD Circuit Diagram 13 2 LCD RAM Address Area 13 3 LCD Control Register LCON 13 4 LCD Voltage Dividing Resistor 13 5 Common COM Signals 13 6 Segment SEG Signals 13 6 Chapter 14 Serial I O Interface Overview 14 1 Programming Procedure 14 1 SIO Control Registers SIOCON 14 2 SIO Pre Scaler Register SIOPS 14 3 SIO Block D...

Page 12: ...r 16 5 Sector Erase 16 7 Programming 16 9 Reading 16 11 Hard Lock Protection 16 12 Chapter 17 Electrical Data Overview 17 1 Chapter 18 Mechanical Data Overview 18 1 Chapter 19 S3F8275X F8278X F8274X Flash MCU Overview 19 1 Operating Mode Characteristics 19 5 Chapter 20 Development Tools Overview 20 1 SHINE 20 1 SAMA Assembler 20 1 SASM88 20 1 HEX2ROM 20 1 Target Boards 20 1 TB8275 8 4 Target Board...

Page 13: ...lock 2 13 2 9 Non Contiguous 16 Byte Working Register Block 2 14 2 10 16 Bit Register Pair 2 15 2 11 Register File Addressing 2 16 2 12 Common Working Register Area 2 17 2 13 4 Bit Working Register Addressing 2 19 2 14 4 Bit Working Register Addressing Example 2 19 2 15 8 Bit Working Register Addressing 2 20 2 16 8 Bit Working Register Addressing Example 2 21 2 17 Stack Operations 2 22 3 1 Registe...

Page 14: ...0 Oscillator Control Register OSCCON 7 6 7 11 STOP Control Register STPCON 7 8 9 1 S3C8275X C8278X C8274X I O Port Data Register Format 9 2 9 2 Port 0 High Byte Control Register P0CONH 9 4 9 3 Port 0 Low Byte Control Register P0CONL 9 4 9 4 Port 0 Pull up Control Register P0PUR 9 5 9 5 External Interrupt Control Register Low Byte EXTICONL 9 5 9 6 External Interrupt Pending Register EXTIPND 9 6 9 7...

Page 15: ...ganization 13 3 13 4 LCD Control Register LCON 13 4 13 5 Internal Voltage Dividing Resistor Connection 13 5 13 6 Select No Select Signals in Static Display Mode 13 6 13 7 Select No Select Signal in 1 2 Duty 1 2 Bias Display Mode 13 7 13 8 Select No Select Signal in 1 3 Duty 1 3 Bias Display Mode 13 7 13 9 LCD Signals and Wave Forms Example in 1 4 Duty 1 3 Bias Display Mode 13 8 14 1 Serial I O Mod...

Page 16: ...e Reset Timing 17 9 17 7 Clock Timing Measurement at XIN 17 11 17 8 Clock Timing Measurement at XTIN 17 12 17 9 Operating Voltage Range 17 13 18 1 64 Pin QFP Package Dimensions 64 QFP 1420F 18 1 18 2 64 Pin LQFP Package Dimensions 64 LQFP 1010 18 2 19 1 S3F8275X F8278X F8274X Pin Assignments 64 QFP 1420F 19 2 19 2 S3F8275X F8278X F8274X Pin Assignments 64 LQFP 1010 19 3 19 3 Operating Voltage Rang...

Page 17: ...egisters 5 8 6 1 Instruction Group Summary 6 2 6 2 Flag Notation Conventions 6 8 6 3 Instruction Set Symbols 6 8 6 4 Instruction Notation Conventions 6 9 6 5 Opcode Quick Reference 6 10 6 6 Condition Codes 6 12 8 1 S3C8275X C8278X C8274X Set 1 Register and Values After RESET 8 2 8 2 S3C8275X C8278X C8274X Set 1 Bank 0 Register Values After RESET 8 3 8 3 S3C8275X C8278X C8274X Set 1 Bank 1 Register...

Page 18: ...ristics 17 10 17 10 Main Oscillation Stabilization Time 17 11 17 11 Sub Oscillation Stabilization Time 17 12 17 12 A C Electrical Characteristics for Internal Flash ROM 17 13 19 1 Descriptions of Pins Used to Read Write the Flash ROM 19 4 19 2 Comparison of S3F8275X F8278X F8274X and S3C8275X C8278X C8274X Features 19 4 19 3 Operating Mode Selection Criteria 19 5 19 4 D C Electrical Characteristic...

Page 19: ...ointers 2 13 Using the RPs to Calculate the Sum of a Series of Registers 2 14 Addressing the Common Working Register Area 2 18 Standard Stack Operations Using PUSH and POP 2 23 Chapter 5 Interrupt Structure How to clear an interrupt pending bit 5 15 Chapter 7 Clock Circuit Switching the CPU Clock 7 7 Chapter 16 Embedded Flash Memory Interface Sector Erase 16 8 Program 16 10 Reading 16 11 Hard Lock...

Page 20: ...CON Oscillator Control Register 4 21 P0CONH Port 0 Control Register High Byte 4 22 P0CONL Port 0 Control Register Low Byte 4 23 P0PUR Port 0 Pull Up Control Register 4 24 P1CONH Port 1 Control Register High Byte 4 25 P1CONL Port 1 Control Register Low Byte 4 26 P1PUR Port 1 Pull up Control Register 4 27 P2CONH Port 2 Control Register High Byte 4 28 P2CONL Port 2 Control Register Low Byte 4 29 P2PU...

Page 21: ... 24 BXOR Bit XOR 6 25 CALL Call Procedure 6 26 CCF Complement Carry Flag 6 27 CLR Clear 6 28 COM Complement 6 29 CP Compare 6 30 CPIJE Compare Increment and Jump on Equal 6 31 CPIJNE Compare Increment and Jump on Non Equal 6 32 DA Decimal Adjust 6 33 DEC Decrement 6 35 DECW Decrement Word 6 36 DI Disable Interrupts 6 37 DIV Divide Unsigned 6 38 DJNZ Decrement and Jump if Non Zero 6 39 EI Enable In...

Page 22: ...POPUD Pop User Stack Decrementing 6 64 POPUI Pop User Stack Incrementing 6 65 PUSH Push to Stack 6 66 PUSHUD Push User Stack Decrementing 6 67 PUSHUI Push User Stack Incrementing 6 68 RCF Reset Carry Flag 6 69 RET Return 6 70 RL Rotate Left 6 71 RLC Rotate Left through Carry 6 72 RR Rotate Right 6 73 RRC Rotate Right through Carry 6 74 SB0 Select Bank 0 6 75 SB1 Select Bank 1 6 76 SBC Subtract wit...

Page 23: ...latest CPU architecture The S3C8275X C8278X C8274X is a microcontroller with a 16 8 4K byte mask programmable ROM embedded The S3F8275X F8278X F8274X is a microcontroller with a 16 8 4K byte flash ROM embedded Using a proven modular design approach Samsung engineers have successfully developed the S3C8275X F8275X C8278X F8278X C8274X F8274X by integrating the following peripheral modules with the ...

Page 24: ...rs Programmable interval timer External event counter function Configurable as one 16 bit timer counters Watch Timer Interval time 3 91mS 0 25S 0 5S and 1S at 32 768 kHz 0 5 1 2 4 kHz Selectable buzzer output LCD Controller Driver 32 segments and 4 common terminals Static 1 2 duty 1 3 duty and 1 4 duty selectable Internal resistor circuit for LCD bias 8 bit Serial I O Interface 8 bit transmit rece...

Page 25: ...P5 7 P5 0 SEG8 SEG15 P4 7 P4 0 SEG16 SEG23 P3 7 P3 0 SEG24 SEG30 P2 7 P2 1 16 Bit Timer Counter 1 P0 0 INT0 P0 1 INT1 P0 2 INT2 P0 3 T1CLK P0 4 TAOUT P0 5 TBOUT P0 6 CLKOUT P0 7 BUZ I O Port 1 P1 0 SCK P1 1 SO P1 2 SI P1 3 INT3 P1 4 INT4 P1 5 INT5 P1 6 INT6 P1 7 INT7 I O Port 3 I O Port 4 P2 0 SEG31 VBLDREF P2 1 P2 7 SEG30 SEG24 P3 0 P3 7 SEG23 SEG16 P4 0 P4 7 SEG15 SEG8 Port I O and Interrupt Con...

Page 26: ...6 SEG10 P4 5 SEG11 P4 4 SEG12 P4 3 SEG13 P4 2 64 63 62 61 60 59 58 57 56 55 54 53 52 P0 2 INT2 P0 3 T1CLK P0 4 TAOUT P0 5 TBOUT P0 6 CLKOUT P0 7 BUZ P1 0 SCK P1 1 SO P1 2 SI P1 3 INT3 P1 4 INT4 P1 5 INT5 P1 6 INT6 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG14 P4 1 SEG15 P4 0 SEG16 P3 7 SEG17 P3 6 SEG18 P3 5 SEG19 P3 4 SEG20 P3 3 SEG21 P3 2 SE...

Page 27: ...25 P2 6 SEG26 P2 5 SEG27 P2 4 SEG28 P2 3 SEG29 P2 2 SEG30 P2 1 SEG31 P2 0 VBLDREF P1 7 INT7 SEG0 P5 7 COM0 P6 0 COM1 P6 1 COM2 P6 2 COM3 P6 3 VLC0 VLC1 VLC2 VDD VSS XOUT XIN TEST XTIN XTOUT nRESET V REG P0 0 INT0 P0 1 INT1 P0 2 INT2 P0 3 T1CLK P0 4 TAOUT P0 5 TBOUT P0 6 CLKOUT P0 7 BUZ P1 0 SCK P1 1 SO P1 2 SI P1 3 INT3 P1 4 INT4 P1 5 INT5 P1 6 INT6 SEG1 P5 6 SEG2 P5 5 SEG3 P5 4 SEG4 P5 3 SEG5 P5 ...

Page 28: ...P1 3 P1 7 I O I O port with bit programmable pins Schmitt trigger input or push pull open drain output and software assignable pull ups P1 3 P1 7 are alternately used for external interrupt input noise filters interrupt enable and pending control E 4 26 27 28 29 33 SCK SO SI INT3 INT7 P2 0 P2 1 P2 7 I O I O port with bit programmable pins Input or push pull open drain output and software assignabl...

Page 29: ...23 P0 5 CLKOUT I O System clock output E 4 24 P0 6 BUZ I O Output pin for buzzer signal E 4 25 P0 7 SCK SO SI I O Serial clock data output and data input E 4 26 27 28 P1 0 P1 1 P1 2 COM0 COM3 I O LCD common signal outputs H 9 2 5 P6 0 P6 3 SEG0 SEG15 SEG16 SEG30 SEG31 I O LCD segment signal outputs H 9 H 8 H 10 1 64 50 49 35 34 P5 7 P4 0 P3 7 P2 1 P2 0 VBLDREF VBLDREF I O Battery level detector re...

Page 30: ...TS P Channel N Channel In VDD Figure 1 4 Pin Circuit Type A In VDD Schmitt Trigger Pull Up Resistor Figure 1 5 Pin Circuit Type B nRESET VDD Output Disable Data Pull up Resistor VDD I O P CH N CH Open Drain Resistor Enable Schmitt Trigger Figure 1 6 Pin Circuit Type E 4 P0 P1 ...

Page 31: ...VIEW 1 9 Out COM SEG VLC0 VLC1 VLC2 Output Disable VSS Figure 1 7 Pin Circuit Type H 4 VDD Open Drain Data Output Disable 1 SEG Output Disable 2 Resistor Enable VDD Circuit Type H 4 P CH N CH Pull Up Resistor I O Figure 1 8 Pin Circuit Type H 8 P2 1 P2 7 P3 ...

Page 32: ...VIEW S3C8275X F8275X C8278X F8278X C8274X F8274X 1 10 VDD Data Output Disable 1 COM SEG Output Disable 2 Resistor Enable VDD Circuit Type H 4 P CH N CH Pull Up Resistor I O Figure 1 9 Pin Circuit Type H 9 P4 P5 P6 ...

Page 33: ...X C8274X F8274X PRODUCT OVERVIEW 1 11 VDD Data Output Disable 1 Resistor Enable VDD Circuit Type H 4 P CH N CH Pull Up Resistor I O Open Drain SEG Alternative Function BLDEN BLD Select To BLD Figure 1 10 Pin Circuit Type H 10 P2 0 ...

Page 34: ...mable ROM The S3C8274X has an internal 4 Kbyte mask programmable ROM The 256 byte physical register space is expanded into an addressable area of 320 bytes using addressing modes A 16 byte LCD display register file is implemented There are 605 mapped registers in the internal register file Of these 528 are for general purpose This number includes a 16 byte working register common area used as a sc...

Page 35: ...ns The ROM address at which a program execution starts after a reset is 0100H The reset address of ROM can be changed by a smart option only in the S3F8275X Full Flash Device Refer to the chapter 16 Embedded Flash Memory Interface for more detail contents Decimal 16 383 255 HEX 3FFFH 3FH 00H 0 16K bytes Internal Program Memory Area Smart Option Area Interrupt Vector Area Available ISP Sector Area ...

Page 36: ...the Smart Option area 003CH 003FH by OTP MTP tools SPW2 plus single programmer or GW PRO2 gang programmer ISP reset vector address selection bit 00 200H ISP area size 256 byte 01 300H ISP area size 512 byte 10 500H ISP area size 1024 byte 11 900H ISP area size 2048 byte ISP protection size selection note 00 256 bytes 01 512 bytes 10 1024 bytes 11 2048 bytes Not used ISP protection enable disable b...

Page 37: ...om 003CH to 003FH The ISP of smart option 003EH is available in the S3F8275X only The default value of ROM address 003EH is FFH And ROM address 003EH should be kept FFH when used the S3C8275X C8278X F8278X C8274X F8274X The LVR of smart option 003FH is available in all the device S3C8275X F8275X C8278X F8278X C8274X F8274X The default value of ROM address 003FH is FFH ...

Page 38: ...r can only be addressed using register addressing modes The extension of register space into separately addressable areas sets banks and pages is supported by various addressing mode restrictions the select bank instructions SB0 and SB1 and the register page pointer PP Specific register types and the area in bytes that they occupy in the register file are summarized in Table 2 1 Table 2 1 S3C8275X...

Page 39: ...ontrol Registers Register Addressing Mode Set1 FFH E0H 32 Bytes E0H DFH D0H CFH C0H Prime Data Registers All addressing modes LCD Display Reigster Page 2 0FH 00H 16 Bytes Page 1 Page 1 Page 0 Prime Data Registers All Addressing Modes Page 0 Set 2 General Purpose Data Registers Indirect Register Indexed Mode and Stack Operations C0H BFH 00H FFH FFH 192 Bytes 64 Bytes 256 Bytes Figure 2 3 Internal R...

Page 40: ...FFH E0H 32 Bytes E0H DFH D0H CFH C0H Prime Data Registers All addressing modes LCD Display Reigster Page 2 0FH 00H 16 Bytes Page 0 Prime Data Registers All Addressing Modes Page 0 Set 2 General Purpose Data Registers Indirect Register Indexed Mode and Stack Operations C0H BFH 00H FFH 192 Bytes 64 Bytes 256 Bytes NOTE In case of S3C8278X C8274X there are page 0 and page 2 Page 2 is for LCD display ...

Page 41: ...er page selection bits NOTES 1 In the S3C8275X microcontroller the internal register file is configured as three pages Pages 0 2 The pages 0 1 are used for general purpose register file and page 2 is used for LCD data register or general purpose register 2 In the S3C8278X C8274X microcontroller the internal register file is configured as two pages Pages 0 2 The page 0 is used for general purpose r...

Page 42: ...0H Destination 0 Source 0 SRP 0C0H LD R0 0FFH Page 0 RAM clear starts RAMCL0 CLR R0 DJNZ R0 RAMCL0 CLR R0 R0 00H LD PP 10H Destination 1 Source 0 LD R0 0FFH Page 1 RAM clear starts RAMCL1 CLR R0 DJNZ R0 RAMCL1 CLR R0 R0 00H NOTE You should refer to page 6 39 and use DJNZ instruction properly when DJNZ instruction is used in your program ...

Page 43: ... file Registers in set 1 locations are directly accessible at all times using Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 locations C0H FFH is logically duplicate...

Page 44: ...ddressable following a reset In order to address prime registers on pages 0 1 or 2 you must set the register page pointer PP to the appropriate source and destination values FFH FCH E0H D0H C0H Set 1 Bank 0 Peripheral and I O General purpose CPU and system control LCD data register FFH Page 1 Set 2 FFH C0H 00H BFH Page 0 Set 2 Page 0 Prime Space LCD Data Register Area Page 2 00H 0FH Bank 1 NOTE In...

Page 45: ...ize and relative locations of selected working register spaces One working register slice is 8 bytes eight 8 bit working registers R0 R7 or R8 R15 One working register block is 16 bytes sixteen 8 bit working registers R0 R15 All the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer ...

Page 46: ...sing modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RP0 point to the lower slice and RP1 point to the upper slice see Figure 2 8 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 9 RP0 points to the upper s...

Page 47: ... ADD R0 R1 R0 R0 R1 ADC R0 R2 R0 R0 R2 C ADC R0 R3 R0 R0 R3 C ADC R0 R4 R0 R0 R4 C ADC R0 R5 R0 R0 R5 C The sum of these six registers 6FH is located in the register R0 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence w...

Page 48: ...ister file and an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register and the le...

Page 49: ... C8278X C8274X microcontroller pages 0 2 are implemented Pages 0 2 contain all of the addressable registers in the internal register file Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RP0 points to locations C0H C7H and RP1 to locations C8H CFH that is to the common working register area FFH C0H Set 2 Prime Regis...

Page 50: ...by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages FFH Page 1 Set 2 FFH C0H 00H BFH Page 0 Set 2 Page 0 Prime Space LCD Data Registers Page 2 00H 0FH FFH FCH E0H D0H C0H Set 1 Following a hardware reset register pointers RP0 and RP1 point to the common working register are...

Page 51: ...register area the address bits are concatenated in the following way to form a complete 8 bit address The high order bit of the 4 bit address selects one of the register pointers 0 selects RP0 1 selects RP1 The five high order bits in the register pointer select an 8 byte slice of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As sho...

Page 52: ...ive high order bits Address OPCODE Selects RP0 or RP1 RP1 RP0 4 bit address provides three low order bits Figure 2 13 4 Bit Working Register Addressing Register address 76H RP0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 R6 0 1 1 0 1 1 1 0 Selects RP0 Instruction INC R6 OPCODE RP1 0 1 1 1 1 0 0 0 Figure 2 14 4 Bit Working Register Addressing Example ...

Page 53: ...ts of the complete address are provided by the original instruction Figure 2 16 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 4 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register addres...

Page 54: ...SPACES 2 21 8 bit address form instruction LD R11 R2 RP0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 Selects RP1 R11 Register address 0ABH RP1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 Specifies working register addressing Figure 2 16 8 Bit Working Register Addressing Example ...

Page 55: ...ed Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL SPH Register locations D8H and D9H contain the 16 bit stack pointer SP that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H an...

Page 56: ...s in the internal register file using PUSH and POP instructions LD SPL 0FFH SPL FFH Normally the SPL is set to 0FFH by the initialization routine PUSH PP Stack address 0FEH PP PUSH RP0 Stack address 0FDH RP0 PUSH RP1 Stack address 0FCH RP1 PUSH R3 Stack address 0FBH R3 POP R3 R3 Stack address 0FBH POP RP1 RP1 Stack address 0FCH POP RP0 RP0 Stack address 0FDH POP PP PP Stack address 0FEH ...

Page 57: ... used to determine the location of the data operand The operands specified in SAM88RC instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are Registe...

Page 58: ...ion Execution OPCODE OPERAND 8 bit Register File Address Point to One Register in Register File One Operand Instruction Example Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Program Memory Register File Figure 3 1 Register Addressing dst OPCODE 4 bit Working Register Point to the Working Register 1 of 8 Two Operand Instruction Example Sample Instruction ADD R1 R2...

Page 59: ...y 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations C0H FFH in set 1 using the Indirect Register addressing mode dst Address of Operand used by Instruction OPCODE ADDRESS 8 bit Register File Address Point to One Register in Register File One Operand Instructio...

Page 60: ...d dst OPCODE PAIR Points to Register Pair Example Instruction References Program Memory Sample Instructions CALL RR2 JP RR2 Program Memory Register File Value used in Instruction OPERAND REGISTER Program Memory 16 Bit Address Points to Program Memory Figure 3 4 Indirect Register Addressing to Program Memory ...

Page 61: ...SS 4 bit Working Register Address Point to the Working Register 1 of 8 Sample Instruction OR R3 R6 Program Memory Register File src 3 LSBs Value used in Instruction OPERAND Selected RP points to start fo working register block RP0 or RP1 MSB Points to RP0 or RP1 Figure 3 5 Indirect Working Register Addressing to Register File ...

Page 62: ...emory access Program Memory Register File src Value used in Instruction OPERAND Example Instruction References either Program Memory or Data Memory Program Memory or Data Memory Next 2 bit Point to Working Register Pair 1 of 4 LSB Selects Register Pair 16 Bit address points to program memory or data memory RP0 or RP1 MSB Points to RP0 or RP1 Selected RP points to start of working register block Fi...

Page 63: ... instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports Indexed addressing mode for the internal register file is the Load instruct...

Page 64: ...ected RP points to start of working register block dst src OPCODE Program Memory x OFFSET 4 bit Working Register Address Sample Instructions LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed NEXT 2 Bits Register Pair Value used in Instruction 8 Bits 16 Bits 16 Bits F...

Page 65: ...ted RP points to start of working register block Sample Instructions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed NEXT 2 Bits Register Pair Value used in Instruction 8 Bits 16 Bits 16 Bits dst src OPCODE Program Memory src OFFSET 4 bit Working Register Add...

Page 66: ...irect Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H Identical operation to LDC example except that external program memory is accessed dst src OPCODE Program Memory 0 or 1 Lower Address ...

Page 67: ...ontinued OPCODE Program Memory Lower Address Byte Memory Address Used Upper Address Byte Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Next OPCODE Figure 3 11 Direct Addressing for Call and Jump Instructions ...

Page 68: ...Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Current Instruction Program Memory Locations 0 255 Program Memory OPCODE dst Lower Address Byte Upper Address Byte Next Instruction LSB Must b...

Page 69: ...his addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR OPCODE Program Memory Displacement Program Memory Address Used Sample Instructions JR ULT OFFSET Where OFF...

Page 70: ...uction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers The Operand value is in the instruction OPCODE Sample Instruction LD R0 0AAH Program Memory OPERAND Figure 3 14 Immediate Addressing ...

Page 71: ...y a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this manual The locations and read write characteristics of all mapped registers in the S3C8275X C8278X C8274X register file are listed in Table 4 1 The hardware reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 Set 1 Registers Register Name Mnemonic Address R...

Page 72: ... register low byte P2CONL 235 EBH R W Port 2 pull up resistor enable register P2PUR 236 ECH R W Port 3 control register high byte P3CONH 237 EDH R W Port 3 control register low byte P3CONL 238 EEH R W Port 3 Pull up resistor enable register P3PUR 239 EFH R W Port 0 data register P0 240 F0H R W Port 1 data register P1 241 F1H R W Port 2 data register P2 242 F2H R W Port 3 data register P3 243 F3H R...

Page 73: ...gh byte P4CONH 233 E9H R W Port 4 control register low byte P4CONL 234 EAH R W Port 5 control register high byte P5CONH 235 EBH R W Port 5 control register low byte P5CONL 236 ECH R W Port 6 control register P6CON 237 EDH R W Locations EEH EFH are not mapped Flash memory control register FMCON 240 F0H R W Flash memory user programming enable register FMUSR 241 F1H R W Flash memory sector address r...

Page 74: ... Name of individual bit or related bits Full Register name Register ID Sign Flag S 0 Operation does not generate a carry or borrow condition 1 Operation generates carry out or borrow into high order bit 7 0 Operation result is a non zero value 1 Operation result is zero 0 Operation generates positive number MSB 0 1 Operation generates negative number MSB 1 Description of the effect of specific bit...

Page 75: ...dressing Mode Register addressing mode only 7 6 Not used for the S3C8275X C8278X C8274X 5 VIN Source Bit 0 Internal source 1 External source 4 Battery Level Detector Output Bit 0 VIN VREF when BLD is enabled 1 VIN VREF when BLD is enabled 3 Battery Level Detector Enable Disable Bit 0 Disable BLD 1 Enable BLD 2 0 Detection Voltage Selection Bits 0 0 0 VBLD 2 2V 1 0 1 VBLD 2 4V 0 1 1 VBLD 2 8V Other...

Page 76: ...6 3 0 1 fxx 1024 1 0 fxx 128 1 1 fxx 16 1 Basic Timer Counter Clear Bit 1 0 No effect 1 Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer and Timer Counters 2 0 No effect 1 Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to 00H Immediately following the write operation the BTCON 1 value is auto...

Page 77: ...nable IRQ for main wake up in power down mode 1 Disable IRQ for main wake up in power down mode 6 5 Not used for the S3C8275X C8278X C8274X must keep always 0 4 3 CPU Clock System Clock Selection Bits note 0 0 fxx 16 0 1 fxx 8 1 0 fxx 2 1 1 fxx 2 0 Not used for the S3C8275X C8278X C8274X must keep always 0 NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select...

Page 78: ... E8H Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 1 0 Reset Value 0 0 Read Write R W R W Addressing Mode Register addressing mode only 7 2 Not used for the S3C8275X C8278X C8274X must keep always 0 1 0 Clock Output Frequency Selection Bits 0 0 Select fxx 64 0 1 Select fxx 16 1 0 Select fxx 8 1 1 Select fxx 4 ...

Page 79: ...e interrupt by both falling and rising edge 5 4 P1 6 External Interrupt INT6 Configuration Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge 1 0 Enable interrupt by rising edge 1 1 Enable interrupt by both falling and rising edge 3 2 P1 5 External Interrupt INT5 Configuration Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge 1 0 Enable interrupt by rising edge 1 1 Enabl...

Page 80: ...e interrupt by both falling and rising edge 5 4 P0 2 External Interrupt INT2 Configuration Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge 1 0 Enable interrupt by rising edge 1 1 Enable interrupt by both falling and rising edge 3 2 P0 1 External Interrupt INT1 Configuration Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge 1 0 Enable interrupt by rising edge 1 1 Enabl...

Page 81: ...pt request is not pending pending bit clear when write 0 1 Interrupt request is pending when read 4 P1 4 INT4 Interrupt Pending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending when read 3 P1 3 INT3 Interrupt Pending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending when read 2 P0 2 INT2 Interrup...

Page 82: ... zero 5 Sign Flag S 0 Operation generates a positive number MSB 0 1 Operation generates a negative number MSB 1 4 Overflow Flag V 0 Operation result is 127 or 128 1 Operation result is 127 or 128 3 Decimal Adjust Flag D 0 Add operation completed 1 Subtraction operation completed 2 Half Carry Flag H 0 No carry out of bit 3 or no borrow into bit 3 by addition or subtraction 1 Addition generated carr...

Page 83: ...ister addressing mode only 7 4 Flash Memory Mode Selection Bits 0 1 0 1 Programming mode 1 0 1 0 Sector erase mode 0 1 1 0 Hard lock mode Other values Not available 3 Sector Erase Status Bit 0 Success sector erase 1 Fail sector erase 2 1 Not used for the S3F8275X F8278X F8274X 0 Flash Operation Start Bit 0 Operation stop 1 Operation start This bit will be cleared automatically just after the corre...

Page 84: ...of flash ROM NOTE The high byte flash memory sector address pointer value is the higher eight bits of the 16 bit pointer address FMSECL Flash Memory Sector Address Register Low Byte F3H Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Flash Memory Sector Address Bit Low Byte The 7th bi...

Page 85: ...e Register F1H Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory User Programming Enable Bits 1 0 1 0 0 1 0 1 Enable user programming mode Other values Disable user programming mode ...

Page 86: ...nterrupt Level 5 IRQ5 Enable Bit External Interrupt P0 2 0 Disable mask 1 Enable unmask 4 Interrupt Level 4 IRQ4 Enable Bit External Interrupt P0 1 0 Disable mask 1 Enable unmask 3 Interrupt Level 3 IRQ3 Enable Bit External Interrupt P0 0 0 Disable mask 1 Enable unmask 2 Interrupt Level 2 IRQ2 Enable Bit Watch Timer Overflow 0 Disable mask 1 Enable unmask 1 Interrupt Level 1 IRQ1 Enable Bit SIO In...

Page 87: ...upper eight bits of the 16 bit instruction pointer address IP15 IP8 The lower byte of the IP address is located in the IPL register DBH IPL Instruction Pointer Low Byte DBH Set 1 Bit Identifier 7 6 5 4 3 2 1 0 Reset Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer...

Page 88: ...fined 0 0 1 B C A 0 1 0 A B C 0 1 1 B A C 1 0 0 C A B 1 0 1 C B A 1 1 0 A C B 1 1 1 Group priority undefined 6 Interrupt Subgroup C Priority Control Bit 0 IRQ6 IRQ7 1 IRQ7 IRQ6 5 Interrupt Group C Priority Control Bit 0 IRQ5 IRQ6 IRQ7 1 IRQ6 IRQ7 IRQ5 3 Interrupt Subgroup B Priority Control Bit 0 IRQ3 IRQ4 1 IRQ4 IRQ3 2 Interrupt Group B Priority Control Bit 0 IRQ2 IRQ3 IRQ4 1 IRQ3 IRQ4 IRQ2 0 Int...

Page 89: ...Pending Bit External Interrupt P1 3 0 Not pending 1 Pending 5 Level 5 IRQ5 Request Pending Bit External Interrupt P0 2 0 Not pending 1 Pending 4 Level 4 IRQ4 Request Pending Bit External Interrupt P0 1 0 Not pending 1 Pending 3 Level 3 IRQ3 Request Pending Bit External Interrupt P0 0 0 Not pending 1 Pending 2 Level 2 IRQ2 Request Pending Bit Watch Timer Overflow 0 Not pending 1 Pending 1 Level 1 I...

Page 90: ...resistors 1 Disable internal LCD dividing resistors 6 5 LCD Clock Selection Bits 0 0 fw 29 64 Hz 0 1 fw 28 128 Hz 1 0 fw 27 256 Hz 1 1 fw 26 512 Hz 4 2 LCD Duty and Bias Selection Bits 0 0 0 1 4duty 1 3bias 0 0 1 1 3duty 1 3bias 0 1 0 1 3duty 1 2bias 0 1 1 1 2duty 1 2bias 1 x x Static NOTES 1 x means don t care 2 When 1 2 bias is selected the bias levels are set as VLC0 VLC1 VLC2 and VSS 1 Not use...

Page 91: ...lly cleared to 0 when the sub oscillator is stopped by OSCCON 2 NOTES 1 The OSCCON 7 must be maintained to 1 during the sub oscillator operation 2 A capacitor 0 1uF should be connected between VREG and GND 6 4 Not used for the S3C8275X C8278X C8274X 3 Main Oscillator Control Bit 0 Main oscillator RUN 1 Main oscillator STOP 2 Sub Oscillator Control Bit 0 Sub oscillator RUN 1 Sub oscillator STOP 1 N...

Page 92: ...en drain output mode 1 0 Push pull output mode 1 1 Alternative function BUZ 5 4 P0 6 CLKOUT Configuration Bits 0 0 Schmitt trigger input mode 0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Alternative function CLKOUT 3 2 P0 5 TBOUT Configuration Bits 0 0 Schmitt trigger input mode 0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Alternative function TBOUT 1 0 ...

Page 93: ... 0 Push pull output mode 1 1 Not used for the S3C8275X C8278X C8274X 5 4 P0 2 INT2 Configuration Bits 0 0 Schmitt trigger input mode 0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Not used for the S3C8275X C8278X C8274X 3 2 P0 1 INT1 Configuration Bits 0 0 Schmitt trigger input mode 0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Not used for the S3C8275X C82...

Page 94: ...esistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 4 P0 4 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 3 P0 3 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 2 P0 2 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 1 P0 1 s Pull up Resistor Enable Bit 0 Disable pull up res...

Page 95: ...Push pull output mode 1 1 Not used for the S3C8275X C8278X C8274X 5 4 P1 6 INT6 Configuration Bits 0 0 Schmitt trigger input mode 0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Not used for the S3C8275X C8278X C8274X 3 2 P1 5 INT5 Configuration Bits 0 0 Schmitt trigger input mode 0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Not used for the S3C8275X C8278X...

Page 96: ...utput mode 1 0 Push pull output mode 1 1 Not used for the S3C8275X C8278X C8274X 5 4 P1 2 SI Configuration Bits 0 0 Schmitt trigger input mode SI 0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Not used for the S3C8275X C8278X C8274X 3 2 P1 1 SO Configuration Bits 0 0 Schmitt trigger input mode 0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Alternative functi...

Page 97: ...esistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 4 P1 4 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 3 P1 3 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 2 P1 2 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 1 P1 1 s Pull up Resistor Enable Bit 0 Disable pull up res...

Page 98: ... 0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Alternative function SEG24 5 4 P2 6 SEG25 Configuration Bits 0 0 Input mode 0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Alternative function SEG25 3 2 P2 5 SEG26 Configuration Bits 0 0 Input mode 0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Alternative function SEG26 1 0 P2 4 SEG27 Conf...

Page 99: ...nel open drain output mode 1 0 Push pull output mode 1 1 Alternative function SEG28 5 4 P2 2 SEG29 Configuration Bits 0 0 Input mode 0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Alternative function SEG29 3 2 P2 1 SEG30 Configuration Bits 0 0 Input mode 0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Alternative function SEG30 1 0 P2 0 SEG31 VBLDREF Configu...

Page 100: ...esistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 4 P2 4 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 3 P2 3 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 2 P2 2 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 1 P2 1 s Pull up Resistor Enable Bit 0 Disable pull up res...

Page 101: ...0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Alternative function SEG16 5 4 P3 6 SEG17 Configuration Bits 0 0 Input mode 0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Alternative function SEG17 3 2 P3 5 SEG18 Configuration Bits 0 0 Input mode 0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Alternative function SEG18 1 0 P3 4 SEG19 Confi...

Page 102: ...0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Alternative function SEG20 5 4 P3 2 SEG21 Configuration Bits 0 0 Input mode 0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Alternative function SEG21 3 2 P3 1 SEG22 Configuration Bits 0 0 Input mode 0 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Alternative function SEG22 1 0 P3 0 SEG23 Confi...

Page 103: ...esistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 4 P3 4 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 3 P3 3 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 2 P3 2 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 1 P3 1 s Pull up Resistor Enable Bit 0 Disable pull up res...

Page 104: ...e 0 1 Input mode with pull up resistor 1 0 Push pull output mode 1 1 Alternative function SEG8 5 4 P4 6 SEG9 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up resistor 1 0 Push pull output mode 1 1 Alternative function SEG9 3 2 P4 5 SEG10 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up resistor 1 0 Push pull output mode 1 1 Alternative function SEG10 1 0 P4 4 SEG11 Config...

Page 105: ...0 1 Input mode with pull up resistor 1 0 Push pull output mode 1 1 Alternative function SEG12 5 4 P4 2 SEG13 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up resistor 1 0 Push pull output mode 1 1 Alternative function SEG13 3 2 P4 1 SEG14 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up resistor 1 0 Push pull output mode 1 1 Alternative function SEG14 1 0 P4 0 SEG15 Confi...

Page 106: ...ode 0 1 Input mode with pull up resistor 1 0 Push pull output mode 1 1 Alternative function SEG0 5 4 P5 6 SEG1 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up resistor 1 0 Push pull output mode 1 1 Alternative function SEG1 3 2 P5 5 SEG2 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up resistor 1 0 Push pull output mode 1 1 Alternative function SEG2 1 0 P5 4 SEG3 Configu...

Page 107: ...de 0 1 Input mode with pull up resistor 1 0 Push pull output mode 1 1 Alternative function SEG4 5 4 P5 2 SEG5 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up resistor 1 0 Push pull output mode 1 1 Alternative function SEG5 3 2 P5 1 SEG6 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up resistor 1 0 Push pull output mode 1 1 Alternative function SEG6 1 0 P5 0 SEG7 Configur...

Page 108: ...1 Input mode with pull up resistor 1 0 Push pull output mode 1 1 Alternative function COM3 5 4 P6 2 COM2 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up resistor 1 0 Push pull output mode 1 1 Alternative function COM2 3 2 P6 1 COM1 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up resistor 1 0 Push pull output mode 1 1 Alternative function COM1 1 0 P6 0 COM0 Configuration...

Page 109: ...274X 3 0 Source Register Page Selection Bits 0 0 0 0 Source page 0 0 0 0 1 Source page 1 Not used for the S3C8278X C8274X 0 0 1 0 Source page 2 Others Not used for the S3C8275X C8278X C8274X NOTES 1 In the S3C8275X microcontroller the internal register file is configured as three pages Pages 0 2 The pages 0 1 are used for general purpose register file and page 2 is used for LCD data register or ge...

Page 110: ...oints to address C0H in register set 1 selecting the 8 byte working register slice C0H C7H 2 0 Not used for the S3C8275X C8278X C8274X RP1 Register Pointer 1 D7H Set 1 Bit Identifier 7 6 5 4 3 2 1 0 Reset Value 1 1 0 0 1 Read Write R W R W R W R W R W Addressing Mode Register addressing only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256 byte work...

Page 111: ...B first mode 5 SIO Mode Selection Bit 0 Receive only mode 1 Transmit receive mode 4 Shift Clock Edge Selection Bit 0 Tx at falling edges Rx at rising edges 1 Tx at rising edges Rx at falling edges 3 SIO Counter Clear and Shift Start Bit 0 No action 1 Clear 3 bit counter and start shifting 2 SIO Shift Operation Enable Bit 0 Disable shifter and clock counter 1 Enable shifter and clock counter 1 SIO ...

Page 112: ...er address SP15 SP8 The lower byte of the stack pointer value is located in register SPL D9H The SP value is undefined following a reset SPL Stack Pointer Low Byte D9H Set 1 Bit Identifier 7 6 5 4 3 2 1 0 Reset Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address Low Byte The low byte stack pointer value is the low...

Page 113: ... 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 STOP Control Bits 1 0 1 0 0 1 0 1 Enable stop instruction Other values Disable stop instruction NOTE Before execute the STOP instruction set this STPCON register as 10100101b Otherwise the STOP instruction will not execute as well as reset will be generated ...

Page 114: ...IRQ2 0 1 1 IRQ3 1 0 0 IRQ4 1 0 1 IRQ5 1 1 0 IRQ6 1 1 1 IRQ7 1 Fast Interrupt Enable Bit 2 0 Disable fast interrupt processing 1 Enable fast interrupt processing 0 Global Interrupt Enable Bit 3 0 Disable all interrupt processing 1 Enable all interrupt processing NOTES 1 You can select only one interrupt level at a time for fast interrupt processing 2 Setting SYM 1 to 1 enables fast interrupt proces...

Page 115: ...n Bits 0 0 0 fxx 512 0 0 1 fxx 256 0 1 0 fxx 64 0 1 1 fxx 8 1 0 0 fxx system clock 1 0 1 fxt sub clock 1 1 0 T1CLK external clock 1 1 1 Not available 3 Timer 1 A Counter Clear Bit 0 No effect 1 Clear the timer 1 A counter when write automatically cleared to 0 after being cleared basic timer counter 2 Timer 1 A Counter Operating Enable Bit 0 Disable counting operation 1 Enable counting operation 1 ...

Page 116: ... 0 0 0 fxx 512 0 0 1 fxx 256 0 1 0 fxx 64 0 1 1 fxx 8 1 0 0 fxt sub clock Others Not available 3 Timer B Counter Clear Bit 0 No effect 1 Clear the timer B counter when write automatically cleared to 0 after being cleared basic timer counter 2 Timer B Counter Operating Enable Bit 0 Disable counting operation 1 Enable counting operation 1 Timer B Interrupt Enable Bit 0 Disable interrupt 1 Enable int...

Page 117: ...sable watch timer interrupt 1 Enable watch timer interrupt 5 4 Buzzer Signal Selection Bits 0 0 0 5 kHz 0 1 1 kHz 1 0 2 kHz 1 1 4 kHz 3 2 Watch Timer Speed Selection Bits 0 0 Set watch timer interrupt to 1s 0 1 Set watch timer interrupt to 0 5s 1 0 Set watch timer interrupt to 0 25s 1 1 Set watch timer interrupt to 3 91ms 1 Watch Timer Enable Bit 0 Disable watch timer Clear frequency dividing circ...

Page 118: ...y of the levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or m...

Page 119: ...e number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V1 one source S1 Type 2 One level IRQn one vector V1 multiple sources S1 Sn Type 3 One level IRQn multiple vectors V1 Vn multiple sources S1 Sn Sn 1 Sn m In the S3C8275X C8278X C8274X microcontroller two interrupt types are implemented Vectors Sources Levels S1 V1 S2 Type 2 IRQn S3 Sn V...

Page 120: ...unter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed Vectors Sources Levels Reset Clear NOTES 1 Within a given interrupt level the low vector address has high priority For example F0H has higher priority than F2H...

Page 121: ... memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H The reset address of ROM can be changed by a smart option only in the S3F8275X Full Flash Device Refer to the chapter 16 Embedded Flash Memory Interface for more detail contents 16 383 0 Decimal 255 00H 100H FFH 3FFFH HEX Inte...

Page 122: ...t IRQ3 226 E2H P0 1 external interrupt IRQ4 228 E4H P0 2 external interrupt IRQ5 230 E6H P1 3 external interrupt IRQ6 238 EEH P1 7 external interrupt IRQ7 3 236 ECH P1 6 external interrupt 2 234 EAH P1 5 external interrupt 1 232 E8H P1 4 external interrupt 0 NOTES 1 Interrupt priorities are identified in inverse order 0 is the highest priority 1 is the next highest and so on 2 If two or more inter...

Page 123: ... The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source The system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register ID R W Function Description...

Page 124: ...el enable disable settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be sure to include the necessary register file address register pointer information Interrupt Request Register Read only IRQ0 IRQ7 Interrupts Inter...

Page 125: ...E1H bank 0 E2H bank 0 E3H bank 0 Watch timer overflow IRQ2 WTCON E1H bank 1 P0 0 external interrupt IRQ3 P0CONL EXTICONL EXTIPND E5H bank 0 F9H bank 0 F7H bank 0 P0 1 external interrupt IRQ4 P0CONL EXTICONL EXTIPND E5H bank 0 F9H bank 0 F7H bank 0 P0 2 external interrupt IRQ5 P0CONL EXTICONL EXTIPND E5H bank 0 F9H bank 0 F7H bank 0 P1 3 external interrupt IRQ6 P1CONL EXTICONL EXTIPND E8H bank 0 F9...

Page 126: ...pts during the normal operation it is recommended to use the EI and DI instructions for this purpose System Mode Register SYM DEH Set 1 R W 7 6 5 4 3 2 1 0 MSB LSB Global interrupt enable bit 0 Disable all interrupts processing 1 Enable all interrupts processing Fast interrupt enable bit 0 Disable fast interrupts processing 1 Enable fast interrupts processing Fast interrupt level selection bits 0 ...

Page 127: ...terrupt level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH Set 1 R W 7 6 5 4 3 2 1 0 MSB LSB IRQ1 IRQ2...

Page 128: ...ic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 Group A IRQ0 IRQ1 Group B IRQ2 IRQ3 IRQ4 Group C IRQ5 IRQ6 IRQ7 IPR Group B IPR Group C IRQ2 B1 IRQ4 B2 IRQ3 B22 B21 IRQ5 C1 IRQ7 C2 IRQ6 C22 C21 IPR Group A IRQ1 A2 IRQ0 A1 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1...

Page 129: ...p A 0 IRQ0 IRQ1 1 IRQ1 IRQ0 Subgroup B 0 IRQ3 IRQ4 1 IRQ4 IRQ3 Group C 0 IRQ5 IRQ6 IRQ7 1 IRQ6 IRQ7 IRQ5 Subgroup C 0 IRQ6 IRQ7 1 IRQ7 IRQ6 Group B 0 IRQ2 IRQ3 IRQ4 1 IRQ3 IRQ4 IRQ2 Group priority 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Undefined B C A A B C B A C C A B C B A A C B Undefined D7 D4 D1 Figure 5 8 Interrupt Priority Register IPR ...

Page 130: ... register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it...

Page 131: ...iced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software The service routine must clear the approp...

Page 132: ...lly enabled EI SYM 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one levels are currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The CPU then initiates a...

Page 133: ...gister IMR value to the stack PUSH IMR 2 Load the IMR register with a new mask value that enables only the higher priority interrupt 3 Execute an EI instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack PO...

Page 134: ... PC are swapped 2 The FLAG register values are written to the FLAGS FLAGS prime register 3 The fast interrupt status bit in the FLAGS register is set 4 The interrupt is serviced 5 Assuming that the fast interrupt status bit is set when the fast interrupt service routine ends the instruction pointer and PC values are swapped back 6 The content of FLAGS FLAGS prime is copied automatically back to th...

Page 135: ...addressing rotate and shift operations DATA TYPES The SAM8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit addres...

Page 136: ...ent LDEI dst src Load external data memory and increment LDCI dst src Load program memory and increment LDEPD dst src Load external data memory with pre decrement LDCPD dst src Load program memory with pre decrement LDEPI dst src Load external data memory with pre increment LDCPI dst src Load program memory with pre increment LDW dst src Load word POP dst Pop from stack POPUD dst src Pop user stac...

Page 137: ...t src Add with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ...

Page 138: ...ual CPIJNE dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BI...

Page 139: ...RR dst Rotate right RRC dst Rotate right through carry SRA dst Shift right arithmetic SWAP dst Swap nibbles CPU Control Instructions CCF Complement carry flag DI Disable interrupts EI Enable interrupts IDLE Enter Idle mode NOP No operation RCF Reset carry flag SB0 Set bank 0 SB1 Set bank 1 SCF Set carry flag SRP src Set register pointers SRP0 src Set register pointer 0 SRP1 src Set register pointe...

Page 140: ...ster can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then ...

Page 141: ...ing logic operations D Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and cannot be used as a test condition H Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit...

Page 142: ...ic zero 1 Set to logic one Set or cleared according to operation Value is unaffected x Value is undefined Table 6 3 Instruction Set Symbols Symbol Description dst Destination operand src Source operand Indirect register address prefix PC Program counter IP Instruction pointer FLAGS Flags register D5H RP Register pointer Immediate operand or register address prefix H Hexadecimal number suffix D Dec...

Page 143: ...ddr addr 0 254 even number only Ir Indirect working register only Rn n 0 15 IR Indirect register or indirect working register Rn or reg reg 0 255 n 0 15 Irr Indirect working register pair only RRp p 0 2 14 IRR Indirect register pair or indirect working register pair RRp or reg reg 0 254 even only where p 0 2 14 X Indexed addressing mode reg Rn reg 0 255 n 0 15 XS Indexed short offset addressing mo...

Page 144: ...IR1 TCM r1 r2 TCM r1 Ir2 TCM R2 R1 TCM IR2 R1 TCM R1 IM BAND r0 Rb I 7 PUSH R2 PUSH IR2 TM r1 r2 TM r1 Ir2 TM R2 R1 TM IR2 R1 TM R1 IM BIT r1 b B 8 DECW RR1 DECW IR1 PUSHUD IR1 R2 PUSHUI IR1 R2 MULT R2 RR1 MULT IR2 RR1 MULT IM RR1 LD r1 x r2 B 9 RL R1 RL IR1 POPUD IR2 R1 POPUI IR2 R1 DIV R2 RR1 DIV IR2 RR1 DIV IM RR1 LD r2 x r1 L A INCW RR1 INCW IR1 CP r1 r2 CP r1 Ir2 CP R2 R1 CP IR2 R1 CP R1 IM L...

Page 145: ...inued OPCODE MAP LOWER NIBBLE HEX 8 9 A B C D E F U 0 LD r1 R2 LD r2 R1 DJNZ r1 RA JR cc RA LD r1 IM JP cc DA INC r1 NEXT P 1 ENTER P 2 EXIT E 3 WFI R 4 SB0 5 SB1 N 6 IDLE I 7 STOP B 8 DI B 9 EI L A RET E B IRET C RCF H D SCF E E CCF X F LD r1 R2 LD r2 R1 DJNZ r1 RA JR cc RA LD r1 IM JP cc DA INC r1 NOP ...

Page 146: ...ote Z Zero Z 1 1110 note NZ Not zero Z 0 1101 PL Plus S 0 0101 MI Minus S 1 0100 OV Overflow V 1 1100 NOV No overflow V 0 0110 note EQ Equal Z 1 1110 note NE Not equal Z 0 1001 GE Greater than or equal S XOR V 0 0001 LT Less than S XOR V 1 1010 GT Greater than Z OR S XOR V 0 0010 LE Less than or equal Z OR S XOR V 1 1111 note UGE Unsigned greater than or equal C 0 0111 note ULT Unsigned less than ...

Page 147: ...or fast referencing The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution t...

Page 148: ... occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Examples Give...

Page 149: ...ds are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if a carry from the low order nibble occurred Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 R R 6 05 R IR opc dst src 3 6 06 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH ADD R1 R2 R1 15H R2 03H AD...

Page 150: ...et cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 R R 6 55 R IR opc dst src 3 6 56 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH AND R1 R2 R1 02H R2 03H AND R1 R2 R1 02H R2 03H AND 01H 02H Register 01H 01H register 02H 03H AND 01H 02H Regist...

Page 151: ...d H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst b 0 src 3 6 67 r0 Rb opc src b 1 dst 3 6 67 Rb r0 NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H and register 01H 05H BAND R1 01H 1 R1 06H register 01H 05H BAND 01H 1 R1...

Page 152: ...ed Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst b 0 src 3 6 17 r0 Rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H and register 01H 01H BCP R1 01H 1 R1 07H register 01H 01H If destination working register R1 contains the value 07H 00000111B and th...

Page 153: ...Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst b 0 2 4 57 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITC R1 1 R1 05H If working register R1 contains the value 07H 00000111B the statement BITC R1 1 complements bit one of the destination...

Page 154: ...ags are affected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst b 0 2 4 77 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITR R1 1 R1 05H If the value of working register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination r...

Page 155: ...e affected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst b 1 2 4 77 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITS R1 3 R1 0FH If working register R1 contains the value 07H 00000111B the statement BITS R1 3 sets bit three of the destination regi...

Page 156: ...e second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit Examples Given R1 07H and register 01H 03H BOR R1 01H 1 R1 07H register 01H 03H BOR 01H 2 R1 Register 01H 07H R1 07H In the first example destination working register R1 contains the value 07H 00000111B and source register 01H the value...

Page 157: ... flags are affected Format Note 1 Bytes Cycles Opcode Hex Addr Mode dst src opc src b 0 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRF SKIP R1 3 PC jumps to SKIP location If working register R1 contains the value 07H 00000111B the statement ...

Page 158: ...ags are affected Format Note 1 Bytes Cycles Opcode Hex Addr Mode dst src opc src b 1 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 00000111B the statement BTJRT SKIP R1 1 tests bit one...

Page 159: ...Hex Addr Mode dst src opc dst b 0 src 3 6 27 r0 Rb opc src b 1 dst 3 6 27 Rb r0 NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H 00000111B and register 01H 03H 00000011B BXOR R1 01H 1 R1 06H register 01H 03H BXOR 01H 2 R1 Register 01H 07H R1 0...

Page 160: ...that follows the instruction CALL RR0 SP 0000H 0000H 1AH 0001H 49H CALL 40H SP 0000H 0000H 1AH 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location 0000H The PC is then loaded with the value 3521H the address o...

Page 161: ...lue of the carry flag is changed to logic zero if C 0 the value of the carry flag is changed to logic one Flags C Complemented No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 EF Example Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register 0D5H changing its value from logic zero to logic one ...

Page 162: ...Addr Mode dst opc dst 2 4 B0 R 4 B1 IR Examples Given Register 00H 4FH register 01H 02H and register 02H 5EH CLR 00H Register 00H 00H CLR 01H Register 01H 02H register 02H 00H In Register R addressing mode the statement CLR 00H clears the destination register 00H value to 00H In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to 00...

Page 163: ...ted H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 60 R 4 61 IR Examples Given R1 07H and register 07H 0F1H COM R1 R1 0F8H COM R1 R1 07H register 07H 0EH In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and vice versa leaving the value 0F8H 11111...

Page 164: ...r 6 A3 r lr opc src dst 3 6 A4 R R 6 A5 R IR opc dst src 3 6 A6 R IM Examples 1 Given R1 02H and R2 03H CP R1 R2 Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S...

Page 165: ...gs are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst RA 3 12 C2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Example Given R1 02H R2 03H and register 03H 02H CPIJE R1 R2 SKIP R2 04H PC jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H ...

Page 166: ...ormat Bytes Cycles Opcode Hex Addr Mode dst src opc src dst RA 3 12 D2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Example Given R1 02H R2 03H and register 03H 04H CPIJNER1 R2 SKIP R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value 03H and general register 03 the value 04H The s...

Page 167: ...ruction Carry Before DA Bits 4 7 Value Hex H Flag Before DA Bits 0 3 Value Hex Number Added to Byte Carry After DA 0 0 9 0 0 9 00 0 0 0 8 0 A F 06 0 0 0 9 1 0 3 06 0 ADD 0 A F 0 0 9 60 1 ADC 0 9 F 0 A F 66 1 0 A F 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 SUB 0 0 8 1 6 F FA 06 0 SBC 1 7 F 0 0 9 A0 60 1 1 6 F 1 6 F 9A 66 1 Flags C Set if there was a carry fro...

Page 168: ...BCD values 15 and 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic 0 0 0 1 0 1 0 1 15 0 0 1 0 0 1 1 1 27 0 0 1 1 1 1 0 0 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 42 Assuming the same values...

Page 169: ...verflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 00 R 4 01 IR Examples Given R1 03H and register 03H 10H DEC R1 R1 02H DEC R1 Register 03H 0FH In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DE...

Page 170: ...ormat Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 8 80 RR 8 81 IR Examples Given R0 12H R1 34H R2 30H register 30H 0FH and register 31H 21H DECW RR0 R0 12H R1 33H DECW R2 Register 30H 0FH register 31H 20H In the first example destination register R0 contains the value 12H and register R1 the value 34H The statement DECW RR0 addresses R0 and the following operand R1 as a 16 bit word and decreme...

Page 171: ... set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 8F Example Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pendin...

Page 172: ...t if MSB of quotient 1 cleared otherwise V Set if quotient is 28 or if divisor 0 cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Examples Given R0 10H R1 03H R2 40H register 40H 80H DIV RR0 R2 R0 03H R1...

Page 173: ...rking register being used as a counter should be set at the one of location 0C0H to 0CFH with SRP SRP0 or SRP1 instruction Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst r opc dst 2 8 jump taken rA RA 8 no jump r 0 to F Example Given R1 02H and LOOP is the label of a relative address SRP 0C0H DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many ca...

Page 174: ... an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the EI instruction Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 9F Example Given SYM 00H EI If the SYM register contains the value 00H that is if interrupts are currently disabled the statement EI sets the SYM register to 01H enabling ...

Page 175: ... is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 1F Example The diagram below shows one example of how to use an ENTER statement 0050 IP 0022 SP 22 Data Address Data 0040 PC 40 41 42 43 Enter Address H Address L Address H Address Data 1F 01 10 Memory 0043 IP 0020 SP ...

Page 176: ...struction pointer is then loaded into the program counter and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 internal stack 2F 16 internal stack Example The diagram below shows one example of how to use an EXIT statement 0050 IP 0022 SP Address Data 0040 PC Address Data Memory 0052 IP 0022 SP Address Data 0060 PC Address Data Memor...

Page 177: ...LE instruction must be immediately followed by at least three NOP instructions This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed If three or more NOP instructons are not used after IDLE instruction leakage current could be flown because of the floating state in the internal bus Flags No flags are affected Format Bytes Cycles Opcode Hex Addr M...

Page 178: ...code Hex Addr Mode dst dst opc 1 4 rE r r 0 to F opc dst 2 4 20 R 4 21 IR Examples Given R0 1BH register 00H 0CH and register 1BH 0FH INC R0 R0 1CH INC 00H Register 00H 0DH INC R0 R0 1BH register 01H 10H In the first example if destination working register R0 contains the value 1BH the statement INC R0 leaves the value 1CH in that same register The next example shows the effect an INC instruction ...

Page 179: ... R0 1AH R1 02H register 02H 0FH and register 03H 0FFH INCW RR0 R0 1AH R1 03H INCW R1 Register 02H 10H register 03H 00H In the first example the working register pair RR0 contains the value 1AH in register R0 and 02H in register R1 The statement INCW RR0 increments the 16 bit destination by one leaving the value 03H in register R1 In the second example the statement INCW R1 uses Indirect Register I...

Page 180: ...ernal stack IRET Fast Bytes Cycles Opcode Hex opc 1 6 BF Example In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped This causes the PC to jump to address 100H and the IP to keep the return address The last instruction in the service routine norma...

Page 181: ...IRR NOTES 1 The 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 In the first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Examples Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL_W LABEL_W 1000H PC 1000H JP 00H PC 0120H The first example shows a conditional JP A...

Page 182: ... 127 128 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement Flags No flags are affected Format 1 Bytes Cycles Opcode Hex Addr Mode dst cc opc dst 2 6 ccB RA cc 0 to F NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits Example Given The carry flag 1 and LABEL_X ...

Page 183: ...n The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src dst opc src 2 4 rC r IM 4 r8 r R src opc dst 2 4 r9 R r r 0 to F opc dst src 2 4 C7 r lr 4 D7 Ir r opc src dst 3 6 E4 R R 6 E5 R IR opc dst src 3 6 E6 R IM 6 D6 IR IM opc src dst 3 6 F5 IR R opc dst src x 3 6 87 r x r opc src dst x 3 6 97 x r r ...

Page 184: ...01H R0 20H register 01H 20H LD 01H R0 Register 01H 01H R0 01H LD R1 R0 R1 20H R0 01H LD R0 R1 R0 01H R1 0AH register 01H 0AH LD 00H 01H Register 00H 20H register 01H 20H LD 02H 00H Register 02H 20H register 00H 01H LD 00H 0AH Register 00H 0AH LD 00H 10H Register 00H 01H register 01H 10H LD 00H 02H Register 00H 01H register 01H 02 register 02H 02H LD R0 LOOP R1 R0 0FFH R1 0AH LD LOOP R0 R1 Register...

Page 185: ...nstruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R0 06H and general register 00H 05H LDB R0 00H 2 R0 07H register 00H 05H LDB 00H 0 R0 R0 06H register 00H 04H In the first example destination working register R0 contains the value 06H and the source general register 00H the value 05H The ...

Page 186: ...c dst src XS 3 12 E7 r XS rr 4 opc src dst XS 3 12 F7 XS rr r 5 opc dst src XLL XLH 4 14 A7 r XL rr 6 opc src dst XLL XLH 4 14 B7 XL rr r 7 opc dst 0000 DAL DAH 4 14 A7 r DA 8 opc src 0000 DAL DAH 4 14 B7 DA r 9 opc dst 0001 DAL DAH 4 14 A7 r DA 10 opc src 0001 DAL DAH 4 14 B7 DA r NOTES 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 For formats 3 a...

Page 187: ...ogram memory location 0105H 01H RR2 R0 6DH R2 01H R3 04H LDE R0 01H RR2 R0 contents of external data memory location 0105H 01H RR2 R0 7DH R2 01H R3 04H LDC note 01H RR2 R0 11H contents of R0 is loaded into program memory location 0105H 01H 0104H LDE 01H RR2 R0 11H contents of R0 is loaded into external data memory location 0105H 01H 0104H LDC R0 1000H RR2 R0 contents of program memory location 110...

Page 188: ...ource are unaffected LDCD references program memory and LDED references external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 10 E2 r Irr Examples Given R6 10H R7 33H R8 12H program memory location 1033H 0CDH and external data memory location 1033H 0...

Page 189: ...he source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes Irr even for program memory and odd for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 10 E3 r Irr Examples Given R6 10H R7 33H R8 12H program memory locations 1033H 0CDH and 1034H 0C5H external data memory locations 1033H 0DDH a...

Page 190: ...e destination location The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes Irr an even number for program memory and an odd number for external data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 2 14 F2 Irr r Examples Given R0 77H R6 30H and R7 00H LDCPD RR6 R0 RR6 RR...

Page 191: ...the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 2 14 F3 Irr r Examples Given R0 7FH R6 21H and R7 0FFH LDCPI RR6 R0 RR6 RR6 1 7F...

Page 192: ...H register 02H 03H and register 03H 0FH LDW RR6 RR4 R6 06H R7 1CH R4 06H R5 1CH LDW 00H 02H Register 00H 03H register 01H 0FH register 02H 03H register 03H 0FH LDW RR2 R7 R2 03H R3 0FH LDW 04H 01H Register 04H 03H register 05H 0FH LDW RR6 1234H R6 12H R7 34H LDW 02H 0FEDH Register 02H 0FH register 03H 0EDH In the second example please note that the statement LDW 00H 02H loads the contents of the s...

Page 193: ...et if MSB of the result is a 1 cleared otherwise V Cleared D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Examples Given Register 00H 20H register 01H 03H register 02H 09H register 03H 06H MULT 00H 02H Register 00H 01H register 01H 20H register 02H 09H MULT 00H 01H Register 00H 00H register 01H 0C0H MULT 00H 30H Register ...

Page 194: ...ded into the program counter The instruction pointer is then incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 10 0F Example The following diagram shows one example of how to use the NEXT instruction Data 01 10 Before After 0045 IP Address Data 0130 PC 43 44 45 Address H Address L Address H Address Data Memory 130 Routine 0043 IP Address Data 0120 PC 43 44 45 Addr...

Page 195: ...ecutes this instruction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 FF Example When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ...

Page 196: ...ed H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 R R 6 45 R IR opc dst src 3 6 46 R IM Examples Given R0 15H R1 2AH R2 01H register 00H 08H register 01H 37H and register 08H 8AH OR R0 R1 R0 3FH R1 2AH OR R0 R2 R0 37H R2 01H register 01H 37H OR 00H 01H Register 00H 3FH register 01H 37H OR 01H 00H Register 00H 08H register 01H 0BFH ...

Page 197: ...x Addr Mode dst opc dst 2 8 50 R 8 51 IR Examples Given Register 00H 01H register 01H 1BH SPH 0D8H 00H SPL 0D9H 0FBH and stack register 0FBH 55H POP 00H Register 00H 55H SP 00FCH POP 00H Register 00H 01H register 01H 55H SP 00FCH In the first example general register 00H contains the value 01H The statement POP 00H loads the contents of location 00FBH 55H into destination register 00H and then inc...

Page 198: ...pointer is then decremented Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 8 92 R IR Example Given Register 00H 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00H Register 00H 41H register 02H 6FH register 42H 6FH If general register 00H contains the value 42H and register 42H the value 6FH the statement POPUD 02H 00H loa...

Page 199: ...The user stack pointer is then incremented Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 8 93 R IR Example Given Register 00H 01H and register 01H 70H POPUI 02H 00H Register 00H 02H register 01H 70H register 02H 70H If general register 00H contains the value 01H and register 01H the value 70H the statement POPUI 02H 00H loads the value 70H into the dest...

Page 200: ...dst opc src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Examples Given Register 40H 4FH register 4FH 0AAH SPH 00H and SPL 00H PUSH 40H Register 40H 4FH stack register 0FFH 4FH SPH 0FFH SPL 0FFH PUSH 40H Register 40H 4FH register 4FH 0AAH stack register 0FFH 0AAH SPH 0FFH SPL 0FFH In the first example if the stack pointer contains the value 0000H and general reg...

Page 201: ...ecremented stack pointer Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 3 8 82 IR R Example Given Register 00H 03H register 01H 05H and register 02H 1AH PUSHUD 00H 01H Register 00H 02H register 01H 05H register 02H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUD 00H 01H decrements the user stack pointer by...

Page 202: ...incremented user stack pointer Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 3 8 83 IR R Example Given Register 00H 03H register 01H 05H and register 04H 2AH PUSHUI 00H 01H Register 00H 04H register 01H 05H register 04H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack poin...

Page 203: ...Carry Flag RCF RCF Operation C 0 The carry flag is cleared to logic zero regardless of its previous value Flags C Cleared to 0 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 CF Example Given C 1 or 0 The instruction RCF clears the carry flag C to logic zero ...

Page 204: ...tement that is executed is the one that is addressed by the new program counter value Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 8 internal stack AF 10 internal stack Example Given SP 00FCH SP 101AH and PC 1234 RET PC 101AH SP 00FEH The statement RET pops the contents of stack pointer location 00FCH 10H into the high byte of the program counter The stack pointer then pops the...

Page 205: ...if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 90 R 4 91 IR Examples Given Register 00H 0AAH register 01H 02H and register 02H 17H RL 00H Register 00H 55H C 1 RL 01H Register 01H 02H register 02H 2EH C 0 In the first exa...

Page 206: ...e V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 10 R 4 11 IR Examples Given Register 00H 0AAH register 01H 02H and register 02H 17H C 0 RLC 00H Register 00H 54H C 1 RLC 01H Register 01H 02H register 02H 2EH C 0 In the first example if general r...

Page 207: ...metic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 E0 R 4 E1 IR Examples Given Register 00H 31H register 01H 02H and register 02H 17H RR 00H Register 00H 98H C 1 RR 01H Register 01H 02H register 02H 8BH C 1 In the first example if general register 00H contains th...

Page 208: ... V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 C0 R 4 C1 IR Examples Given Register 00H 55H register 01H 02H register 02H 17H and C 0 RRC 00H Register 00H 2AH C 1 RRC 01H Register 01H 02H register 02H 0BH C 1 In the first example if general reg...

Page 209: ...instruction clears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 4F Example The statement SB0 clears FLAGS 0 to 0 selecting bank 0 register addressing ...

Page 210: ...ag in the FLAGS register FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area of the register file Bank 1 is not implemented in some S3C8 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 5F Example The statement SB1 sets FLAGS 0 to 1 selecting bank 1 register addressing if implemented ...

Page 211: ...rflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 R ...

Page 212: ...X 6 78 SCF Set Carry Flag SCF Operation C 1 The carry flag C is set to logic one regardless of its previous value Flags C Set to 1 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 DF Example The statement SCF sets the carry flag to logic one ...

Page 213: ...red otherwise S Set if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 D0 R 4 D1 IR Examples Given Register 00H 9AH register 02H 03H register 03H 0BCH and C 1 SRA 00H Register 00H 0CD C 0 SRA 02H Register 02H 03H register 03H 0DEH C 0 In the first example if general register 00H contains the value 9AH...

Page 214: ...ermine whether to write one or both of the register pointers RP0 and RP1 Bits 3 7 of the selected register pointer are written unless both register pointers are selected RP0 3 is then cleared to logic zero and RP1 3 is set to logic one Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode src opc src 2 4 31 IM Examples The statement SRP 40H sets register pointer 0 RP0 at location 0D...

Page 215: ... operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed In application programs a STOP instruction must be immediately followed by at least three NOP instructions This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed If three or more NOP instructons are not used after STOP instruction l...

Page 216: ...rand cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 R R 6 25 R IR opc dst src 3 6 26 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH SUB R...

Page 217: ...f the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 F0 R 4 F1 IR Examples Given Register 00H 3EH register 02H 03H and register 03H 0A4H SWAP 00H Register 00H 0E3H SWAP 02H Register 02H 03H register 03H 4AH In the first example if general register 00H contains the value 3EH 00111110B the statement SWAP 00H swaps ...

Page 218: ...ise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 R R 6 65 R IR opc dst src 3 6 66 R IM Examples Given R0 0C7H R1 02H R2 12H register 00H 2BH register 01H 02H and register 02H 23H TCM R0 R1 R0 0C7H R1 02H Z 1 TCM R0 R1 R0 0C7H R1 02H register 02H 23H Z 0 TCM 00H 01H Register 00H 2BH register 01H ...

Page 219: ...cted H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 R R 6 75 R IR opc dst src 3 6 76 R IM Examples Given R0 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H TM R0 R1 R0 0C7H R1 02H Z 0 TM R0 R1 R0 0C7H R1 02H register 02H 23H Z 0 TM 00H 01H Register 00H 2BH register 01H 02H Z 0 TM 00H 01H Register 00H 2BH r...

Page 220: ... status can be released by an internal interrupt including a fast interrupt Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4n 3F n 1 2 3 Example The following sample program structure shows the sequence of operations that follow a WFI statement EI WFI Next instruction Main program Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed Enabl...

Page 221: ... reset to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 B2 r r 6 B3 r lr opc src dst 3 6 B4 R R 6 B5 R IR opc dst src 3 6 B6 R IM Examples Given R0 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H XOR R0 R1 R0 0C5H R1 02H XOR R0 R1 R0 0E4H R1 02H register 02H 23H XOR 00H 01H Register 00H 29H register 01H 02H XOR 00H 01H Regist...

Page 222: ...ster settings SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal ceramic resonator RC oscillation source or an external clock source Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 System clock control register CLKCON Oscillator control register OSCCON and STOP control register STPCON Clock o...

Page 223: ...R CIRCUITS XIN XOUT Figure 7 1 Crystal Ceramic Oscillator fx XIN XOUT Figure 7 2 External Oscillator fx XIN XOUT R Figure 7 3 RC Oscillator fx SUB OSCILLATOR CIRCUITS XTIN XTOUT 32 768 kHz VREG 104 Figure 7 4 Crystal Oscillator fxt XTIN XTOUT Figure 7 5 External Oscillator fxt ...

Page 224: ...rnal clock signal is gated to the CPU but not to interrupt structure timers and timer counters Idle mode is released by a reset or by an external or internal interrupt CPU Clock IDLE Instruction Selector 2 CLKCON 4 3 System Clock 1 1 1 4096 Frequency Dividing Circuit Stop Release Main System Oscillator Circuit Selector 1 fx fxt Stop Sub system Oscillator Circuit INT OSCCON 0 OSCCON 3 OSCCON 2 STPC...

Page 225: ...Q wake up enable bit is CLKCON 7 After the main oscillator is activated and the fxx 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed to fxx 8 fxx 2 or fxx 1 System Clock Control Register CLKCON D4H Set 1 R W LSB MSB 7 6 5 4 3 2 1 0 Not used for S3C8275X C8278X C8274X must keep always 0 Not used for S3C8275X C8278X C8274X must keep alway...

Page 226: ...reset fxx 64 is select for clock output frequency because the reset value of CLOCON 1 0 is 00b Clock Output Control Register CLOCON E8H Set 1 Bank 1 R W LSB MSB 7 6 5 4 3 2 1 0 Not used for S3C8275X C8278X C8274X must keep always 0 Clock output frequency selection bits 00 Select fxx 64 01 Select fxx 16 10 Select fxx 8 11 Select fxx 4 Figure 7 8 Clock Output Control Register CLOCON MUX fxx 64 fxx 1...

Page 227: ... oscillator can be stopped or run by setting OSCCON 2 Oscillator Control Register OSCCON E0H Set 1 Bank 0 R W LSB MSB 7 6 5 4 3 2 1 0 Not used for S3C8275X C8278X C8274X System clock selection bit 0 Main oscillator select 1 Sub oscillator select Sub oscillator control bit 0 Sub oscillator RUN 1 Sub oscillator STOP Main oscillator control bit 0 Main oscillator RUN 1 Main oscillator STOP Not used fo...

Page 228: ...ock of fx 16 and you want to switch from the fx clock to a sub clock and to stop the main clock To do this you need to set CLKCON 4 3 to 11 OSCCON 0 to 1 and OSCCON 3 to 1 simultaneously This switches the clock from fx to fxt and stops main clock oscillation The following steps must be taken to switch from a sub clock to the main clock first set OSCCON 3 to 0 to enable main clock oscillation Then ...

Page 229: ...7 6 5 4 3 2 1 0 MSB LSB STOP control bits Other values Disable STOP instruction 10100101 Enable STOP instruction NOTE Before execute the STOP instruction set this STPCON register as 10100101B Otherwise the STOP instuction will not execute as well as reset will be generated Figure 7 11 STOP Control Register STPCON ...

Page 230: ...e watchdog function basic timer is enabled Ports 0 6 are set to input mode and all pull up resistors are disabled for the I O port Peripheral control and data register settings are disabled and reset to their default hardware values The program counter PC is loaded with the program reset address in the ROM 0100H When the programmed oscillation stabilization time interval has elapsed the instructio...

Page 231: ...After RESET Register Name Mnemonic Address Bit Values After RESET Dec Hex 7 6 5 4 3 2 1 0 Locations D0H D2H are not mapped Basic timer control register BTCON 211 D3H 0 0 0 0 0 0 0 0 System clock control register CLKCON 212 D4H 0 0 0 System flags register FLAGS 213 D5H x x x x x x 0 0 Register pointer 0 RP0 214 D6H 1 1 0 0 0 Register pointer 1 RP1 215 D7H 1 1 0 0 1 Stack pointer high byte SPH 216 D...

Page 232: ...egister low byte P2CONL 235 EBH 0 0 0 0 0 0 0 0 Port 2 pull up resistor enable register P2PUR 236 ECH 0 0 0 0 0 0 0 0 Port 3 control register high byte P3CONH 237 EDH 0 0 0 0 0 0 0 0 Port 3 control register low byte P3CONL 238 EEH 0 0 0 0 0 0 0 0 Port 3 pull up resistor enable register P3PUR 239 EFH 0 0 0 0 0 0 0 0 Port 0 data register P0 240 F0H 0 0 0 0 0 0 0 0 Port 1 data register P1 241 F1H 0 0...

Page 233: ... TBCON 231 E7H 0 0 0 0 0 0 0 Clock output control register CLOCON 232 E8H 0 0 Port 4 control register high byte P4CONH 233 E9H 0 0 0 0 0 0 0 0 Port 4 control register low byte P4CONL 234 EAH 0 0 0 0 0 0 0 0 Port 5 control register high byte P5CONH 235 EBH 0 0 0 0 0 0 0 0 Port 5 control register low byte P5CONL 236 ECH 0 0 0 0 0 0 0 0 Port 6 control register P6CON 237 EDH 0 0 0 0 0 0 0 0 Locations ...

Page 234: ...ocation 0100H and 0101H Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller s current internal operating mode The external interrupts in the S3C8275X C8278X C8274X interrupt structure that can be used to release...

Page 235: ...m and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slow clock fxx 16 because CLKCON 4 and CLKCON 3 are cleared to 00B If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released When you use an interrupt to release idl...

Page 236: ...terrupts INT and P0 3 P0 7 can be used as T1CLK TAOUT TBOUT CLKOUT and BUZ 1 1 bit programmable I O port Schmitt trigger input or push pull open drain output and software assignable pull ups Alternatively P1 3 P1 7 can be used as input for external interrupts INT and P1 0 P1 2 can be used as SCK SO and SI 2 1 bit programmable I O port Input or push pull open drain output and software assignable pu...

Page 237: ...al Hex Location R W Port 0 data register P0 240 F0H Set 1 Bank 0 R W Port 1 data register P1 241 F1H Set 1 Bank 0 R W Port 2 data register P2 242 F2H Set 1 Bank 0 R W Port 3 data register P3 243 F3H Set 1 Bank 0 R W Port 4 data register P4 244 F4H Set 1 Bank 0 R W Port 5 data register P5 245 F5H Set 1 Bank 0 R W Port 6 data register P6 246 F6H Set 1 Bank 0 R W MSB S3C8275X C8278X C8274X I O Port D...

Page 238: ...the associated peripheral module Port 0 Pull up Resistor Control Register P0PUR Using the port 0 pull up resistor control register P0PUR E6H set 1 bank 0 you can configure pull up resistors to individual port 0 pins Port 0 Interrupt Control Registers EXTICONL 5 0 EXTIPND 2 0 To process external interrupts at the port 0 pins two additional control registers are provided the external interrupt contr...

Page 239: ... 6 CLKOUT P0 5 TBOUT P0 4 TAOUT N channel open drain output mode Schmitt trigger input mode Figure 9 2 Port 0 High Byte Control Register P0CONH Port 0 Control Register Low Byte P0CONL E5H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB P0 3 T1CLK P0CONL bit pair pin configuration settings 00 01 10 11 Not available P0 2 INT2 P0 1 INT1 P0 0 INT0 Schmitt trigger input mode T1CLK N channel open drain output ...

Page 240: ...sabled when the corresponding pin is selected as push pull output or alternative function Figure 9 4 Port 0 Pull up Control Register P0PUR External Interrupt Control Register Low Byte EXTICONL E9H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB P1 3 INT3 EXTICONL bit configuration settings 00 01 Enable interrupt by falling edge Disable interrupt 10 11 Enable interrupt by both falling and rising edge Enab...

Page 241: ... Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB EXTIPND bit configuration settings 0 1 Interrupt is pending when read No interrupt pending when read clear pending bit when write P0 2 INT2 P0 1 INT1 P0 0 INT0 P1 7 INT7 P1 6 INT6 P1 5 INT5 P1 4 INT4 P1 3 INT3 Figure 9 6 External Interrupt Pending Register EXTIPND ...

Page 242: ...pheral module Port 1 Pull up Resistor Control Register P1PUR Using the port 1 pull up resistor control register P1PUR E9H set 1 bank 0 you can configure pull up resistors to individual port 1 pins Port 1 Interrupt Control Registers EXTICONH EXTICONL 7 6 EXTIPND 7 3 To process external interrupts at the port 1 pins three additional control registers are provided the external interrupt control regis...

Page 243: ... P1 4 INT4 N channel open drain output mode Schmitt trigger input mode Figure 9 7 Port 1 High Byte Control Register P1CONH Port 1 Control Register Low Byte P1CONL E8H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB P1 3 INT3 P1CONL bit pair pin configuration settings 00 01 10 11 Alternative function SCK SO P1 2 SI P1 1 SO P1 0 SCK Schmitt trigger input mode SI SCK N channel open drain output mode Push pu...

Page 244: ...bled when the corresponding pin is selected as push pull output or alternative function Figure 9 9 Port 1 Pull up Control Register P1PUR External Interrupt Control Register High Byte EXTICONH F8H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB P1 7 INT7 EXTICONH bit configuration settings 00 01 Enable interrupt by falling edge Disable interrupt 10 11 Enable interrupt by both falling and rising edge Enabl...

Page 245: ...g and rising edge Enable interrupt by rising edge P0 2 INT2 P0 1 INT1 P0 0 INT0 Figure 9 11 External Interrupt Control Register Low Byte EXTICONL External Interrupt Pending Register EXTIPND F7H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB EXTIPND bit configuration settings 0 1 Interrupt is pending when read No interrupt pending when read clear pending bit when write P0 2 INT2 P0 1 INT1 P0 0 INT0 P1 7 ...

Page 246: ...ll pins to input mode You use control registers setting to select input or output mode push pull or open drain and enable the alternative functions When programming this port please remember that any alternative peripheral I O function you configure using the port 2 control registers must also be enabled in the associated peripheral module Port 2 Pull up Resistor Control Register P2PUR Using the p...

Page 247: ...channel open drain output mode Push pull output mode Figure 9 14 Port 2 Low byte Control Register P2CONL Port 2 Pull up Control Register P2PUR ECH Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB P2PUR bit configuration settings 0 1 Enable pull up resistor Disable pull up resistor P2 3 P2 2 P2 1 P2 0 P2 7 P2 6 P2 5 P2 4 NOTE A pull up resistor of port 2 is automatically disabled when the corresponding pin...

Page 248: ...ns to input mode You use control registers setting to select input or output mode push pull or open drain and enable the alternative functions When programming this port please remember that any alternative peripheral I O function you configure using the port 3 control registers must also be enabled in the associated peripheral module Port 3 Pull up Resistor Control Register P3PUR Using the port 3...

Page 249: ... Push pull output mode P3 3 SEG20 P3 2 SEG21 Figure 9 17 Port 3 Low Byte Control Register P3CONL Port 3 Pull up Control Register P3PUR EFH Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB P3PUR bit configuration settings 0 1 Enable pull up resistor Disable pull up resistor P3 1 P3 0 P3 3 P3 2 P3 5 P3 4 P3 7 P3 6 NOTE A pull up resistor of port 3 is automatically disabled when the corresponding pin is sele...

Page 250: ...r P4 0 P4 3 A reset clears the P4CONH and P4CONL registers to 00H configuring all pins to input mode You use control registers setting to select input with or without pull up or push pull output mode and enable the alternative functions When programming this port please remember that any alternative peripheral I O function you configure using the port 4 control registers must also be enabled in th...

Page 251: ...4CONL EAH Set 1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB P4 1 SEG14 P4 0 SEG15 P4CONH bit pair pin configuration settings 00 01 10 11 Push pull output mode Alternative function SEG12 SEG15 Input with pull up resistor Input mode P4 2 SEG13 P4 3 SEG12 Figure 9 20 Port 4 Low Byte Control Register P4CONL ...

Page 252: ...r P5 0 P5 3 A reset clears the P5CONH and P5CONL registers to 00H configuring all pins to input mode You use control registers setting to select input with or without pull up or push pull output mode and enable the alternative functions When programming this port please remember that any alternative peripheral I O function you configure using the port 5 control registers must also be enabled in th...

Page 253: ...e P5CONL ECH Set 1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB P5 1 SEG6 P5 0 SEG7 P5CONL bit pair pin configuration settings 00 01 10 11 Push pull output mode Alternative function SEG4 SEG7 Input with pull up resistor Input mode P5 2 SEG5 P5 3 SEG4 Figure 9 22 Port 5 Low Byte Control Register P5CONL ...

Page 254: ... clears the P6CON register to 00H configuring all pins to input mode You use control register setting to select input with or without pull up or push pull output mode and enable the alternative functions When programming this port please remember that any alternative peripheral I O function you configure using the port 6 control register must also be enabled in the associated peripheral module Por...

Page 255: ...ism in the event of a system malfunction To signal the end of the required oscillation stabilization interval after a reset or a stop mode release The functional components of the basic timer block are Clock frequency divider fxx divided by 4096 1024 128 or 16 with multiplexer 8 bit basic timer counter BTCNT set 1 bank 0 FDH read only Basic timer control register BTCON set 1 D3H read write ...

Page 256: ...tion you must write the signature code 1010B to the basic timer register control bits BTCON 7 BTCON 4 The 8 bit basic timer counter BTCNT set 1 bank 0 FDH can be cleared at any time during normal operation by writing a 1 to BTCON 1 To clear the frequency dividers for all timers input clock you write a 1 to BTCON 0 Basic Timer Control Register BTCON D3H Set 1 R W 7 6 5 4 3 2 1 0 MSB LSB Divider cle...

Page 257: ...If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt In stop mode whenever a reset or an internal and an external interrupt occurs the oscillator starts The BTCNT value th...

Page 258: ... oscillation stabilization interval until bit 4 of the basic timer counter overflows MUX fXX 4096 DIV fXX 1024 fXX 128 fXX 16 fXX Bits 3 2 Bit 0 Basic Timer Control Register Write 1010xxxxB to Disable Clear Bit 1 RESET or STOP Data Bus 8 Bit Up Counter BTCNT Read Only Start the CPU note OVF RESET u Figure 10 2 Basic Timer Block Diagram ...

Page 259: ...0H generation Timer 1 control register TACON set 1 bank 1 E6H read write FUNCTION DESCRIPTION Interval Timer Function The timer 1 module can generate an interrupt the timer 1 match interrupt T1INT T1INT belongs to the interrupt level IRQ 0 and is assigned a separate vector address F0H The T1INT pending condition should be cleared by software after IRQ 0 is serviced The T1INT pending bit must be cl...

Page 260: ...ct time interval you should write TACON 3 and TACON 0 to 10B which cleared counter and interrupt pending bit When the T1INT sub routine is serviced the pending condition must be cleared by software by writing a 0 to the timer 1 interrupt pending bit TACON 0 Timer 1 A Control Register TACON E6H Set 1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB Timer 1 interrupt enable bit 0 Disable interrupt 1 Enable interr...

Page 261: ...CON 6 4 M U X 1 8 1 64 1 256 1 512 TACON 0 TAOUT T1INT 1 1 DIV R fxt T1CLK XIN or XTIN fxx BTCON 0 TACON 2 TBCNT TACNT 16 Bit Comparator TBDATA Buffer TADATA Buffer TBDATA TADATA LSB MSB LSB MSB Match Signal T1CLR TACON 1 Match R TACON 3 Data Bus Data Bus Clear Figure 11 2 Timer 1 Block Diagram One 16 bit Mode ...

Page 262: ... match interrupt TAINT and the timer B match interrupt TBINT TAINT belongs to the interrupt level IRQ 0 and is assigned a separate vector address F0H TBINT belongs to the interrupt level IRQ 0 and is assigned a separate vector address F2H The TAINT and TBINT pending condition should be cleared by software after they are serviced In interval timer mode a match signal is generated when the counter v...

Page 263: ...nterval you should write TACON 3 TBCON 3 and TACON 0 TBCON 0 which cleared counter and interrupt pending bit When the TAINT and TBINT sub routine has been serviced the pending condition must be cleared by software by writing a 0 to the timer A and B interrupt pending bits TACON 0 or TBCON 0 Timer 1 A Control Register TACON E6H Set 1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB Timer A interrupt enable bit 0...

Page 264: ...when read Clear pending bit when write 1 Interrupt is pending when read No effect when write Timer B counter operating enable bit 0 Disable counting operation 1 Enable counting operation Timer B counter clear bit 0 No affect 1 Clear the timer B counter when write Not used for S3C8275X C8278X C8274X Timer B clock selection bits 000 fxx 512 001 fxx 256 010 fxx 64 011 fxx 8 100 fxt sub clock Others N...

Page 265: ...N 6 4 M U X 1 8 1 64 1 256 1 512 TACON 0 TAOUT TAINT DIV R fxt T1CLK XIN or XTIN fxx BTCON 0 TACON 2 8 Bit Comparator TADATA Buffer TADATA Register LSB MSB LSB MSB Match Signal TACLR TACON 1 Match R TACON 3 Data Bus Data Bus TACNT 8 Bit Up Counter Clear 1 1 Figure 11 5 Timer A Block Diagram Two 8 bit Timers Mode ...

Page 266: ...ode TACON 7 0 Timer B TBCON 6 4 M U X TBCON 0 TBINT DIV R fxt XIN or XTIN fxx BTCON 0 TBCON 2 8 Bit Comparator TBDATA Buffer TBDATA Register LSB MSB LSB MSB Match Signal TBCLR TBCON 1 Match R TBCON 3 Data Bus Data Bus TBCNT 8 Bit Up Counter Clear TBOUT Figure 11 6 Timer B Block Diagram Two 8 bit Timers Mode ...

Page 267: ...speed selection bits WTCON 3 2 The watch timer can generate a steady 0 5 kHz 1 kHz 2 kHz or 4 kHz signal to BUZ output pin for Buzzer By setting WTCON 3 and WTCON 2 to 11b the watch timer will function in high speed mode generating an interrupt every 3 91 ms High speed mode is useful for timing events for program debugging sequences Also you can select watch timer clock source by setting the WTCON...

Page 268: ...on bits 00 0 5 kHz 01 1 kHz 10 2 kHz 11 4 kHz Watch Timer Control Register WTCON E1H Set 1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB Watch timer INT Enable Disable bit 0 Disable watch timer INT 1 Enable watch timer INT Watch timer interrupt pending bit 0 Interrupt request is not pending Clear pending bit when write 0 1 Interrupt request is pending Watch timer speed selection bits 00 Set watch timer inter...

Page 269: ...e Selector Circuit MUX WTCON 0 WTINT WTCON 6 fW 215 fW 214 fW 213 fW 27 fW 64 0 5 kHz fW 32 1 kHz fW 16 2 kHz fW 8 4 kHz 1 Hz fX Main clock where fx 4 19 MHz fxt Sub clock 32 768 kHz fW Watch timer frequency Clock Selector Frequency Dividing Circuit fW 32 768 kHz fxt fLCD 2048 Hz WTCON 7 WTCON 0 Pending Bit 8 BUZ P0 7 fx 128 Figure 12 2 Watch Timer Circuit Diagram ...

Page 270: ...D operating power supply pins VLC0 VLC2 LCD bias by Internal External register The LCD control register LCON is used to turn the LCD display on or off to select LCD clock frequency to select bias and duty and switch the current to the dividing resistor for the LCD display Data written to the LCD display RAM can be automatically transferred to the segment signal pins without program control When a ...

Page 271: ...2 LCD CIRCUIT DIAGRAM Data BUS Port Latch LCON LCD Display RAM 200H 20FH SEG Port Driver LCD Voltage Controller SEG0 P5 7 SEG15 P4 0 SEG16 P3 7 SEG31 P2 0 COM Port Driver Timing Controller COM3 P6 3 COM2 P6 2 COM0 P6 0 fLCD VLC0 VLC1 VLC2 Figure 13 2 LCD Circuit Diagram ...

Page 272: ...ion that are not used for LCD display can be allocated to general purpose use COM0 COM1 COM2 COM3 b0 b4 b0 b4 b0 b4 b0 b4 b0 b4 b1 b5 b2 b6 b3 b7 b1 b5 b2 b6 b3 b7 b1 b5 b2 b6 b3 b7 b1 b5 b2 b6 b3 b7 b1 b5 b2 b6 b3 b7 200H 201H 202H 203H 204H b0 b4 b0 b4 b0 b4 b1 b5 b2 b6 b3 b7 b1 b5 b2 b6 b3 b7 b1 b5 b2 b6 b3 b7 20DH 20EH 20FH SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG26 SEG27 SEG28 SE...

Page 273: ...l determines the frequency of COM signal scanning of each segment output This is also referred as the LCD frame frequency Since the LCD clock is generated by watch timer clock fw The watch timer should be enabled when the LCD display is turned on LCD Control Register LCON E0H Set 1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB Internal LCD dividing register enable bit 0 Enable internal LCD dividing resistors...

Page 274: ...s S3C8275X C8278X C8274X LCON 0 VLC0 VLC2 VLC1 VSS VDD R R R VLCD LCON 7 0 Enable internal resistors Static and 1 3 Bias 1 2 Bias LCON 0 VLC0 VLC2 VLC1 VSS VDD R R R VLCD LCON 7 0 Enable internal resistors LCON 0 VLC0 VLC2 VLC1 VSS VDD R R R VLCD LCON 7 1 Disable internal resistors Voltage Dividing Resistor Adjustment S3C8275X C8278X C8274X S3C8275X C8278X C8274X Figure 13 5 Internal Voltage Divid...

Page 275: ...elected SEGMENT SEG SIGNALS The 32 LCD segment signal pins are connected to corresponding display RAM locations at page 2 Bits of the display RAM are synchronized with the common signal output pins When the bit value of a display RAM location is 1 a select signal is sent to the corresponding segment pin When the display bit is 0 a no select signal to the corresponding segment pin 1 Frame Select No...

Page 276: ...OM SEG Vss VLC1 2 VLC 0 VLC 0 VLC1 2 VLC1 2 VLC 0 VLC1 2 VLC 0 Figure 13 7 Select No Select Signal in 1 2 Duty 1 2 Bias Display Mode FR Select Non Select 1 Frame SEG COM COM SEG VLC0 VSS VLC1 VLC2 VLC0 VSS VLC1 VLC2 VLC0 VSS VLC1 VLC2 VLC0 VLC1 VLC2 Figure 13 8 Select No Select Signal in 1 3 Duty 1 3 Bias Display Mode ...

Page 277: ... Register page 4 address B1H LD B1H 7Ah SEG2 0 1 0 1 0 1 2 3 SEG3 1 1 1 0 4 5 6 7 Data Register page 4 address B2H LD B2H 63h SEG4 1 1 0 0 0 1 2 3 SEG5 0 1 1 0 4 5 6 7 COM3 Data Register page 4 address B0H LD B0H 3Eh SEG0 0 1 1 1 0 1 2 3 SEG1 1 1 0 0 4 5 6 7 VLC2 VLC1 VLC0 VLC2 VLC1 VLC0 VLC2 VLC1 VLC0 VLC2 VLC1 VLC0 VLC2 VLC1 VLC0 VLC2 VLC1 VLC0 VLC2 VLC1 VLC0 VLC1 VLC0 VLC2 VLC2 VLC1 VLC0 VLC1 V...

Page 278: ...sure flexible data transmission rates you can select an internal or external clock source PROGRAMMING PROCEDURE To program the SIO module follow these basic steps 1 Configure the I O pins at port SCK SI SO by loading the appropriate value to the P1CONL register if necessary 2 Load an 8 bit value to the SIOCON control register to properly configure the serial I O module In this operation SIOCON 2 m...

Page 279: ...ift operation and the interrupt are disabled The selected data direction is MSB first Serial I O Module Control Register SIOCON E1H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB SIO interrupt enable bit 0 Disable SIO interrupt 1 Enable SIO interrupt SIO interrupt pending bit 0 No interrupt pending 0 Clear pending condition when write 1 Interrupt is pending SIO shift operation enable bit 0 Disable shift...

Page 280: ...ler value 1 or SCK input clock SIO Pre scaler Register SIOPS E3H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB Baud rate fXX 4 SIOPS 1 Figure 14 2 SIO Prescaler Register SIOPS SIO BLOCK DIAGRAM SIO INT Pending 3 Bit Counter Clear SIOCON 0 fxx 2 SIOPS E3H set 1 bank 0 SCK SIOCON 7 SIOCON 1 Interrupt Enable CLK SI SIOCON 3 Data Bus SO M U X 1 2 8 bit P S 8 8 Bit SIO Shift Buffer SIODATA E2H set 1 bank 0 ...

Page 281: ... DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SI SCK Figure 14 4 Serial I O Timing in Transmit Receive Mode Tx at falling SIOCON 4 0 SIO INT DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SCK Transmit Complete SI SO Set SIOCON 3 Figure 14 5 Serial I O Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 ...

Page 282: ...teria voltage can be set by the software The criteria voltage can be set by matching to one of the 3 kinds of voltage below that can be used 2 2 V 2 4 V or 2 8 V VDD reference voltage or external input level External reference voltage The BLD block works only when BLDCON 3 is set If VDD level is lower than the reference voltage selected with BLDCON 2 0 BLDCON 4 will be set If VDD level is higher B...

Page 283: ... established resistor string is selected and the VBLD is fixed in accordance with this resistor Table 15 1 shows specific VBLD of 3 levels Battery Level Detector Control Register F4H Set 1 Bank 1 R W Reset 00H 7 6 5 4 3 2 1 0 MSB LSB Not used Comparator Mux BANDGAP BLD Enable Disable BLD OUT Bias VREF VIN RBLD VBLDREF Resistor String P2CONL 1 0 VBAT NOTES 1 The reset value of BLDCON is 00H 2 VREF ...

Page 284: ...rnally instead of masked ROM The flash memory is accessed by LDC instruction and the type of sector erase and a byte programmable flash a user can program the data in the flash memory area any time you want The S3F8275X s embedded 16K byte memory has two operating features User program mode S3F8275X only Tool program mode Refer to the chapter 19 S3F8275X F8278X F8274X FLASH MCU ...

Page 285: ...tically just after the corresponding operation completed Sector erase status bit 0 Success sector erase 1 Fail sector erase Flash memory mode selection bits 0101 Programming mode 1010 Sector erase mode 0110 Hard lock mode others Not available Not used for S3F8275X Figure 16 1 Flash Memory Control Register FMCON The bit 0 of FMCON register FMCON 0 is a start bit for Erase and Hard Lock operation mo...

Page 286: ...abled because the value of FMUSR is 00000000B by reset operation If necessary to operate the flash memory you can use the user programming mode by setting the value of FMUSR to 10100101B The other value of 10100101b user program mode is disabled Flash Memory User Programming Enable Register FMUSR F1H Set 1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB Flash memory user programming enable bits 10100101 Enable...

Page 287: ...fter loading sector base address located in the target address to write data into FMSECH and FMSECL register If the next operation is also to write data you should check whether next address is located in the same sector or not It case of other sectors you must load sector address to FMSECH and FMSECL register according to the sector Flash Memory Sector Address Register High Byte FMSECH F2H Set 1 ...

Page 288: ...f you don t like to use ISP sector this area can be used as a normal program memory can be erased or programmed by LDC instruction by setting ISP disable bit 1 at the Smart Option Even if ISP sector is selected ISP sector can be erased or programmed in the Tool Program mode by Serial programming tools The size of ISP sector can be varied by settings of Smart Option You can choose appropriate ISP s...

Page 289: ...ctors by setting the ISP enable disable bit to 0 and the Reset Vector Selection bit to 0 at the Smart Option you can choose the reset vector address of CPU as shown in Table 16 3 by setting the ISP Reset Vector Address Selection bits Table 16 2 Reset Vector Address Smart Option 003EH ISP Reset Vector Address Selection Bit Bit 7 Bit 6 Bit 5 Reset Vector Address After POR Usable Area for ISP Sector ...

Page 290: ...l 128 byte sizes of program memory areas So each sector should be erased first to program a new data byte into a sector Minimum 10ms delay time for erase is required after setting sector address and triggering erase start bit FMCON 0 Sector Erase is not supported in Tool Program Modes MDS mode tool or Programming tool 0000H Sector 11 128 Byte 04FFH 0500H Sector 127 128 Byte 3F7FH Sector 126 128 By...

Page 291: ...tor erase is success or not PROGRAMMING TIP Sector Erase SB1 reErase LD FMUSR 0A5H User program mode enable LD FMSECH 10H LD FMSECL 00H Set sector address 1000H 107FH CP UserID_Code User_value Check user s ID code written by user User_value is any value by user JR NE Not_ID_Code If not equal jump to Not_ID_Code LD FMCON 10100001B Start sector erase NOP Dummy instruction this instruction must be ne...

Page 292: ...sector before programming 2 Set Flash Memory User Programming Enable Register FMUSR to 10100101B 3 Set Flash Memory Sector Register FMSECH FMSECL to sector value of write address 4 Load a flash memory upper address into upper register of pair working register 5 Load a flash memory lower address into lower register of pair working register 6 Load a transmission data into a working register 7 Check ...

Page 293: ...H 17FFH LD R3 84H LD R4 78H Temporary data CP UserID_Code User_value Check user s ID code written by user User_value is any value by user JR NE Not_ID_Code If not equal jump to Not_ID_Code LD FMCON 01010001B Start program LDC RR2 R4 Write the data to a address of same sector 1784H NOP Dummy Instruction This instruction must be needed LD FMUSR 0 User Program mode disable Not_ID_Code SB1 LD FMUSR 0 ...

Page 294: ... a flash memory lower address into lower register of pair working register 3 Load receive data from flash memory location area on LDC instruction by indirectly addressing mode PROGRAMMING TIP Reading LD R2 3H Load flash memory upper address To upper of pair working register LD R3 0 Load flash memory lower address To lower pair working register LOOP LDC R0 RR2 Read data from flash memory location B...

Page 295: ...ter tool provided by the manufacturer The Hard Lock Protection Procedure in User program Mode 1 Set Flash Memory User Programming Enable Register FMUSR to 10100101B 2 Check user s ID code written by user 3 Set Flash Memory Control Register FMCON to 01100001B 4 Set Flash Memory User Programming Enable Register FMUSR to 00000000B PROGRAMMING TIP Hard Lock Protection SB1 LD FMUSR 0A5H User Program mo...

Page 296: ...tics Data retention supply voltage in Stop mode Stop mode release timing when initiated by an external interrupt Stop mode release timing when initiated by a RESET I O capacitance A C electrical characteristics Input timing for external interrupts Input timing for RESET Serial data transfer timing BLD electrical characteristics LVR electrical characteristics Oscillation characteristics Oscillation...

Page 297: ...C to 85 C VDD 2 0 V to 3 6 V Parameter Symbol Conditions Min Typ Max Unit Operating voltage VDD fx 0 4 4 2MHz fxt 32 8kHz 2 0 3 6 V fx 0 4 8 0MHz 2 5 3 6 Input high voltage VIH1 All input pins except for VIH2 VIH3 0 7 VDD VDD V VIH2 Ports 0 1 nRESET 0 8 VDD VDD VIH3 XIN XOUT and XTIN XTOUT VDD 0 1 VDD Input low voltage VIL1 All input pins except for VIL2 VIL3 0 3 VDD V VIL2 Ports 0 1 nRESET 0 2 VD...

Page 298: ... up resistors RL1 VI 0 V VDD 3V TA 25 C Ports 0 6 40 70 100 kΩ RL2 VI 0 V VDD 3V TA 25 C nRESET 220 360 500 Oscillator feed back resistors ROSC1 VDD 3 V TA 25 C XIN VDD XOUT 0V 600 1700 3000 kΩ ROSC2 VDD 3 V TA 25 C XTIN VDD XTOUT 0 V 2000 4000 8000 LCD voltage dividing resistor RLCD TA 25 C 60 110 160 kΩ VLCD COMi voltage drop i 0 3 VDC 15 µA per common pin 120 mV VLCD SEGx voltage drop x 0 31 VD...

Page 299: ...1 12 0 25 0 µA IDD4 3 Idle mode VDD 3 3 V 0 3 V 32 kHz crystal oscillator TA 25 C OSCCON 7 1 2 0 4 0 TA 25 C 0 2 2 0 IDD5 4 Stop mode VDD 3 3 V 0 3 V TA 25 C 85 C 10 NOTES 1 Supply current does not include current drawn through internal pull up resistors LCD voltage dividing resistors the LVR block and external output current loads 2 IDD1 and IDD2 include power consumption for sub clock oscillatio...

Page 300: ...a retention supply voltage VDDDR 2 0 3 6 V Data retention supply current IDDDR Stop mode TA 25 C VDDDR 2 0 V Disable LVR block 1 µA Execution of STOP Instruction Idle Mode Basic Timer Active VDDDR Stop Mode Normal Operating Mode Data Retention Mode VDD 0 8 VDD tWAIT NOTE tWAIT is the same as 16 x 1 BT clock Figure 17 1 Stop Mode Release Timing When Initiated by an External Interrupt ...

Page 301: ...e Data Retention Mode tWAIT nRESET VDD 0 2 VDD 0 8 VDD NOTE tWAIT is the same as 16 1 BT clock Figure 17 2 Stop Mode Release Timing When Initiated by a RESET Table 17 4 Input Output Capacitance TA 25 C 85 C VDD 0 V Parameter Symbol Conditions Min Typ Max Unit Input capacitance CIN f 1 MHz unmeasured pins are connected to VSS 10 pF Output capacitance COUT I O capacitance CIO ...

Page 302: ...CK source tKCY 2 50 External SCK source 250 SI setup time to SCK high tSIK Internal SCK source 250 tKSI External SCK source 400 SI hold time to SCK high Internal SCK source 400 External SCK source 300 ns Output delay for SCK to SO tKSO Internal SCK source 250 Interrupt input High Low width tINTH tINTL All interrupt VDD 3 V 500 700 ns nRESET input Low width tRSL Input VDD 3 V 10 µs tINTH tINTL 0 8 ...

Page 303: ...C8275X F8275X C8278X F8278X C8274X F8274X 17 8 nRESET tRSL 0 2 VDD Figure 17 4 Input Timing for RESET tKH tKL 0 2VDD SCK tKCY 0 8VDD 0 8VDD 0 2VDD tSIK tKSI SI SO tKSO Output Data Figure 17 5 Serial Data Transfer Timing ...

Page 304: ...age of BLD V BLDCON 2 0 000b 101b 011b 10 100 mV BLD circuit response time TB Fw 32 768 kHz 1 ms Table 17 7 LVR Low Voltage Reset Electrical Characteristics TA 25 C Parameter Symbol Conditions Min Typ Max Unit Voltage of LVR VLVR TA 25 C 2 0 2 2 2 4 V VDD voltage rising time tR 10 µs VDD voltage off time tOFF 0 5 s Hysteresis voltage of LVR V 10 100 mV Current consumption IDDPR VDD 3 3 V 70 120 µA...

Page 305: ...illator XIN C1 XOUT Main oscillation frequency 2 5 V 3 6 V 0 4 8 2 0 V 3 6 V 0 4 4 2 External clock XIN XOUT XIN input frequency 2 5 V 3 6 V 0 4 8 2 0 V 3 6 V 0 4 4 2 RC oscillator XIN XOUT R Frequency 3 3 V 0 4 1 MHz Table 17 9 Sub Oscillation Characteristics TA 25 C to 85 C Oscillator Clock Configuration Parameter Test Condition Min Typ Max Units Crystal XTIN C1 XTOUT VREG 104 Sub oscillation fr...

Page 306: ... VDD 2 0 V to 3 6 V Oscillator Test Condition Min Typ Max Unit Crystal fx 1 MHz 40 ms Ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range 10 ms External clock XIN input high and low width tXH tXL 62 5 1250 ns tX tXL VDD 0 1 V 0 1 V XIN 1 fx Figure 17 7 Clock Timing Measurement at XIN ...

Page 307: ...17 11 Sub Oscillation Stabilization Time TA 25 C to 85 C VDD 2 0 V to 3 6 V Oscillator Test Condition Min Typ Max Unit Crystal 10 s External clock XTIN input high and low width tXH tXL 5 15 µs tXTH tXTL VDD 0 1 V 0 1 V XTIN 1 fxt Figure 17 8 Clock Timing Measurement at XTIN ...

Page 308: ...rameter Symbol Conditions Min Typ Max Unit Programming time 1 Ftp 30 µs Chip erasing time 2 Ftp1 50 ms Sector erasing time 3 Ftp2 10 ms Data access time FtRS 25 ns Number of writing erasing FNwe 10 000 4 Times NOTES 1 The programming time is the time during which one byte 8 bit is programmed 2 The chip erasing time is the time during which all 16K byte block is erased 3 The sector erasing time is ...

Page 309: ...ontroller is currently available in a 64 pin QFP and LQFP package 64 QFP 1420F 64 20 00 0 20 23 90 0 30 14 00 0 20 17 90 0 30 1 1 00 1 00 0 40 0 10 0 05 NOTE Dimensions are in millimeters 0 80 0 20 0 10 MAX 0 15 0 10 0 05 0 8 0 80 0 20 0 05 MIN 2 65 0 10 3 00 MAX 0 15 MAX Figure 18 1 64 Pin QFP Package Dimensions 64 QFP 1420F ...

Page 310: ...74X F8274X 18 2 0 08 MAX 0 09 0 20 64 LQFP 1010 64 NOTE Dimensions are in millimeters 10 00 BSC 12 00 BSC 10 00 BSC 12 00 BSC 1 0 50 BSC 0 7 0 45 0 75 0 10 0 05 1 40 0 05 1 60 MAX 0 20 0 07 0 03 Figure 18 2 64 Pin LQFP Package Dimensions 64 LQFP 1010 ...

Page 311: ...tead of masked ROM The Flash ROM is accessed by serial data format The S3F8275X F8278X F8274X is fully compatible with the S3C8275X C8278X C8274X both in function and in pin configuration Because of its simple programming requirements the S3F8275X F8278X F8274X is ideal for use as an evaluation chip for the S3C8275X C8278X C8274X NOTE This chapter is about the Tool Program Mode of Flash MCU If you...

Page 312: ...1 SEG23 P3 0 SEG24 P2 7 SEG25 P2 6 SEG26 P2 5 SEG27 P2 4 SEG28 P2 3 SEG29 P2 2 SEG30 P2 1 SEG31 P2 0 VBLDREF P1 7 INT7 SEG0 P5 7 COM0 P6 0 COM1 P6 1 COM2 P6 2 COM3 P6 3 VLC0 SDAT VLC1 SCLK VLC2 VDD VDD VSS VSS XOUT XIN VPP TEST XTIN XTOUT nRESET nRESET VREG P0 0 INT0 P0 1 INT1 SEG1 P5 6 SEG2 P5 5 SEG3 P5 4 SEG4 P5 3 SEG5 P5 2 SEG6 P5 1 SEG7 P5 0 SEG8 P4 7 SEG9 P4 6 SEG10 P4 5 SEG11 P4 4 SEG12 P4 3...

Page 313: ... SEG26 P2 5 SEG27 P2 4 SEG28 P2 3 SEG29 P2 2 SEG30 P2 1 SEG31 P2 0 VBLDREF P1 7 INT7 SEG0 P5 7 COM0 P6 0 COM1 P6 1 COM2 P6 2 COM3 P6 3 VLC0 SDAT VLC1 SCLK VLC2 VDD VDD VSS VSS XOUT XIN VPP TEST XTIN XTOUT nRESET nRESET V REG P0 0 INT0 P0 1 INT1 P0 2 INT2 P0 3 T1CLK P0 4 TAOUT P0 5 TBOUT P0 6 CLKOUT P0 7 BUZ P1 0 SCK P1 1 SO P1 2 SI P1 3 INT3 P1 4 INT4 P1 5 INT5 P1 6 INT6 SEG1 P5 6 SEG2 P5 5 SEG3 P...

Page 314: ...for Flash ROM cell reading writing 3 3V is applied in Flash reading writing mode because internal block makes 12 5V So TEST pin must be connected to VDD nRESET nRESET 16 I Chip initialization VDD VSS VDD VSS 9 10 I Power supply pin for logic circuit VDD should be tied to 3 3 V during programming Table 19 2 Comparison of S3F8275X F8278X F8274X and S3C8275X C8278X C8274X Features Characteristic S3F8...

Page 315: ...operating mode read write or read protection is selected according to the input signals to the pins listed in Table 19 3 below Table 19 3 Operating Mode Selection Criteria VDD VPP TEST REG MEM Address A15 A0 R W Mode 3 3 V 3 3 V 0 0000H 1 Flash ROM read 12 5 V 0 0000H 0 Flash ROM program 12 5 V 1 0E3FH 0 Flash ROM read protection NOTES 1 The VPP Test pin must be connected to VDD S3F8275X only 2 0 ...

Page 316: ...N 7 1 12 0 25 0 µA IDD4 3 Idle mode VDD 3 3 V 0 3 V 32 kHz crystal oscillator TA 25 C OSCCON 7 1 2 0 4 0 IDD5 4 Stop mode VDD 3 3V 0 3 V TA 25 C 0 2 2 0 TA 25 C 85 C 10 NOTES 1 Supply current does not include current drawn through internal pull up resistors LCD voltage dividing resistors the LVR block and external output current loads 2 IDD1 and IDD2 include power consumption for sub clock oscilla...

Page 317: ...ASH MCU 19 7 2 MHz 6 25 kHz main 8 2 kHz sub 2 4 Supply Voltage V Instruction Clock 1 4n x oscillator frequency n 1 2 8 16 1 05 MHz Instruction Clock 8 MHz 4 2 MHz fx Main Sub oscillation frequency 2 5 3 6 400 kHz main 32 8 kHz sub 3 1 Figure 19 3 Operating Voltage Range ...

Page 318: ...msung Arrangeable Microcontroller SAM Assembler SAMA is a universal assembler and generates object code in standard hexadecimal format Assembled program code includes the object code that is used for ROM data and required SMDS program control data To assemble programs SAMA requires a source file and an auxiliary definition DEF file with device specific information SASM88 The SASM88 is a relocatabl...

Page 319: ... 20 2 BUS SMDS2 RS 232C POD Probe Adapter PROM OTP Writer Unit RAM Break Display Unit Trace Timer Unit SAM8 Base Unit Power Supply Unit IBM PC AT or Compatible TB8275 8 4 Target Board EVA Chip Target Application System Figure 20 1 SMDS Product Configuration SMDS2 ...

Page 320: ...o User_VCC OFF ON J101 J102 1 39 2 40 25 RESET 7411 IDLE STOP 1 41 79 42 80 40 pin connector 40 pin connector 160 QFP S3E8270 EVA Chip 100 pin connector Smart Option SMDS2 SMDS2 41 80 SW1 High S3F8275 Low S3F8278 4 High External Low Internal Device Selection Select Smart Option Source 81 120 121 160 1 40 JP6 MDS XTAL V DD V LC0 V LC1 V LC2 External LCD Bias Y1 sub clock X TAL Figure 20 2 TB8275 8 ...

Page 321: ...s VCC only to the target board evaluation chip The target system must have its own power supply NOTE The following symbol in the To User_Vcc Setting column indicates the electrical short off configuration Table 20 2 Main clock Selection Settings for TB8275 8 4 Main Clock Settings Operating Mode Comments XIN XTAL MDS No Connection SMDS2 SMDS2 100 Pin Connector EVA Chip S3E8270 XIN XOUT Set the XI s...

Page 322: ...mart Option Source Target System TB8275 8 4 The Smart Option is selected by internal smart option area 003EH 003FH of ROM But this selection is not available Table 20 4 Smart Option Switch Settings for TB8275 8 4 Smart Option Settings Comments B0 B1 B2 B3 B4 B5 B6 B7 B8 Smart Option Low 0 High 1 SW1 The Smart Option is selected by this switch when the Smart Option source is selected by external Th...

Page 323: ...th TB8278 4 SMDS2 SELECTION SAM8 In order to write data into program memory that is available in SMDS2 the target board should be selected to be for SMDS2 through a switch as follows Otherwise the program memory writing function is not available Table 20 6 The SMDS2 Tool Selection Setting JP2 Setting Operating Mode SMDS2 SMDS2 JP2 Target System R W R W SMDS2 IDLE LED The Yellow LED is ON when the ...

Page 324: ...45 47 49 51 53 55 57 59 61 63 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 SEG0 P5 7 COM1 P6 1 COM3 P6 3 VLC1 VDD N C TEST N C VREG INT1 P0 1 T1CLK P0 3 TBOUT P0 5 BUZ P0 7 SO P1 1 INT3 P1 3 INT5 P1 5 N C N C N C N C SEG31 P2 0 VBLDREF SEG29 P2 2 SEG27 P2 4 SEG25 P2 6 SEG23 P3 0 SEG21 P3 2 SEG19 P3 4 SEG17 P3 6 SEG15 P4 0 SEG13 P4 2 SEG11 P4 4 SEG9 P4 6 SEG7 P5 0 SEG5 P5 2 SEG3 P5 4 SEG1 P5 6 N...

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