System Address Space
A–41
Scatter-Gather TLB
Figure 1–20 Scatter-Gather Associative TLB
Each time an incoming PCI address hits in a PCI target window that has scatter-
gather translation enabled, ad<31:15> are compared with the 32KB PCI page
address in the TLB tag. If a match is found, the required 21164 page address is one of
the four items provided by the data of the matching TLB entry. PCI address
ad<14:13> selects the correct 8KB 21164 page from the four pages fetched.
A TLB hit avoids having to look up the scatter-gather map PTEs in memory, result-
ing in improved system performance. If no match is found in the TLB, the scatter-
gather map lookup is performed and four PTE entries are fetched and written over an
existing entry in the TLB.
The TLB entry to be replaced is determined by a round-robin algorithm on the
unlocked entries. Coherency of the TLB is maintained by software write transac-
tions to the SG_TBIA (scatter-gather translation buffer invalidate all) register.
The tag portion contains a DAC flag to indicate that the PCI tag address <31:15>
corresponds to a 64-bit DAC address. Only one bit is required instead of the high-
order PCI address bits <39:32> because only one window is assigned to a DAC
cycle, and the window-hit logic has already performed a comparison of the high-
order bits with the PCI DAC base register. Figure 1–21 shows the entire translation
from PCI address to physical address on a window that implements scatter-gather
DAC
Cycle
PCI
Address
<31:15>
8KB CPU Page Address
Hit
Physical Memory
Dword Address
Memory Page
Address<32:13>
PCI
Address<12:2>
PCI Address<14:13>
Index
D A T A
TAG
LJ04276A.AI4
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V